"A Configurable Memory Architecture With Built In Testing Mechanism"

Abstract: This invention relates to configurable memory architecture with built-in testing mechanism integrated in said memory to support very efficient buit-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionally of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. This invention incorporates structured DFT technique to detect all these failure separately.

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