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DESCRIPTION
Title of Invention:
A/D CONVERTER, SOLID-STATE IMAGE PICKUP DEVICE AND DRIVING
METHOD OF THE SAME, AND ELECTRONIC APPARATUS
Technical Field
[0001] The present technology relates to an A/D converter, a solid-state image
pickup device and a method of driving the same, and an electronic apparatus, and more
specifically relates to an A/D converter, a solid-state image pickup device and a
method of driving the same, and an electronic apparatus which are capable of reducing
power consumption while reducing a circuit size.
Background Art
[0002] In related art, an image sensor performs CDS (Correlated Double Sampling)
processing in which A/D (Analog-to-Digital) conversion is performed on reset
components and signal components in each vertical column of pixels, and each of
differences between the rest components and the signal components is determined to
reduce noise.
[0003] In the CDS processing, for example, a count value of the reset component is
down-counted and held, and after that, a count value of the signal component is upcounted
from the held count value to determine a difference between the reset
component and the signal component.
[0004] On the other hand, an image sensor storing a count value in a storage element
with use of a Gray code or a phase shift code as a clock signal has been proposed (for
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example, refer to PTL 1).
Citation list
Patent Literature
[0005] [PTL 1] Japanese Unexamined Patent Application Publication No. 2009-
38726
Summary
Technical Problem
[0006] However, in a case where it is considered to perform the above-described
CDS processing in the image sensor in PTL 1, a count value of a reset component
stored in the storage element is eliminated upon reading a signal component, and a
difference between the reset component and the signal component is not allowed to be
determined.
[0007] Therefore, it is necessary to include a storage element holding the count value
of the reset component and a storage element holding the count value of the signal
component, and in this case, two groups of N-number of storage elements (that is, 2Nnumber
of storage elements) for an N-bit signal are necessary, and 2N-number of
signal lines transmitting the count values of the reset components and the signal
components to a subtracter determining each of differences between the reset
components and the signal components are necessary. Accordingly, a circuit size is
increased, and power consumption for transmission and transmission time are
increased.
[0008] Moreover, in the image sensor in PTL 1, because of a characteristic in which
the storage element holds the count value, addition and subtraction are not allowed to
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be performed in the image sensor; therefore, to achieve a configuration in which two or
more signals are added in an A/D converter, it is necessary to further include a circuit
for addition.
[0009] The present technology has been made in view of such circumstances to allow
a reduction in power consumption while reducing a circuit size.
Solution to Problem
[0010] An A/D converter according to an aspect of the present technology includes: a
comparison section comparing a reference voltage with an input voltage, the reference
voltage having a ramp waveform whose voltage value varies with time; a storage
section holding a count value in a predetermined count pattern, based on an output
signal from the comparison section; a conversion section converting the count value in
the count pattern held by the storage section into binary data; and a supply section
supplying a pulse signal corresponding to the binary data obtained by conversion in the
conversion section to a first counter.
[0011] The storage section may supply, to a second counter, a most significant bit
signal representing a most significant bit of the count value in the count pattern until
the output signal from the comparison section is reversed, and may hold lower bits
lower than the most significant bit of the count value in the count pattern when the
output signal from the comparison section is reversed.
[0012] The conversion section may convert lower bits of the count value in the count
pattern into binary data, and the supply section may supply, to the first counter, a pulse
signal corresponding to a value of each bit in the binary data of a reference signal
serving as a reference pulse signal.
[0013] The reference signal may be a pulse signal configured of n-number of pulse
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trains of 2° to 2n pulses, where the bit number of the lower bits is n, and the supply
section may supply, to the first counter, a pulse train corresponding to each bit whose
value is 1 of 0th to nth bits in the binary data of the reference signal.
[0014] The second counter may count a most significant bit of a count value in the
first counter as a carry.
[0015] The A/D converter may further include a bit mismatch prevention section
preventing a bit mismatch of the most significant bit signal supplied to the second
counter.
[0016] The count pattern may be a Gray code.
[0017] The count pattern may be a phase shift code.
[0018] A solid-state image pickup device according to an aspect of the present
technology includes: a pixel array in which a plurality of pixels performing
photoelectric conversion are arranged in a matrix; and an A/D converter provided to
every column or every plurality of columns of the pixels and converting analog signals
output from the pixels of each column into digital signals, in which the A/D converter
includes a comparison section comparing a reference voltage with an input voltage of
the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time, a storage section holding a count value in a predetermined count
pattern, based on an output signal from the comparison section, a conversion section
converting the count value in the count pattern held by the storage section into binary
data, and a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a first counter.
[0019] The storage section may supply, to a second counter, a most significant bit
signal representing a most significant bit of the count value in the count pattern until
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the output signal from the comparison section is reversed, and holds lower bits lower
than the most significant bit of the count value in the count pattern when the output
signal from the comparison section is reversed.
[0020] The conversion section may convert lower bits of the count value in the count
pattern into the binary data, and the supply section may supply, to the first counter, a
pulse signal corresponding to a value of each bit in the binary data of a reference signal
serving as a reference pulse signal.
[0021] The reference signal may be a pulse signal configured of n-number of pulse
trains of 2° to 2n pulses, where the bit number of the lower bits is n, and the supply
section may supply, to the first counter, a pulse train corresponding to each bit whose
value is 1 of 0th to nth bits in the binary data of the reference signal.
[0022] The second counter may count a most significant bit of a count value in the
first counter as a carry.
[0023] The solid-state image pickup device may further include a clock generation
section generating a clock signal; and an input section inputting a count value in the
count pattern to the storage section, based on the clock signal.
[0024] In the solid-state image pickup device, the input section may be provided to
every plurality of the A/D converters, a clock buffer for transmitting the clock signal to
the input section provided to every plurality of the A/D converters may be provided to
every plurality of the A/D converters, and the clock buffer may transmit the reference
signal to the supply section after the output signal from the comparison section is
reversed.
[0025] The A/D converter may further include a bit mismatch prevention section
preventing a bit mismatch of the most significant bit signal supplied to the second
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counter.
[0026] The count pattern may be a Gray code.
[0027] The count pattern may be a phase shift code.
[0028] There is provided a method of driving a solid-state imaging device according
to an aspect of the present technology, the solid-state imaging device including a pixel
array in which a plurality of pixels performing photoelectric conversion are arranged in
a matrix, and an A/D converter provided to every column or every plurality of columns
of the pixels and converting analog signals output from the pixels of each column into
digital signals, the method including: a comparing step of allowing the A/D converter
to compare a reference voltage with an input voltage of the analog signal, the reference
voltage having a ramp waveform whose voltage value varies with time; a storing step
of allowing the A/D converter to hold a count value in a predetermined count pattern,
based on an output signal from the comparison section; a converting step of allowing
the A/D converter to convert the count value in the count pattern held by the storage
section into binary data; and a supplying step of allowing the A/D converter to supply
a pulse signal corresponding to the binary data obtained by conversion in the
conversion section to a counter.
[0029] There is provided an electronic apparatus according to an aspect of the
present technology provided with a solid-state image pickup device, the solid-state
image pickup device including: a pixel array in which a plurality of pixels performing
photoelectric conversion are arranged in a matrix; and an A/D converter provided to
every column or every plurality of columns of the pixels and converting analog signals
output from the pixels of each column into digital signals, in which the A/D converter
includes a comparison section comparing a reference voltage with an input voltage of
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the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time; a storage section holding a count value in a predetermined count
pattern, based on an output signal from the comparison section; a conversion section
converting the count value in the count pattern held by the storage section into binary
data; and a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a counter.
[0030] In the aspects of the present technology, a reference voltage having a ramp
waveform whose voltage value varies with time is compared with an input voltage of
an analog signal, a count value in a predetermined count pattern is held, based on an
output signal as a comparison result, the held count value in the count pattern is
converted into binary data, a pulse signal corresponding to the binary data obtained by
conversion is supplied to a counter.
Advantageous Effects of Invention
[0031] According to the aspects of the present technology, power consumption is
allowed to be reduced while reducing a circuit size.
Brief Description of Drawings
[0032] [FIG. 1] FIG. 1 is a diagram illustrating a configuration example of an
embodiment of a solid-state image pickup device to which the present technology is
applied.
[FIG. 2] FIG. 2 is a diagram illustrating a specific configuration example of a column
AD conversion circuit.
[FIG. 3] FIG. 3 is a diagram describing reference pulses and operations of BIN
selection switches.
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[FIG. 4] FIG. 4 is a diagram describing an example of masking of the reference
pulses by a BIN selection signal.
[FIG. 5] FIG. 5 is a timing chart describing an operation of the column AD
conversion circuit.
[FIG. 6] FIG. 6 is a block diagram illustrating another functional configuration
example of the solid-state image pickup device.
[FIG. 7] FIG. 7 is a block diagram illustrating still another functional configuration
example of the solid-state image pickup device.
[FIG. 8] FIG. 8 is a diagram describing another example of the reference pulses.
[FIG. 9] FIG. 9 is a diagram illustrating a configuration example of a solid-state
image pickup device with a laminate configuration.
[FIG. 10] FIG. 10 is a diagram describing a circuit layout of the solid-state image
pickup device with the laminate configuration.
[FIG. 11] FIG. 11 is a diagram illustrating a configuration example of an
embodiment of an electronic apparatus to which the present technology is applied.
Description of Embodiments
[0033] Some embodiments of the present technology will be described in detail
below referring to the accompanying drawings. It is to be noted that description will
be given in the following order.
1. Basic Application Example of Present Technology
2. Application Example with a Large Number of Columns
3. Application Example Taking Measures against Metastable
4. Others
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[0034] < 1. Basic Application Example of Present Technology>
[Configuration example of solid-state image pickup device]
FIG. 1 illustrates a configuration example of a CMOS (Complementary Metal
Oxide Semiconductor) image sensor (hereinafter simply referred to as "image sensor")
as a solid-state image pickup device to which the present technology is applied.
[0035] An image sensor 10 in FIG. 1 includes a pixel array section 12 including
pixels which are arranged in a matrix, and reads signals (analog signals) of pixels
through vertical signal lines 13 formed for respective columns along a vertical
direction (a pixel arrangement direction in a pixel column) in the drawing.
[0036] A column AD conversion circuit 14 converts an analog signal read through
the vertical signal line 13 into an N-bit digital signal, and then to output the N-bit
digital signal to an output buffer 15. Predetermined digital signal processing is
performed on the digital signal output from the output buffer 15 in a digital signal
processing circuit (not illustrated) subsequent to the output buffer 15.
[0037] A clock generation circuit 16 generates a clock signal to supply the clock
signal to a DAC (Digital Analog Converter) 17, a lower-bit Gray code generation
circuit 18, and a reference pulse generation circuit 19.
[0038] The DAC 17 generates, based on the clock signal from the clock generation
circuit 16, a reference voltage having a ramp waveform whose voltage value varies
with time, and inputs the reference voltage to the column AD conversion circuit 14.
[0039] The lower-bit Gray code generation circuit 18 is a so-called Gray code
counter, and performs counting in Gray code, based on the clock signal from the clock
generation circuit 16.
[0040] The reference pulse generation circuit 19 generates a reference pulse signal
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which will be described later, based on the clock signal from the clock generation
circuit 16, and supplies the reference pulse signal to the column AD conversion circuit
14.
[0041] Next, a configuration of the column AD conversion circuit 14 will be
described below.
[0042] The column AD conversion circuit 14 includes a comparator 31, a lower-bit
storage element 32, a carry select switch circuit 33, a higher-bit U/D CNT (Up/Down
Counter) 34, a Gray code binary conversion circuit 35, a storing operation control
circuit 36, and a lower-bit U/D CNT 37.
[0043] The comparator 31 compares the reference voltage input from the DAC 17
with a voltage (an input voltage) of the analog signal read through the vertical signal
line 13, and supplies, to the lower-bit storage element 32, an output based on a
magnitude relationship between the reference voltage and the input voltage. When
the magnitude relationship between the reference voltage and the input voltage is
reversed, the comparator 31 reverses the output.
[0044] The lower-bit storage element 32 supplies, to the higher-bit U/D CNT 34, a
most significant bit signal representing a most significant bit of a count value in Gray
code of the lower-bit Gray code generation circuit 18 through the carry select switch
circuit 33 until the output of the comparator 31 is reversed. Moreover, when the
output of the comparator 31 is reversed, the lower-bit storage element 32 holds lower
bits lower than the most significant bit of the count value by counting in Gray code,
and supplies the count values of the lower bits to the Gray code binary conversion
circuit 35.
[0045] The carry select switch circuit 33 is configured of a switch selecting a most
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significant bit signal from the lower-bit storage element 32 or a most significant bit
signal from the higher-bit U/D CNT 37 to supply the selected signal to the higher-bit
U/D CNT 34.
[0046] The higher-bit U/D CNT 34 performs counting in response to the most
significant bit signal from the carry select switch circuit 33, and holds a count value
obtained thereby. Most significant bits of a Gray code and a binary code are
identical; therefore, the higher-bit U/D CNT 34 counts the most significant bit in
binary code.
[0047] The Gray code binary conversion circuit 35 converts the count values of the
lower bits in Gray code from the lower-bit storage element 32 into binary data, and
supplies the binary data to the storing operation control circuit 36.
[0048] The storing operation control circuit 36 supplies (stores) a pulse signal
corresponding to the binary data from the Gray code binary conversion circuit 35 to
(in) the lower-bit U/D CNT 37. More specifically, for example, the storing operation
control circuit 36 supplies, to the lower-bit U/D CNT 37, a pulse signal, corresponding
to a value of each bit in the binary data from the Gray code binary conversion circuit
35, of the reference pulse signal from the reference pulse generation circuit 19. The
number of pulses in the pulse signal to be supplied to the lower-bit U/D CNT 37 is set
to be the same as a value of the binary data into which the count values in Gray code
are converted.
[0049] The lower-bit U/D CNT 37 performs counting in response to the pulse signal
from the storing operation control circuit 36, and holds a count value obtained thereby.
In other words, the lower-bit U/D CNT 37 counts the lower bits in binary code.
[0050] [Specific configuration example of column AD conversion circuit]
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Now, a specific configuration example of the column AD conversion circuit
14 in FIG. 1 will be described referring to FIG. 2. It is to be noted that the
comparator 31 is not illustrated in the column AD conversion circuit 14 in FIG. 2.
[0051] In the column AD conversion circuit 14 in FIG. 2, the lower-bit storage
element 32 is configured of n-number of storage elements 32-0 to 32-n. Respective
count values by counting in Gray code from the lower-bit Gray code generation circuit
18 are input to the respective storage elements 32-0 to 32-n.
[0052] Until the output of the comparator 31 is reversed, in a case where a carry
occurs in the count value to be input to the storage element 32-n of the count values to
be input to the storage elements 32-0 to 32-n, the above-described most significant bit
signal is supplied to the higher-bit U/D CNT 34 through the carry select switch circuit
33.
[0053] When the output of the comparator 31 is reversed, supply of the most
significant bit signal from the storage element 32-n to the higher-bit U/D CNT 34 stops,
and count values input to the storage elements 32-0 to 32-n at this time are held by the
storage elements 32-0 to 32-n, respectively. At this time, a switch of the carry select
switch circuit 33 is turned from the lower-bit storage element 32 side to the lower-bit
U/D CNT 37 side.
[0054] After that, count values GC0 to GCn in Gray code held by the storage
elements 32-0 to 32-n, respectively, are supplied to the Gray code binary conversion
circuit 35.
[0055] The Gray code binary conversion circuit 35 converts the count values GC0
to GCn in Gray code from the storage elements 32-0 to 32-n into binary data BIN0
to BINn, respectively, and supplies the binary data BIN0 to BINn to the storing
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operation control circuit 36.
[0056] The storing operation control circuit 36 in FIG. 2 is configured of BIN
selection switches SWO to SWn and an AND gate 36a.
[0057] The BIN selection switches SWO to SWn perform an ON/OFF operation in
order from the BIN selection switch SWO, and inputs, to the AND gate 36a, BIN
selection signals as output signals corresponding to values of the binary data BINO to
BINn input (supplied) to the BIN selection switches SWO to SWn, respectively.
[0058] The AND gate 36a outputs pulse trains configuring the reference pulse signal
from the reference pulse generation circuit 19 with timing of reception of the BIN
selection signals from the BIN selection switches SWO to SWn.
[0059] [Reference pulses and operations of BIN selection switches]
Now, the reference pulses and operations of the BIN selection switches will
be described referring to FIG. 3.
[0060] The reference pulse signal generated by the reference pulse generation circuit
19 is a pulse signal configured of n-number of pulse trains of 2° to 2n pulses, where the
bit number of lower bits is n. More specifically, as illustrated in the first line from the
top in FIG. 3, the reference pulse signal is a pulse signal configured of n-number of
pulse trains of 1, 2, 4, 8, ..., 2" pulses.
[0061] Moreover, as illustrated in the second and subsequent lines from the top in
FIG. 3, the BIN selection switches SWO to SWn perform the ON/OFF operation in
order from the BIN selection switch SWO. In FIG. 3, the operations of the BIN
selection switches SWO to SW3 are illustrated, and BIN selection signals
corresponding to values of the binary data BINO to BIN3 to be input to the BIN
selection switches SWO to SW3, respectively, are input to the AND gate 36a.
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[0062] It is to be noted that, as illustrated in FIG. 3, a first pulse train (of 2° (=1)
pulses) in the reference pulse signal corresponds to the operation of the BIN selection
switch SWO (BIN selection signal), and a second pulse train (of 21 (=2) pulses) in the
reference pulse signal corresponds the operation of the BIN selection switch SW1
(BIN selection signal). Likewise, a third pulse train (of 22 (=4) pulses) in the
reference pulse signal corresponds to the operation of the BIN selection switch S W_2
(BIN selection signal), and a fourth pulse train (of 23 (=8) pulses) in the reference pulse
signal corresponds to the operation of the BIN selection switch SW3 (BIN selection
signal). Thus, an (i+l)th pulse train (of 21 pulses) in the reference pulse signal
corresponds to an operation of a BIN selection switch SWi (BIN selection signal).
[0063] In other words, in the AND gate 36a, n-number of pulse trains in the
reference pulse signal pass through or are masked, based on ON or OFF (1 or 0) of the
BIN selection signals corresponding to the values of the binary data BIN0 to BINn.
More specifically, in a case where a value of an ith bit (BINi) of the binary data
BIN0 to BINn is 1, an (i+l)th pulse train (of 2' pulses) in the reference pulses passes
through, and in a case where the value of the ith bit (BINi) is 0, the (i+l)th pulse train
(of 21 pulses) in the reference pulses is masked. The reference pulses configured of
pulse trains passing through or masked by the AND gate 36a are supplied to the lowerbit
U/D CNT 37 as a masked signal.
[0064] [Example of a mask of reference pulse by BIN selection signal]
Now, an example of masking of the reference pulses by a BIN selection signal
will be described referring to FIG. 4.
[0065] For example, it is assumed that lower 4 bits of the binary data obtained by
conversion by the Gray code binary conversion circuit 35 is "1010" (which is
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equivalent to "10" in decimal).
[0066] In this case, values of the first bit and the third bit in the binary data are 1
(values of the 0th bit and the second bit are 0); therefore, a BIN selection signal which
is illustrated in the second line from the top in FIG. 4 and corresponds to values "0",
"1", "0", and "1" of the binary data BIN_0 to BIN3 to be input to the BIN selection
switches SW0 to SW3, respectively, is input to the AND gate 36a. Meanwhile, the
reference pulses in the first line from the top in FIG. 4 are input to the AND gate 36a.
[0067] Thus, by the AND gate 36a, the first pulse train (of 2° (=1) pulses) in the
reference pulses is masked, the second pulse train (of 21 (=2) pulses) passes through,
the third pulse train (of 22 (=4) pulses) is masked, and the fourth pulse train (of 23 (=8)
pulses) is masked. As a result, as illustrated in the third line from the top in FIG. 4, as
a masked signal, a masked signal of 10 pulses is supplied to the lower-bit U/D CNT 37.
In other words, the same number of pulses as the value of binary data obtained by
conversion by the Gray code binary conversion circuit 35 are supplied.
[0068] Then, the lower-bit U/D CNT 37 counts the pulses supplied as the masked
signal, that is, counts the value of the binary data obtained by conversion by the Gray
code binary conversion circuit 35, and holds a count value obtained thereby. Thus,
the lower-bit U/D CNT 37 counts lower bits held by the lower-bit storage element 32
in binary code.
[0069] It is to be noted that, in a case where a carry from an nth bit occurs in the
count value in the lower-bit U/D CNT 37, a most significant bit signal is supplied to
the higher-bit U/D CNT 34 through the carry select switch circuit 33. In other words,
the higher-bit U/D CNT 34 counts the most significant bit in the lower-bit U/D CNT
37 as a carry.
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[0070] [About operation of column AD conversion circuit]
Next, an operation of the column AD conversion circuit 14 will be described
below referring to a timing chart in FIG. 5.
[0071] It is to be noted that, in an example in FIG. 5, the lower-bit storage element
32 holds count values of 0th to 3rd bits (n=3).
[0072] First, after a count value reset signal for resetting count values of the higherbit
U/D CNT 34 and the lower-bit U/D CNT 37 is input, when a CNT (counter) enable
signal is turned on at a time t i l , reading of a reset level (a reset component) of each
vertical column of the pixels 11 starts. In the example in FIG. 5, a reset level reading
period is referred to as "first AD period". At this time, the higher-bit U/D CNT 34
starts down-counting of most significant bits of count values in Gray code input to the
storage elements 32-0 to 32-3.
[0073] At a time tl2, when the output (a count stop signal) of the comparator 31 is
reversed, the higher-bit U/D CNT 34 stops down-counting, and holds count values at
this time, and the storage elements 32-0 to 32-3 also hold count values at this time.
[0074] After the first-AD period, when an storing operation control circuit enable
signal is turned on, an operation of storing count values of lower bits held by the
storage elements 32-0 to 32-3 by the storing operation control circuit 36 (a first GC
BIN storing period) starts. At this time, the Gray code binary conversion circuit 35
converts count values GC0 to GC3 in Gray code from the storage elements 32-0 to
32-3 into binary data BIN0 to BIN3, and supplies the binary data BIN0 to BIN3 to
the storing operation control circuit 36.
[0075] Then, at a time tl3, in the storing operation control circuit 36, a BIN selection
signal corresponding to values (in the example in FIG. 5, "0", "1", "0", and "1") of the
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binary data BINO to BIN_3 to be input to the BIN selection switches SWO to SW_3,
respectively, together with the reference pulses from the reference pulse generation
circuit 19, starts to be input to the AND gate 36a. Then, as described referring to FIG.
4, when the reference pulses having passed through or having been masked by the
AND gate 36a are supplied to the lower-bit U/D CNT 37 as a masked signal, the
lower-bit U/D CNT 37 starts down-counting of pulses supplied as the masked signal.
Down-counting by the lower-bit U/D CNT 37 is performed until a time tl4.
[0076] At the time tl4, when the storing operation control circuit enable signal is
turned off, and the first GC BIN storing period ends, the lower-bit U/D CNT 37 stops
down-counting, and holds count values at this time.
[0077] Thus, the count value of the reset level is down-counted and held by the
higher-bit U/D CNT 34 and the lower-bit U/D CNT 37.
[0078] Next, at a time t21, when a CNT enable signal is turned on, reading of a
signal level (a signal component) of each vertical column of the pixels 11 starts. In
the example in FIG. 5, a signal level reading period is referred to as "second AD
period". At this time, the higher-bit U/D CNT 34 starts up-counting of most
significant bits of count values in Gray code to be input to the storage elements 32-0 to
32-3 from the count value held at the time tl2. It is to be noted that, in the storage
elements 32-0 to 32-3, the count value of the reset level is eliminated.
[0079] At a time t22, when the output (the count stop signal) of the comparator 31 is
reversed, the higher-bit U/D CNT 34 stops up-counting, and holds a count value at this
time, and the storage elements 32-0 to 32-3 also hold the count values at this time.
[0080] After the second AD period, when the storing operation control circuit enable
signal is turned on, an operation of storing count values of lower bits held by the
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storage elements 32-0 to 32-3 by the storing operation control circuit 36 (a second GC
BIN storing period) starts. At this time, the Gray code binary conversion circuit 35
converts the count values GCO to GC3 in Gray code from the storage elements 32-0
to 32-3 into the binary data BINO to BIN_3, respectively, and supplies the binary data
BINO to BIN3 to the storing operation control circuit 36.
[0081] Then, at a time t23, in the storing operation control circuit 36, a BIN selection
signal corresponding to values (in the example in FIG. 5, "1", "0", "1", and "1") of the
binary data BINO to BIN3 to be input to the BIN selection switches SW0 to SW_3,
respectively, together with the reference pulses from the reference pulse generation
circuit 19, starts to be input to the AND gate 36a. Then, as described referring to FIG.
4, when the reference pulses having passed through or having been masked by the
AND gate 36a are supplied to the lower-bit U/D CNT 37 as a masked signal, the
lower-bit U/D CNT 37 starts up-counting of pulses supplied as the masked signal from
the value held at the time tl4. Up-counting by the lower-bit U/D CNT 37 is
performed until a time t24.
[0082] It is to be noted that, in the example in FIG. 5, in a period from the time t23 to
the time t24, a carry in the count value in the lower-bit U/D CNT 37 occurs, and the
higher-bit U/D CNT 34 up-counts the most significant bit in the lower-bit U/D CNT 37
as a carry.
[0083] At the time t24, when the storing operation control circuit enable signal is
turned off, and the second GC BIN storing period ends, the lower-bit U/D CNT 37
stops up-counting, and holds a count value at this time.
[0084] Thus, the count value of the signal level is up-counted and held by the higherbit
U/D CNT 34 and the lower-bit U/D CNT 37.
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[0085] In other words, the count value of the reset level is down-counted and held,
and the count value of the signal level is up-counted from the held count value;
therefore, CDS processing is allowed to be performed on each column.
[0086] After that, respective bit values from the higher-bit U/D CNT 34 and the
lower-bit U/D CNT 37 are output in order, and data of all bits (N bits) are output.
[0087] In the above operation, even if CDS processing is performed in an image
sensor storing a count value in a storage element with use of a Gray code, it is not
necessary to include a storage element holding a count value of a reset component and
a storage element holding a count value of a signal component, and it is not necessary
to include signal lines transmitting the count values of the reset component and the
signal component to a subtracter determining a difference between the reset component
and the signal component; therefore, power consumption is allowed to be reduced
while reducing a circuit size.
[0088] Moreover, a lower bit storing operation is performed between a rest level
reading operation and a signal level reading operation and after the signal level reading
operation; therefore, CDS processing is allowed to be performed without increasing
processing time.
[0089] Further, a data amount (a bit amount) used in the storing operation is reduced
to only lower bits; therefore, power consumption by subsequent digital signal
processing is allowed to be further reduced while reducing a circuit size for transfer.
[0090] It is to be noted that timings of operations of the higher-bit U/D CNT 34 and
the lower-bit U/D CNT 37 are different in the reading operation and the lower bit
storing operation; therefore, the count values of the higher-bit U/D CNT 34 and the
lower-bit U/D CNT 37 each include an offset component, but the offset component is
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cancelled by CDS processing, and a correct count value is obtainable in the end
accordingly.
[0091] Moreover, in a configuration in which signals of two or more pixels are added
in the A/D converter, after a count value of a certain pixel is obtained by the operation
illustrated in FIG. 5, the count value is not reset, and the operation illustrated in FIG. 5
is performed again after switching to a pixel to be selected; therefore, addition is
performed in the higher-bit U/D CNT 34 and the lower-bit U/D CNT 37. Thus, in the
present technology, the configuration in which the signals of two or more pixels are
added in the A/D converter is achievable without further including a circuit for
addition.
[0092] A configuration in which a count value in Gray code of the lower-bit Gray
code generation circuit 18 is supplied to all of the column AD conversion circuits 14
for respective pixel columns is described above; however, in a case where the number
of columns is large, a load of pulse transmission from the lower-bit Gray code
generation circuit 18 is increased, thereby not allowing high-speed pulses to be
transmitted.
[0093] Therefore, a configuration in which a lower-bit Gray code generation circuit
is provided to every plurality of column AD conversion circuits 14 will be described
below.
[0094] <2. Application Example with a Large Number of Columns>
[Configuration example of solid-state image pickup device]
FIG. 6 illustrates a configuration example of an image sensor (a CMOS image
sensor) as a solid-state image pickup device in which a lower-bit Gray code generation
circuit is provided to every plurality o f column AD conversion circuits 14.
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[0095] It is to be noted that, in an image sensor 110 in FIG. 6, like components are
denoted by like numerals as of the image sensor 10 in FIG. 1 and will not be further
described.
[0096] In other words, the image sensor 110 in FIG. 6 is different from the image
sensor 10 in FIG. 1 in that a clock selector switch 121, clock buffers 122-1 to 122-M,
and clock selector switches 123-1 to 123-M are further included, and lower-bit Gray
code generation circuits 124-1 to 124-M are included instead of the lower-bit Gray
code generation circuit 18.
[0097] It is to be noted that, in the following description, in a case where distinctions
between the clock buffers 122-1 to 122-M, between the clock selector switches 123-1
to 123-M, and between the lower-bit Gray code generation circuits 124-1 to 124-M are
not necessary, the clock buffers 122-1 to 122-M, the clock selector switches 123-1 to
123-M, and the lower-bit Gray code generation circuits 124-1 to 124-M may be simply
referred to as "clock buffer 122", "clock selector switch 123", and "lower-bit Gray
code generation circuit 124", respectively. Moreover, the lower-bit Gray code
generation circuits 124 have a function similar to that of the lower-bit Gray code
generation circuit 18 in FIG. 1, and will not be further described.
[0098] In the image sensor 110 in FIG. 6, the number (column number) of pixel
columns of the pixels 11 is adequately larger than the number of pixel columns of the
pixels 11 in the CMOS image sensor 10 in FIG. 1. Moreover, in the image sensor
110 in FIG. 6, the clock buffer 122, the clock selector switch 123, and the lower-bit
Gray code generation circuit 124 are provided to every plurality of column AD
conversion circuits 14.
[0099] In other words, for example, in a case where the clock buffer 122, the clock
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selector switch 123, and the lower-bit Gray code generation circuit 124 are provided to
every 256 columns, the column number in the image sensor 110 is 256*M columns.
[0100] The clock selector switch 121 is a switch for selecting a clock signal from the
clock generation circuit 16 or a reference pulse signal from a reference pulse
generation circuit (not illustrated) to supply the selected signal to the clock buffer 122.
[0101] The clock buffer 122 is provided to every plurality of columns, for example,
every 256 columns to distribute the clock signal or the reference pulse signal from the
clock selector switch 121 to the column AD conversion circuits 14 for respective
columns with low skew.
[0102] The clock selector switch 123 is a switch for selecting whether the clock
signal distributed by the clock buffer 122 is to be transmitted to the lower-bit Gray
code generation circuit 124 or the reference pulse signal is to be transmitted to the
storing operation control circuit 36.
[0103] With the above-described configuration, the clock buffer 122 and the low-bit
Gray code generation circuit 124 are provided to every plurality of columns such as
every 256 columns, and the clock signal from the clock generation circuit 16 is
distributed to the lower-bit Gray code generation circuit 124; therefore, effects similar
to those in the image sensor 10 in FIG. 1 are obtained, and even in an image sensor
with a large number of columns, a load of pulse transmission from the low-bit Gray
code generation circuit to the column AD conversion circuits for respective columns is
allowed to be reduced, and high-speed pulses without delay are allowed to be
transmitted.
[0104] It is to be noted that, since the clock signal is distributed from the clock
generation circuit 16 to the lower-bit Gray code generation circuits 124 with different
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delays, the lower-bit Gray code generation circuits 124 operate at different timings.
Thus, count values in Gray code counted by the lower-bit Gray code generation
circuits 124 are different from one another, but the delay of the clock signal is fixed for
each of the lower-bit Gray code generation circuits 124; therefore, an influence by the
delay is cancelled by CDS processing, and a correct count value is obtainable in the
end.
[0105] [About reference pulse transmission]
Incidentally, also in the image sensor 110 illustrated in FIG. 6, the lower-bit
storing operation is performed between the reset level reading operation and the signal
level reading operation and after the signal level reading operation. Assuming that a
period in which the lower bit storing operation is performed is referred to as "lower-bit
storing period", in the lower-bit storing period, the lower-bit Gray code generation
circuit 124 does not need to perform counting. In other words, in the lower-bit
storing period, it is not necessary to distribute the clock signal from the clock
generation circuit 16 to the lower-bit Gray code generation circuit 124 through the
clock buffer 122.
[0106] Thus, in the lower-bit storing period, the clock selector switches 121 and 122
are turned to the reference pulse signal side.
[0107] In other words, in periods of the reset level reading operation and the signal
level reading operation, the clock selector switches 121 and 122 are turned to the clock
signal side so as to distribute the clock signal from the clock generation circuit 16 to
the lower-bit Gray code generation circuit 124 through the clock buffer 122. After
that, when the output of the comparator 31 is reversed, a count value in Gray code of
the lower-bit Gray code generation circuit 124 at this time is held by the lower-bit
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storage element 32. The count value in Gray code held by the lower-bit storage
element 32 is converted into binary data by the Gray code binary conversion circuit 35
to be supplied to the storing operation control circuit 36.
[0108] Then, in the lower-bit storing period, the clock selector switches 121 and 122
are turned to the reference pulse signal side so as to distribute the reference pulse
signal to the storing operation control circuit 36 through the clock buffer 122.
Therefore, the storing operation control circuit 36 is allowed to store the count value in
the lower-bit U/D CNT 37, based on the reference pulse signal and binary data from
the Gray code binary conversion circuit 35.
[0109] Since the clock selector switches 121 and 122 are turned from the clock
signal side to the reference pulse signal side in the lower-bit storing period in such a
manner, it is not necessary to further include a clock buffer for the reference pulse
signal, and a load of transmission of the reference pulse signal is allowed to be
suppressed, and a high-speed reference pulse signal without delay is allowed to be
transmitted. Therefore, the lower-bit storing period is allowed to be shortened, and a
time necessary for CDS processing is allowed to be shortened accordingly.
[0110] Incidentally, in the configuration of the above-described column AD
conversion circuit 14, when a carry occurs in a count value to be input to the lower-bit
storage element 32, a most significant bit signal is supplied to the higher-bit U/D CNT
34. However, in a case where the output of the comparator 31 is reversed at the
moment of the carry, the count value of the lower-bit storage element 32 is not carried
because of a ripple of the most significant bit signal; however, a bit mismatch caused
by counting the count value in the higher-bit U/D CNT 34 in spite of not carrying the
count value of the lower-bit storage element 23, that is, so-called metastable may occur.
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Accordingly, miscounting may occur.
[0111] Therefore, a configuration taking measures against metastable will be
described below.
[0112] <3. Application Example Taking Measures against Metastable>
[Configuration example of solid-state image pickup device]
FIG. 7 illustrates a configuration example of an image sensor (a CMOS image
sensor) as a solid-state image pickup device taking measures against metastable.
[0113] It is to be noted that, in an image sensor 210 in FIG. 7, like components are
denoted by like numerals as of the image sensor 110 in FIG. 6 and will not be further
described.
[0114] In other words, the image sensor 210 in FIG. 7 is different from the image
sensor 110 in FIG. 6 in that a metastable prevention circuit 221 is further included in
the column AD conversion circuit 14.
[0115] The metastable prevention circuit 221 operates with use of a count in Gray
code of the lower-bit Gray code generation circuit 18 as a clock, and delays the most
significant bit signal from the lower-bit storage element 32, and supplies the delayed
most significant bit signal to the higher-bit U/D CNT 34.
[0116] More specifically, the metastable prevention circuit 221 generates a mask
signal for temporarily masking the falling edge of the most significant bit signal from
the lower-bit storage element 32, based on the count (the clock) of the lower-bit Gray
code generation circuit 18. The metastable prevention circuit 221 masks the falling
edge of the most significant bit signal from the lower-bit storage element 32 with the
mask signal. Then, when masking by the mask signal is cleared, the metastable
prevention circuit 221 supplies the unmasked most significant bit signal to the higher26
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bit U/D CNT 34.
[0117] In the above-described configuration, the most significant bit signal from the
lower-bit storage element 32 is delayed and then is supplied to the higher-bit U/D CNT
34; therefore, effects similar to those in the image sensor 110 in FIG. 6 are obtained,
and metastable caused by counting the count value in the higher-bit U/D CNT 34 in
spite of not carrying the count value of the lower-bit storage element 23 is preventable.
[0118] It is to be noted that the above-described metastable prevention circuit 221
may be provided to the column AD conversion circuit 14 in FIG. 1.
[0119] Moreover, in the above-described image sensor, a Gray code counted by the
lower-bit Gray code generation circuit 18 (the lower-bit Gray code generation circuit
124) as a Gray code counter is used as a clock signal, and a count value is held by a
storage element. On the other hand, in the above-described image sensor, instead of
the lower-bit Gray code generation circuit 18 (the lower-bit Gray code generation
circuit 124), a count code generation circuit performing counting in a count pattern by
a predetermined rule such as a phase shift code may be included, and a count code may
be used as a clock signal, and a count value may be held by the storage element.
[0120] Even in such a configuration, effects similar to those in the above-described
image sensor are obtained.
[0121] Moreover, in the above description, the reference pulse signal is configured
through arranging n-number of pulse trains in order from a pulse train corresponding to
a least significant bit, where the bit number of lower bits is n; however, the n-number
of pulse trains may be arranged in different order.
[0122] For example, the reference pulse signal may be configured through arranging
n-number of pulse trains in order from a pulse train corresponding to a higher bit, that
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is, an nth bit, where the bit number of lower bits is n. More specifically, as illustrated
in FIG. 8, the reference pulse signal may be a pulse signal configured of n-number of
pulse trains of 2n, ..., 8, 4, 2, and 1 pulses. It is to be noted that, in this case, the
operations of the BIN selection switches SWO to SWn may be performed in order
corresponding to the order of the pulse trains.
[0123] Moreover, in the image sensor to which the present technology is applied, it is
only necessary for the storing operation control circuit 36 to be able to supply (store)
the pulse signal corresponding to binary data from the Gray code binary conversion
circuit 35 to (in) the lower-bit U/D CNT 37, and the configuration of the storing
operation control circuit 36 is not limited to that illustrated in FIG. 2, and may be any
other configuration.
[0124] <4,Others>
Moreover, the present technology is applicable to a solid-state image pickup
device with a laminate configuration.
[0125] [Configuration example of solid-state image pickup device with laminate
configuration]
FIG. 9 illustrates a configuration example of a solid-state image pickup device
with a laminate configuration to which the present technology is applied.
[0126] As illustrated in FIG. 9, a solid-state image pickup device 410 has a laminate
configuration of a first chip (an upper chip) 411 and a second chip (a lower chip) 412.
The solid-state image pickup device 410 is formed as a solid-state image pickup device
with a laminate configuration through bonding at a wafer level and then cutting by
dicing.
[0127] In the laminate configuration of the two chips, that is, the upper and lower
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chips, the first chip 411 is configured of a CMOS image sensor (CIS) chip, and the
second chip 412 is configured of a logic chip including a control circuit for the first
chip 411 and an image processing circuit. A bonding pad BPD and an input-output
circuit are formed in the second chip (the lower chip) 412, and opening sections OPN
for wire bonding to the second chip 412 is formed in the first chip (the upper chip).
[0128] The solid-state image pickup device 410 with a laminate configuration of
such two chips has the following characteristic configuration.
[0129] (1) An edge section where image signals are transmitted between the upper
and lower chips 411 and 412 are an output section of a comparator or a sigma-delta
modulator as a boundary circuit with a digital-system circuit of an analog-system
circuit.
(2) Connection between the upper and lower chips 411 and 412 is made
through, for example, vias.
(3) The first chip (the upper chip) 411 uses a CIS (CMOS Image Sensor)
process. However, only a high-voltage transistor (CMOS) is used for a transistor, and
the minimum necessary number of wiring layers for configurations of a pixel array and
its peripheral circuits are used to reduce cost. Herein, a high-voltage transistor refers
to a transistor having a larger thickness of a gate oxide film as a gate insulating film
than that of a typical MOS transistor and being operable without any trouble under
high voltages. It is to be noted that, for a typical CIS process, a low-voltage LV,
high-speed transistor is also necessary in addition to the high-voltage transistor for
high-speed logic circuits such as a control circuit and an image processing circuit.
Further, for the high-speed logic circuit, a larger number of wiring layers than the
minimum necessary number of wiring layers for the pixel array and its peripheral
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circuits are necessary.
(4) The second chip (lower chip) 412 uses a general logic process to
facilitate change and development in FAB.
(5) Circuits necessary for the solid-state pickup device 410 and particularly
important in characteristics where demands for analog characteristics and noise
characteristics (such as 1/f noise) are strict are mounted on the first chip (the upper
chip) 411. In this embodiment, at least a pixel array, a vertical decoder, a driver, and
the like are mounted on the first chip 411.
(6) Circuits operating at high speed and at a low voltage such as a highspeed
logic circuit, a memory, and an interface (I/F) circuit are mounted on the second
chip (the lower chip) 412. Process technology and the number of wiring layers are
determined in consideration of characteristics and sizes necessary for circuits.
Products are developed through combining the same first chip (the upper chip) 411
with the second chips (lower chips) 412 with different functions, characteristics, and
processes.
(7) The vias are disposed at chip ends or between a pad (PAD) and a circuit
region.
(8) Image signal wiring lines are disposed at an end of a comparator circuit
at a wiring pitch of vertical signal lines.
(9) TCVs (through contact vias) for a control signal and power supply are
mainly concentrated on four chip corners to reduce a signal wiring region of the first
chip (upper chip) 411. To solve issues of an increase in power line resistance and an
increase in IR-Drop caused by a reduction in the number of wiring layers in the first
chip (upper chip) 411, the TCVs are effectively arranged to enhance a power source of
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30
the first chip (upper chip) 411 with use of wiring of the second chip (lower chip) 412
for measures against noise, stable supply, and the like.
[0130] [Example of circuit layout]
Next, a circuit layout of the solid-state image pickup device 410 with the
laminate configuration in FIG. 9, that is, classifications of circuits to be mounted on
the first chip (upper chip) 411 and the second chip (lower chip) 412 will be described
below referring to FIG. 10.
[0131] The solid-state pickup device 410 in FIG. 10 includes a pixel array section
501 in which a large number of unit pixels (not illustrated) each including a
photoelectric conversion element are two-dimensionally arranged in a matrix.
[0132] Moreover, the solid-state image pickup device 410 includes a vertical drive
circuit (row scanning circuit) 502, a vertical decoder 503, a column AD conversion
circuit 504, a reference signal supply section 505, a horizontal scanning circuit
(column scanning circuit) 506, a timing control circuit 507, and an image signal
processing section 508.
[0133] The solid-state image pickup device 410 further includes I/F-based circuits
509.
[0134] In the solid-state image pickup device 410 in FIG. 10, the timing control
circuit 507 generates clock signals, control signals, and the like as references for
operation of the vertical drive circuit 502, the column AD conversion circuit 504, the
reference signal supply section 505, and the horizontal scanning circuit 506, based on a
master clock.
[0135] Moreover, peripheral drive systems which drive and control the unit pixels of
the pixel array section 501, and analog systems, i.e., the vertical drive circuit 502, a
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part of the column AD conversion circuit 504, the reference signal supply section 505,
and the like are integrated on the same first chip 411 as that where the pixel array
section 501 is mounted.
[0136] On the other hand, the timing control circuit 507, the image signal processing
section 508, the other part of the column AD conversion circuit 504, and the horizontal
scanning circuit 506 are integrated on the second chip (semiconductor substrate) 412.
[0137] A part surrounded by a broken line in FIG. 10 is arranged on the first chip
(the upper chip) 411, and the other part is arranged on the second chip (the lower chip)
412.
[0138] Although not illustrated, the unit pixels each include a photoelectric
conversion element (for example, a photodiode). Moreover, the unit pixels each
include, for example, a transfer transistor transferring an electric charge obtained by
photoelectric conversion in the photoelectric conversion element to an FD (floating
diffusion) section, in addition to the photoelectric conversion element. A threetransistor
configuration including, in addition to the transfer transistor, a rest transistor
which controls a potential of the FD section and an amplification transistor which
outputs a signal corresponding to the potential of the FD section may be applicable as
the unit pixels. Alternatively, a four-transistor configuration further including a
selection transistor for selecting pixels, or the like may be applicable as the unit pixels.
[0139] The unit pixels are two-dimensionally arranged in the pixel array section 501
in m rows and n columns, a row control line is provided to each row of the pixel
arrangement of m rows and n columns and a column signal line is provided to each
column of the pixel arrangement of m rows and n columns. One end of each row
control line is connected to an output end corresponding to each row of the vertical
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32
drive circuit 502. The vertical drive circuit 502 is configured of a shift register or the
like, and controls row addresses and row scanning of the pixel array section 501
through the row control lines.
[0140] The column AD conversion circuit 504 corresponds to the column AD
conversion circuit 14 in FIG. 1, and includes ADCs (analog digital converters) each
provided to each pixel column of the pixel array section 501, that is, each vertical
signal line LSGN to convert analog signals output from the unit pixels of each column
of the pixel array section 501 into N-bit digital signals, and then to output the digital
signals.
[0141] The reference signal supply section 505 includes, for example, a DAC
(digital-to-analog converter) as a means for generating a reference voltage Vref having
a so-called ramp waveform whose level varies obliquely with time. It is to be noted
that the means for generating the reference voltage Vref having the ramp waveform is
not limited to the DAC.
[0142] The DAC generates the reference voltage Vref having the ramp waveform,
based on a clock provided from the timing control circuit 507, and supplies the
reference voltage Vref to the ADCs of the column AD conversion circuit 504 under
control by a control signal provided from the timing control circuit 507.
[0143] The horizontal scanning circuit 506 is configured of a shift resistor or the like,
and controls column addresses of the ADCs and column scanning in the column AD
conversion circuit 504. Under control by the horizontal scanning circuit 506, the Nbit
digital signals obtained by AD conversion by the respective ADCs are sequentially
read into a horizontal signal line LHR, and the N-bit digital signals are output as image
pickup data to the image signal processing section 508 through the horizontal signal
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33
line LHR.
[0144] The image signal processing section 508 is a circuit performing various kinds
of signal processing on the image pickup data, and is configured through including an
image signal processor (ISP) 508a, a microprocessor 508b, a memory circuit 508a, and
the like.
[0145] In the above-described solid-state image pickup device with the laminate
configuration, flexibility in limitation of a circuit size is allowed to be increased.
[0146] In particular, in the column AD conversion circuit 14 in FIG. 1 corresponding
to the column AD conversion circuit 504, in terms of a circuit size of each column, the
circuit size is increased; however, when the present technology is applied to the solidstate
image pickup device with the laminate configuration, an influence on a sensor
size caused by an increase in the circuit size of each column is allowed to be limited.
[0147] [Configuration example of electronic apparatus to which the present
technology is applied]
It is to be noted that the present technology is not limited to application to
solid-state image pickup devices. In other words, the present technology is applicable
to electronic apparatuses of any kind using a solid-state image pickup element in an
image capturing section (a photoelectric conversion section) such as image pickup
apparatuses including digital still cameras and video cameras, portable terminals
having an image pickup function, and copying machines using a solid-state image
pickup element in an image scanning section. The solid-state image pickup device
may be formed in a form of one chip, or in a form of a module having an image pickup
function in which an image pickup section and a signal processing section or an optical
system are collectively packaged.
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[0148] FIG. 11 is a block diagram illustrating a configuration example of an image
pickup apparatus as an electronic apparatus to which the present technology is applied.
[0149] An image pickup apparatus 600 in FIG. 11 includes an optical section 601
configured of a lens group and the like, a solid-state image pickup device (image
pickup device) 602 adopting any of the above-described configuration of unit pixels 50,
and a DSP circuit 603 as a camera signal processing circuit. The image pickup
apparatus 600 further includes a frame memory 604, a display section 605, a recording
section 606, an operation section 607, and a power source section 608. The DSP
circuit 603, the frame memory 604, the display section 605, the recording section 606,
the operation section 607, and the power source section 608 are connected to one
another through a bus line 609.
[0150] The optical section 601 forms an image on an image pickup plane of the
solid-state image pickup device 602 through taking incident light (image light) from an
object. The solid-state image pickup device 602 converts a light amount of the
incident light forming an image on the image pickup plane by the optical section 601
into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal.
As the solid-state image pickup device 602, a solid-state image pickup device such as
the image sensor 10 according to the above-described embodiment, that is, a solid-state
image pickup device storing a count value in a storage element with use of a count
code in a count pattern by a predetermined rule as a clock signal may be used.
[0151] The display section 605 is configured of, for example, a panel-type display
unit such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and
displays moving or still images picked up by the solid-state image pickup device 602.
The recording section 606 records the moving or still images picked up by the solidSP316030
35
state image pickup device 602 to a recording medium such as a video tape or a DVD
(Digital Versatile Disk).
[0152] The operation section 607 issues operation commands to enable various
functions provided to the image pickup apparatus 600 under an operation by a user.
The power source section 608 appropriately supplies various kinds of power sources as
operation power sources of the DSP circuit 603, the frame memory 604, the display
section 605, the recording section 606, and the operation section 607 to these targets.
[0153] As described above, for example, when the image sensor 10 according to the
above-described embodiment is used as the solid-state image pickup device 602, it is
not necessary to include a storage element holding a count value of a reset component
and a storage element holding a count value of a signal component, and it is not
necessary to include signal lines transmitting the count values of the reset components
and the signal components to a subtracter determining a difference between the reset
component and the signal component; therefore, power consumption is allowed to be
reduced while reducing a circuit size. Therefore, downsizing and power saving in the
image pickup apparatus 600 such as a video camera, a digital camera, or a camera
module for a mobile device such as a cellular phone are achievable.
[0154] Moreover, in the above-described embodiments, a case where the present
technology is applied to a CMOS image sensor configured through arranging, in a
matrix, unit cells detecting a signal charge as physical quantity corresponding to a light
amount of visible light is described as an example. However, the present technology
is not limited to application to the CMOS image sensor, and is applicable to any kind
of column-type solid-state image pickup element configured through providing column
processing sections to respective pixel columns of the pixel array section.
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36
[0155] Further, the present technology is not limited to application to the solid-state
image pickup element which detects a distribution of an incident light amount of
visible light and picks up the distribution as an image, and is applicable to a solid-state
image pickup element which picks up a distribution of an incident amount of infrared
radiation, X-ray radiation, particles, or the like as an image, and any kind of solid-state
image pickup device (physical quantity distribution detection device) in a broad sense,
such as a fingerprint detection sensor which detects a distribution of any other physical
quantity such as pressure or capacitance and picks up the distribution as an image.
[0156] It is to be noted that embodiments of the present technology are not limited to
the above-described embodiments, and may be variously modified without departing
from the scope of the present technology.
[0157] Moreover, the present technology may have the following configurations.
(1) An AID converter including:
a comparison section comparing a reference voltage with an input voltage, the
reference voltage having a ramp waveform whose voltage value varies with time;
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section;
a conversion section converting the count value in the count pattern held by
the storage section into binary data; and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a first counter.
(2) The AID converter according to (1), in which the storage section
supplies, to a second counter, a most significant bit signal representing a most
significant bit of the count value in the count pattern until the output signal from the
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comparison section is reversed, and holds lower bits lower than the most significant bit
of the count value in the count pattern when the output signal from the comparison
section is reversed.
(3) The A/D converter according to (2), in which
the conversion section converts lower bits of the count value in the count
pattern into the binary data, and
the supply section supplies, to the first counter, a pulse signal corresponding
to a value of each bit in the binary data of a reference signal serving as a reference
pulse signal.
(4) The A/D converter according to (3), in which
the reference signal is a pulse signal configured of n-number of pulse trains of
2° to 2n pulses, where the bit number of the lower bits is n, and
the supply section supplies, to the first counter, a pulse train corresponding to
each bit whose value is 1 of 0th to nth bits in the binary data of the reference signal.
(5) The A/D converter according to (3) or (4), in which the second counter
counts a most significant bit of a count value in the first counter as a carry.
(6) The A/D converter according to any one of (2) to (5), further including a
bit mismatch prevention section preventing a bit mismatch of the most significant bit
signal supplied to the second counter.
(7) The A/D converter according to any one of (1) to (6), in which the count
pattern is a Gray code.
(8) The A/D converter according to any one of (1) to (6), in which the count
pattern is a phase shift code.
(9) A solid-state image pickup device including:
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a pixel array in which a plurality of pixels performing photoelectric
conversion are arranged in a matrix; and
an AID converter provided to every column or every plurality of columns of
the pixels and converting analog signals output from the pixels of each column into
digital signals,
in which the A/D converter includes
a comparison section comparing a reference voltage with an input voltage of
the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time,
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section,
a conversion section converting the count value in the count pattern held by
the storage section into binary data, and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a first counter.
(10) The solid-state image pickup device according to (9), in which the
storage section supplies, to a second counter, a most significant bit signal representing
a most significant bit of the count value in the count pattern until the output signal
from the comparison section is reversed, and holds lower bits lower than the most
significant bit of the count value in the count pattern when the output signal from the
comparison section is reversed.
(11) The solid-state image pickup device according to (10), in which
the conversion section converts lower bits of the count value in the count
pattern into the binary data, and
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the supply section supplies, to the first counter, a pulse signal corresponding
to a value of each bit in the binary data of a reference signal serving as a reference
pulse signal.
(12) The solid-state image pickup device according to (11), in which
the reference signal is a pulse signal configured of n-number of pulse trains of
2° to 2n pulses, where the bit number of the lower bits is n, and
the supply section supplies, to the first counter, a pulse train corresponding to
each bit whose value is 1 of 0th to nth bits in the binary data of the reference signal.
(13) The solid-state image pickup device according to (11) or (12), in which
the second counter counts a most significant bit of a count value in the first counter as
a carry.
(14) The solid-state image pickup device according to any one of (9) to (13),
further including:
a clock generation section generating a clock signal; and
an input section inputting a count value in the count pattern to the storage
section, based on the clock signal.
(15) The solid-state image pickup device according to (14), in which
the input section is provided to every plurality of the A/D converters,
a clock buffer for transmitting the clock signal to the input section provided to
every plurality of the A/D converters is provided to every plurality of the A/D
converters, and
the clock buffer transmits the reference signal to the supply section after the
output signal of the comparison section is reversed.
(16) The solid-state image pickup device according to any one of (10) to
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(15), further including a bit mismatch prevention section preventing a bit mismatch of
the most significant bit signal supplied to the second counter.
(17) The solid-state image pickup device according to any one of (9) to (16),
in which the count pattern is a Gray code.
(18) The solid-state image pickup device according to any one of (9) to (16),
in which the count pattern is a phase shift code.
(19) A method of driving a solid-state imaging device, the solid-state
imaging device including a pixel array in which a plurality of pixels performing
photoelectric conversion are arranged in a matrix, and an A/D converter provided to
every column or every plurality of columns of the pixels and converting analog signals
output from the pixels of each column into digital signals, the method including:
a comparing step of allowing the A/D converter to compare a reference
voltage with an input voltage of the analog signal, the reference voltage having a ramp
waveform whose voltage value varies with time;
a storing step of allowing the A/D converter to hold a count value in a
predetermined count pattern, based on an output signal from the comparison section;
a converting step of allowing the A/D converter to convert the count value in
the count pattern held by the storage section into binary data; and
a supplying step of allowing the A/D converter to supply a pulse signal
corresponding to the binary data obtained by conversion in the conversion section to a
counter.
(20) An electronic apparatus provided with a solid-state image pickup
device, the solid-state image pickup device including:
a pixel array in which a plurality of pixels performing photoelectric
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conversion are arranged in a matrix; and
an A/D converter provided to every column or every plurality of columns of
the pixels and converting analog signals output from the pixels of each column into
digital signals,
in which the A/D converter includes
a comparison section comparing a reference voltage with an input voltage of
the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time;
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section;
a conversion section converting the count value in the count pattern held by
the storage section into binary data; and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a counter.
Reference Signs List
[0158] 10 image sensor, 14 column AD conversion circuit, 18 lower-bit
Gray code generation circuit, 19 reference pulse generation circuit, 31
comparator, 32 lower-bit storage element, 34 higher-bit U/D CNT, 35 Gray
code binary conversion circuit, 36 storing operation control circuit, 37 lower-bit
U/D CNT

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CLAIMS
[Claim 1] An A/D converter comprising:
a comparison section comparing a reference voltage with an input voltage, the
reference voltage having a ramp waveform whose voltage value varies with time;
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section;
a conversion section converting the count value in the count pattern held by
the storage section into binary data; and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a first counter.
[Claim 2] The A/D converter according to claim 1, wherein the storage section
supplies, to a second counter, a most significant bit signal representing a most
significant bit of the count value in the count pattern until the output signal from the
comparison section is reversed, and holds lower bits lower than the most significant bit
of the count value in the count pattern when the output signal from the comparison
section is reversed.
[Claim 3] The A/D converter according to claim 2, wherein
the conversion section converts lower bits of the count value in the count
pattern into the binary data, and
the supply section supplies, to the first counter, a pulse signal corresponding
to a value of each bit in the binary data of a reference signal serving as a reference
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pulse signal.
[Claim 4] The A/D converter according to claim 3, wherein
the reference signal is a pulse signal configured of n-number of pulse trains of
2° to 2n pulses, where the bit number of the lower bits is n, and
the supply section supplies, to the first counter, a pulse train corresponding to
each bit whose value is 1 of 0th to nth bits in the binary data of the reference signal.
[Claim 5] The A/D converter according to claim 3, wherein the second counter
counts a most significant bit of a count value in the first counter as a carry.
[Claim 6] The A/D converter according to claim 2, further comprising a bit mismatch
prevention section preventing a bit mismatch of the most significant bit signal supplied
to the second counter.
[Claim 7] The A/D converter according to claim 1, wherein the count pattern is
a Gray code.
[Claim 8] The A/D converter according to claim 1, wherein the count pattern is
a phase shift code.
[Claim 9] A solid-state image pickup device comprising:
a pixel array in which a plurality of pixels performing photoelectric
conversion are arranged in a matrix; and
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an A/D converter provided to every column or every plurality of columns of
the pixels and converting analog signals output from the pixels of each column into
digital signals,
wherein the A/D converter includes
a comparison section comparing a reference voltage with an input voltage of
the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time,
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section,
a conversion section converting the count value in the count pattern held by
the storage section into binary data, and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a first counter.
[Claim 10] The solid-state image pickup device according to claim 9, wherein
the storage section supplies, to a second counter, a most significant bit signal
representing a most significant bit of the count value in the count pattern until the
output signal from the comparison section is reversed, and holds lower bits lower than
the most significant bit of the count value in the count pattern when the output signal
from the comparison section is reversed.
[Claim 11] The solid-state image pickup device according to claim 10, wherein
the conversion section converts lower bits of the count value in the count
pattern into the binary data, and
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the supply section supplies, to the first counter, a pulse signal corresponding
to a value of each bit in the binary data of a reference signal serving as a reference
pulse signal.
[Claim 12] The solid-state image pickup device according to claim 11, wherein
the reference signal is a pulse signal configured of n-number of pulse trains of
2° to 2n pulses, where the bit number of the lower bits is n, and
the supply section supplies, to the first counter, a pulse train corresponding to
each bit whose value is 1 of 0th to nth bits in the binary data of the reference signal.
[Claim 13] The solid-state image pickup device according to claim 11, wherein
the second counter counts a most significant bit of a count value in the first counter as
a carry.
[Claim 14] The solid-state image pickup device according to claim 9, further
comprising:
a clock generation section generating a clock signal; and
an input section inputting a count value in the count pattern to the storage
section, based on the clock signal.
[Claim 15] The solid-state image pickup device according to claim 14, wherein
the input section is provided to every plurality of the A/D converters,
a clock buffer for transmitting the clock signal to the input section provided to
every plurality of the A/D converters is provided to every plurality of the A/D
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converters, and
the clock buffer transmits the reference signal to the supply section after the
output signal from the comparison section is reversed.
[Claim 16] The solid-state image pickup device according to claim 10, further
comprising a bit mismatch prevention section preventing a bit mismatch of the most
significant bit signal supplied to the second counter.
[Claim 17] The solid-state image pickup device according to claim 9, wherein
the count pattern is a Gray code.
[Claim 18] The solid-state image pickup device according to claim 9, wherein
the count pattern is a phase shift code.
[Claim 19] A method of driving a solid-state imaging device, the solid-state
imaging device including a pixel array in which a plurality of pixels performing
photoelectric conversion are arranged in a matrix, and an A/D converter provided to
every column or every plurality of columns of the pixels and converting analog signals
output from the pixels of each column into digital signals, the method comprising:
a comparing step of allowing the A/D converter to compare a reference
voltage with an input voltage of the analog signal, the reference voltage having a ramp
waveform whose voltage value varies with time;
a storing step of allowing the A/D converter to hold a count value in a
predetermined count pattern, based on an output signal from the comparison section;
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a converting step of allowing the A/D converter to convert the count value in
the count pattern held by the storage section into binary data; and
a supplying step of allowing the A/D converter to supply a pulse signal
corresponding to the binary data obtained by conversion in the conversion section to a
counter.
[Claim 20] An electronic apparatus provided with a solid-state image pickup
device, the solid-state image pickup device comprising:
a pixel array in which a plurality of pixels performing photoelectric
conversion are arranged in a matrix; and
an A/D converter provided to every column or every plurality of columns of
the pixels and converting analog signals output from the pixels of each column into
digital signals,
wherein the A/D converter includes
a comparison section comparing a reference voltage with an input voltage of
the analog signal, the reference voltage having a ramp waveform whose voltage value
varies with time;
a storage section holding a count value in a predetermined count pattern,
based on an output signal from the comparison section; ,
a conversion section converting the count value in the count pattern held by
the storage section into binary data; and
a supply section supplying a pulse signal corresponding to the binary data
obtained by conversion in the conversion section to a counter.