A device and a circuit for controlling a power electronics component, an associated driving method and an associated ignitor
The present invention relates to a device, a circuit and a method for controlling a power electronics component.
Power electronics components are for example used in high voltage switching devices to "adapt" the shape of a current to its use in a rotating machine or a motor of an electric vehicle.
The switching device can convert alternating current to direct current or vice versa, or modify the shape, amplitude and frequency of the current wave.
The switching device includes power electronics components, for example IGBT (Insulated Gate Bipolar Transistor) power transistors, which when they are switched from an open state to a closure state, chop a DC voltage into secondary waves in order to modify the nature of the current and form, for example, an alternating current.
To this end, the switching device receives control instructions from a computer which it translates into commands for opening and closing the IGBT transistors. To open or close the IGBT transistors, a voltage is applied between the gate electrode and the emitter electrode of the IGBT transistors. This application is generally performed by RC (Resistor-Capacitor) circuits.
However, the values of resistivity and capacitance of the components of these RC circuits must be modified for each new application, i.e. each time the switching device controls a new machine or even when the operating parameters of this new machine are modified.
The object of the present invention is to propose a circuit for controlling at least one power electronics component intended to be controlled so as to adapt to each new application without having to change components of the RC circuit.
To this end, the invention relates to a circuit for controlling the opening and closing of a power electronics component, the power electronics component having a gate electrode, an emitter electrode and a collector electrode, characterized in that the circuit comprises an H-bridge comprising:
- a first vertical branch comprising a first switch and a first current generator controlled digitally, the first switch being separated from the first current generator

by a middle point intended to be connected to the emitter electrode of the power electronics component; and
- a second vertical branch parallel to the first vertical branch, the second vertical branch comprising a second switch and a second current generator controlled digitally, the second switch being separated from the second generator by a middle point intended to be connected to the gate electrode of the power electronics component;
- the first current generator being suitable for delivering a supply current directed in a first direction in order to supply the gate electrode of the power electronics component; and the second current generator being suitable for delivering a supply current directed in a second direction opposite to the first direction in order to supply the emitter electrode of the power electronics component.
According to other aspects of the invention, the control circuit comprises one or more of the following features:
- the H-bridge includes a third switch connected in parallel to the first current generator, and a fourth switch connected in parallel to the second current generator, and the circuit includes a current source intended to supply the H-bridge, said current source being connected between, on the one hand, the first and the second switches, and, on the other hand, the first and the second current generators;
- the voltage source comprises a capacitor; and
- the switches are MOS transistors.
The invention relates also to a method for driving a control circuit of the abovementioned type, characterized in that it includes, upon a command for closing the power electronics component, a step for the delivery of a supply current by the first current generator, the second switch being in the state of conduction in the first direction.
According to other aspects of the invention, the driving method comprises one or more of the following features:
- the method includes a preliminary step for placing the second switch into
the state of conduction in said first direction, the first switch being in the state of
conduction in said first direction;

- the method additionally includes:
- a step for placing the third switch into the state of conduction in the first direction, the second switch being in the state of conduction in the first direction,
- a step for the delivery, by the current source, of a current pulse directed in the first direction;

- the method includes, upon a command for opening the power electronics component, a step for the delivery of a supply current by the second current generator;
- the method includes a preliminary step for placing the fourth switch into said state of conduction in said second direction, the third switch being in the state of conduction in said second direction;
- the method includes furthermore:

- a step for placing the first and the fourth switches into the state of conduction in said second opposite direction, and
- a step for the delivery, by the current source, of a current pulse in said second direction;

- the step for delivering the current pulse is implemented by the discharging of the capacitor; and
- the step for delivering a supply current comprises a step for the graduai decrease over time in the supply current according to a predefined profile.
Moreover, another subject of the invention is a device for controlling at least one control circuit of the abovementioned t^e, the control device being intended to receive power control instructions, and to control the control circuit in order to open and close at least one power electronics component according to the power control instructions, the device comprising:
- a driving unit able to convert power control instructions into signals for
controlling the opening and/or closing of the switches and into signals for
controlling the switching on and/or switching off of the cun-ent generators of the
control circuit;
- a memory for storing operating parameters of the or each power
electronics component, and control parameters for the current intended to be

applied to the gate electrode and to the emitter electrode of the or each power electronics component, said memory being erasable and rewritable; and
- a peripheral logic unit able to receive from said memory the operating
parameters and the control parameters for the supply current, the peripheral logic
unit being able to execute tasks for the driving unit according to the received
operating parameters and current control parameters.
According to other aspects of the invention, the device comprises one or more of the following features:
- the device comprises at least one timer intended to time the moments of transmission of the control signals for opening and/or closing the switches based on the operating parameters and the control parameters received from the memory;
- the device comprises a regulating unit suitable for delivering digital commands for varying the supply current according to a predefined profile to a digital-to-analogue converter in order to control the current generators; and
- the device comprises:

- a circuit for acquiring information relating to the voltage between the coHector electrode and the emitter electrode of the power electronics component, and
- a time-domain filtering block for filtering information acquired by the acquisition circuit,
■ the driving unit being intended to determine the state of the power electronics component based on information filtered by the time-domain filtering block, the driving unit being also able to control the consistency between the power control instructions and the state of the power electronics component. Moreover, the invention relates to an igniter comprising:
- a control device of the abovementioned type, and
■ an erasable and rewritable memory, said memory being equipped with electrical contacts intended to be connected to a computer in order to receive control parameters and operating parameters, said memory being connected to the memory of the control device in order to transmit to it said control parameters and said operating parameters.

Lastly, the invention relates to an assembly comprising a control circuit of the abovementioned type and a control device of the abovementioned type tor this control circuit.
The invention will be better understood on reading the following description given purely by way of illustration and with reference to the drawings in which:
- Figure 1 is a schematic illustration of a control system for a rotating machine;
- Figure 2 is a schematic illustration of a switch formed by three packs of power electronics components;
- Figure 3 is a schematic illustration of the architecture of a control device and of three control circuits each suitable for controlling a power electronics component of a switch;
- Figure 4 is a schematic illustration of the detail of a control circuit illustrated in Figure 3;
- Figure 5 is a flow chart of a method for driving the components of the control circuit illustrated in Figure 4;
- Figures 6 to 9 are schematic illustrations representing parts of the control circuit illustrated in Figure 4; and
- Figures 10 and 11 are graphs illustrating the change over time of various operating parameters of a power electronics component when the method of Figure 5 is being applied.
With reference to Figure 1, a control system for a rotating electric machine 2 conventionally comprises a computing device 4 suitable for delivering power control instructions to an electronic igniter 6. The purpose of the igniter 6 is to convert these power control instructions into instructions for controlling a switch 10 of a switching device 8.
The switching device 8 is for example a three-phase DC/AC converter. It comprises six switches 10.
In Figures 1 and 2, only one switch 10 has been represented. This switch 10 comprises three packs 11A. 11B, 11C. Each pack 11 A, 11B, 11C comprises an IGBT (Insulated Gate Bipolar Transistor) power transistor 12, 14, 16 mounted in antiparallel with its diode 18, 20, 22. Each power transistor comprises a gate

electrode, a collector electrode and an emitter electrode hereafter referred to as gate, collector and emitter respectively.
Each power transistor 12, 14, 16 is typically capable of switching currents of up to 1200 A. The switch 10, i.e. the three transistors 12, 14, 16 mounted in parallel, is capable of switching currents of up to about 2500 A. Each power transistor 12, 14, 16 is capable of bearing a voltage VCE between the collector and the emitter in the non-conducting state, i.e. in the open state, of up to 4000 V, and in the conducting state, i.e. in the closed state, a voltage VCE generally less than 5V.
The igniter 6 is suitable for controlling the switching of the switch 10. It comprises an encoder/decoder, a power supply system and a digital system, which are not represented.
It also comprises a flash memory 23 and a device 24 for controlling the switching of the power transistors of the pack.
The flash memory 23 is suitable for storing operating and control parameters for the power transistors 12, 14, 16. It is electrically erasable and rewritable. To this end, it is equipped with electrical contacts suitable for being connected to a computer to modify the operating and control parameters for the power transistors 12, 14, 16, each time the switching device 8 controls a new machine.
The control device 24 is illustrated in Figure 3. It is installed in an FPGA (Field Programmable Gate Anay) that can be programmed by the user, It comprises a control logic capable of synchronously and independently controlling three control circuits 26, 28, 30, each suitable for controlling a gate/emitter pair of a power transistor 12, 14, 16 of the switch 10. Only the control circuit 26 and the power transistor 12 have been Illustrated in Figure 4. The control circuits 28 and 30 are able to control the switching of the transistors 14 and 16 respectively. These circuits are identical to the circuit 26 and will not be described in detail.
Since the power transistor 12 behaves as though it intrinsically contains a capacitor, it has been represented in Figures 4 to 9 with a capacitor 32 connected to its gate and its emitter.
The circuit 26 is an H-bridge which is used to set the potential between the gate and the emitter of the power transistor 12. It is delimited by a closed line and

comprises two parallel electrical links forming the first 33A and second 33B vertical branches of an H. The first branch 33A includes a first MOS transistor 34, and a first current generator 40 connected in parallel to a third MOS transistor 42. The first MOS transistor 34 is separated from the current generator 40 / MOS transistor 42 group by a middle point 32A intended to be connected to the emitter of the power transistor 12. The second branch 33B includes a second MOS transistor 36, and a second current generator 44 connected in parallel to a fourth MOS transistor 46. The second MOS transistor 36 is separated from the current generator 44 / fourth MOS transistor 46 group by a second middle point 32B intended to be connected to the gate of the power transistor 12.
When no voltage is applied to their gate, the MOS transistors allow current to flow from their source to their drain (N channel) or from their drain to their source (P channel). This is why the MOS transistors are represented in Figures 4 and 6 to 9 by switches mounted in parallel with a diode.
The generators 40 and 44 are variable resistance current generators controlled digitally via a digital-to-analogue converter which is not represented.
The opening and closing of the MOS transistors 34, 36, 42, 46 is controlled directly by the control device 24 or by driving units controlled by the control device 24.
The MOS transistors 34, 42 and 36, 46 are switches, the purposes of which are to set the polarity of the gate and the emitter of the power transistor 12 in order to cause a current to flow, entering through the gate of the power transistor 12 (current in the clockwise direction F1) or flowing out of the gate (current in the anticlockwise direction F2).
The H-bridge is powered by a capacitor 50 connected at a node 54 located between the MOS transistors 34 and 36, and at a node 56 located between the MOS transistors 34, 36 / current generators 40, 44 groups. The voltage of the capacitor 50 is regulated at 15 V by a voltage source 57. The latter supplies the current required for operation, compensating for inevitable ohmic losses in the process for controlling the gate of the transistor 12.
The method for driving the circuit 26 starts with a step 58 at which a check is carried out to ensure that the capacitor 32 is not short-circuited due to, for example, the failure of a MOS transistor.

If the capacitor 32 is short-circuited, a safety procedure is set up so as not to damage the igniter 6.
If the capacitor 32 is not short-circuited, the voltage VQE between the gate and the emitter of the transistor 12 is initially charged at -15 V.
At step 60, the transistor 36 is closed, i.e. in a conducting state. The transistors 42 and 48 are in an open state, i.e. in a non-conducting state. The current generators 40, 44 are switched off or disabled, i.e. they do not generate current. A discharge current Ig for the capacitor 32 is established in the upper part of the H-bridge in the clockwise direction F1 until the voltage VQE between the gate and the emitter of the transistor 12 is approximately equal to 0 V. The part of the circuit 26 through which the current Ig flows is illustrated in Figure 6.
The current Ig exhibits a high-intensity peak between 5 A and 10 A. This current peak enables the gate of the power transistor 12 to be brought to the conduction threshold.
At this step, the voltage VCE between the collector and emitter of the transistor 12 is high (greater than the operating voltage divided by two). No current flows between the collector and emitter of the power transistor 12.
At a step 62, the current generator 40 is switched on to generate a current Ig. This current Ig is injected into the gate of the power transistor 12 via the capacitor 50 and transistor 36, as can be seen in Figures 7 and 10.
The generator 40 is controlled in such a way that the current Ig decreases gradually according to a predefined curve profile P6, and then the generator 40 is switched off. The current profile P6 has a plateau at the moment when the power transistor 12 switches to the conducting state, as illustrated in Figure 10, or varies as an inverse exponential curve as illustrated in Figure 11.
As can be seen in Figure 10, a current )c is established between the collector and the emitter of this transistor 12 while the voltage VCE gradually decreases.
If the current Ig is too high, the current Ic which is established between the collector and the emitter of the transistor 12 can suddenly become too high (dIc/dt too high) which can result in irreversible damage to the power transistor 12.

Since the current generator 40 according to the invention is controlled digitally, the decrease in the current Ig is regulated in a precise manner by the control device 24 in order to prevent any deterioration of the power transistor 12.
Advantageously, this cun/e profile P6 can easily be modified when the switching device 8 is used for a new application, as explained later.
At a step 64, the transistor 42 is closed. The capacitor 50 is discharged and generates a discharge pulse D as can be seen in Figure 10. This discharge pulse enables the power transistor 12 to be kept in the conducting state, avoiding oscillatory phenomena of successive openings and closures which could damage thetransistor12.
The voltage VCE is then equal to 5 V. The voltage VGE between the gate and the emitter is +15 V.
During steps 60 and 64, the voltage source 57 recharges the capacitor 50 to compensate for the ohmic losses accumulated during the charging and discharging cycles of the capacitor 32.
The procedure for opening the power transistors 12, 14, 16 starts with a step 68 at which the transistor 46 is closed (dotted line in Figure 8), the transistors 34, 36 and 42 being open. A high discharge current Ig for the capacitor 32 is established in the circuit 26 in the anticlockwise direction F2 as illustrated in Figures 8 and 10. This reaches a value of S A to 10 A depending on the type of IGBT. At the end of step 68, the voltage VGE is approximately equal to the conduction threshold voltage of the IGBT.
Next, at a step 70, the transistor 46 is opened (represented as a solid line in Figure 8) and the current generator 44 is switched on. It generates a current Ig of low intensity in the anticlockwise direction F2, as illustrated in Figure 10.
The current Ig is gradually decreased by the current generator 44 and if necessary kept at the same level at the moment when the power transistor 12 switches to the blocked or non-conducting state. Lastly, the current generator 44 is switched off.
At a step 72, illustrated in Rgure 9, the transistors 46 and 34 are closed. The capacitor 50 generates a discharge current pulse D illustrated in Figure 10. The discharging of the capacitor 50 into the capacitor 32 enables the current flowing between the collector and emitter of the power transistor 12 to be brought

back rapidly to a zero value. This pulse provides for eliminating the oscillatory phenomenon which generally takes place when new generation power transistors are opened. Since the current Ic is rapidly brought back to 0, the switching losses are reduced.
At steps 68 and 72, the voltage source 57 recharges the capacitor 50 to compensate for the ohmic losses accumulated during the charging and discharging cycles of the capacitor 32.
The other units of the control device 24 will now be described with reference to Figure 3.
The control device 24 comprises a driving unit 79 suitable for deciding which voltage VGE must be applied between the gate and the emitter of the transistors 12, 14, 16.
The driving unit 79 is a finite state machine, capable of automatically switching from one control state to another when a condition for the transition to the next state is satisfied.
The driving unit 79 is capable of converting power control instructions from the computing device 4 which are received by the encoder/decoder of the igniter 6 into control signals in order to inject or extract current to/from the gates of power transistors 12, 14,16.
The control device 24 also comprises a memory 80, a peripheral logic unit 82 and a circuit 84 for acquiring information relating to the voltage VCE between the collector and the emitter of the power transistors 12,14, 16.
The memory 80 is a dual-port random access memory (RAM), preloaded from the electrically programmable flash memory 23. It contains operating parameters for each power transistor 12, 14, 16, and control parameters for the current Ig intended to be applied to the gate and to the emitter of each power transistor 12, 14, 16. These parameters are transferred from the flash memory 23 to the serial port of the memory 80 when the igniter 6 is switched on and are then able to be transferred from the 16-bit port of the memory 80 in order to program the peripheral logic unit 82.
When the switching device 8 is assigned to a new application, the operating parameters and control parameters can easily be modified by connecting the flash memory 23 to a computer containing a program for modifying these parameters.

The acquisition circuit 84 is suitable for determining at any moment the vdtage VCE between the collector and the emitter of the power transistors 12, 14, 16, and the variation of this voltage with time. The principle of operation of the circuit is explained in the patent application published under the number 02 851 056, and will not be described in this application.
The driving unit 79 is able to receive measurement information of the voltage VCE, and measurements of the variation of this voltage VGE with time, from the acquisition circuit 84 in order to constantly check the consistency of the control instructions received from the computing device 4 with the state of each power transistor 12, 14, 16 both at the switching moments and during the stationary states.
The peripheral logic unit 82 comprises a time-domain filtering block SB for signals received from the acquisition circuit 84, a first timer 90 and a second timer 92, a unit 94 for adjusting the profile of the current injected into the gates of the power transistors 12,14,16 and lastly a checking unit 96.
The time-domain filtering block 88 is able to filter the voltage Vce over a predefined time interval in order to remove signals representing parasitic variations of this voltage.
The first timer 90 is capable of measuring times of the order ten microseconds on command from the driving unit 79. It is suitable for receiving the operating parameters and the control parameters from the memory 80. These comprise in particular the minimum tolerated duration PI of a pulse on the gate of each power transistor 12, 14, 16, and the minimum saturation delay P2 of each power transistor, i.e. the minimum delay between two switching commands. Examples of operating parameters and control parameters are illustrated in Figure 11.
The second timer 92 is capable of measuring times from 25 ns to several microseconds on command from the driving unit 79. It receives the parameters to be timed from the memory 80. It is in particular used to time the moments P3, P4, P5 of injection of currents Ig into each gate of the power transistors 12, 14, 16 of the switch, the length of a current pulse P7, and the regulation time P8.
The regulating unit 94 is able to cause the supply current curves Igl, Ig2, Ig3 of the power transistors 12, 14, 16 to vary according to a profile P6 or several

predefined current profiles received from the memory 80. The current profile P6 can form a step pattern, like the one illustrated in Figure 10, or a decreasing exponential, as illustrated in Figure 11.
The regulating unit 94 is suitable for controlling the current generators 40 and 44 of the control circuits 26. 28 and 30. To this end, it is connected to digital-to-analogue converters, themselves connected to each of the generators 40, 44.
The checking unit 96 receives commands from the driving unit 79 to control driving units of the transistors 34, 36, 42 and 46. The checking unit 96 ensures that there is no recovery of conduction of the MOS transistors. Furthermore, the checking unit 96 provides tor triggering the injection of currents lg1, Ig2, Ig3 into the gates ot each of the transistors 12, 14, 16 at the predefined moments P3, P4, P5.
The operating parameters and the control parameters stored in the memory 80 comprise in particular the minimum tolerated duration P1 of a pulse on the gate of each power transistor, the minimum saturation delay P2, the moments P3, P4, P5 of injection of current into each gate of the power transistors 12, 14, 16, and the profile P6 of the decrease of the gate current.
The control device 24 and the control circuits 26, 28, 30 provide for precisely and rapidly controlling the group of the three transistors 12, 14, 16 while taking into account the operating state of each of these power transistors, the control device 24 being able to set up an emergency procedure in the event that one or more of these power transistors malfunctions.
The power transistors 12, 14. 16 exhibit different moments of transition from the conducting state to the non-conducting state and vice versa. These differences in moments of transition from one state to the other arise from minor differences in the behaviour of their silicon, and from their position in the power switching loop. The manufacturing disparity of the parameters of the packs 11A, 11B, 11C and the slight dissymmetries of the switching loop therefore bring about imbalances in the instantaneous distribution of the current in the parallel packs during the switching operations. This limits the use of the full cutoff power of the packs in the parallel assemblies.
In other words, the first transistor of the switch which switches must withstand a higher transient current than the others until the other transistors

mounted in parallel are fully on. For this reason, it is necessary to limit the nominal switching current of the converter, i.e. the current switched by the switch 10.
The packs 11 A, 11B, 11C are tested before they are used in order to precisely determine the relative differences between them. The triggering moments P3, P4, P5 of the current Ig are determined as a function of these differences. The checking unit 96 of the control device triggers the switching on and switching off of the current generators 40, 44 in order that the group of power transistors 12, 14, 16 switches to the conducting state at the same moment as illustrated in Figure 11 so that the nominal current of the converter can be increased.
As a variant, the current generators 40, 44 can be implemented by voltage regulators and amplifiers.
In the control circuits of the prior art, the energy which Is used to switch the power transistors 12, 14, 16 is dissipated in resistors while, advantageously, in the present invention, this energy is recovered by the capacitor 50. Consequently, the igniter 6 consumes less energy and the components of the control circuits 26, 28, 30 are not heated and therefore not damaged.
In other words, the principle of driving the gate/emitter pair of a power transistor used in the control circuit of the present invention provides for dissipating energy upon igniting the power transistors only over small steps. This has the effect of dividing by a factor of 10 to 50 the energy dissipated by the circuits 26, 28, 30 when the gates of power transistors are ignited. Specifically, the energy is dissipated only during steps 60 and 70 and it is not necessary to artificially increase the intrinsic capacitor 32 of the power transistors 12, 14, 16 by the addition of an additional external capacitor to adjust an RC circuit.

CLAIMS
1.- A circuit (26. 28, 30) for controlling the opening and closing of a power electronics component (12, 14, 16), the power electronics component (12, 14, 16) having a gate electrode, an emitter electrode and a collector electrode, characterized in that the circuit comprises an H-bridge comprising:
- a first vertical branch (33A) comprising a first sw/itch (34) and a first current generator (40) controlled digitally, the first switch (34) being separated from the first current generator (40) by a middle point (32A) intended to be connected to the emitter electrode of the power electronics component (12, 14, 16); and
- a second vertical branch (33B) parallel to the first vertical branch (33A), the second vertical branch (33B) comprising a second switch (36) and a second current generator (44) controlled digitally, the second switch (36) being separated from the second generator (44) by a middle point (32B) intended to be connected to the gate electrode of the power electronics component (12, 14, 16);
- the first current generator (40) being suitable for delivering a supply
current (Ig) directed in a first direction (F1) in order to supply the gate electrode of
the power electronics component (12, 14, 16); and the second current generator
(44) being suitable for delivering a supply current (Ig) directed in a second
direction (F2) opposite to the first direction (F1) in order to supply the emitter
electrode of the power electronics component (12,14, 16).
2.- A control circuit (26, 28, 30) according to Claim 1, in which the H-bridge includes a third switch (42) connected in parallel to the first current generator (40), and a fourth switch (46) connected in parallel to the second current generator (44), and in that the circuit (26, 28, 30) includes a current source (50, 57) suitable for supplying the H-bridge, said current source being connected between, on the one hand, the first (34) and the second (36) switches, and, on the other hand, the first (40) and the second (44) current generators.
3.- A control circuit (26, 28, 30) according to Claim 2, in which the voltage source (50, 57) comprises a capacitor (50).
4.- A control circuit (26, 28, 30) according to any one of Claims 1 to 3, in which the switches (34, 36, 42, 44) are MOS transistors.
5.- A method for driving a control circuit (26, 28, 30) according to any one of Claims 1 to 4, characterized in that it includes, upon a command for closing the

power electronics component (12, 14, 16), a step (62) for the delivery of a supply current (Ig) by the first current generator (40), the second switch (36) being in the state of conduction in the first direction (F1).
6.- A driving method according to Claim 5, which method includes a preliminary step (60) for placing the second switch (36) into the stale of conduction in said first direction (F1), the first switch (34) being in the state of conduction in said first direction (PI).
7.- A driving method according to either Claim 5 or Claim 6 and implemented by the circuit according to Claim 2, which method includes:
- a step {64) for placing the third switch (42) into the state of conduction in the first direction (F1), the second switch (36) being in the state of conduction in the first direction (F1);
- a step (64) for the delivery, by the current source (50, 57). of a current pulse directed in the first direction (F1).
8.- A driving method according to any one of Claims 5 to 7, which method includes, upon a command for opening the power electronics component (12, 14, 16), a step (70) for the delivery of a supply current (Ig) by the second current generator (44).
9.- A driving method according to Claim 8 and implemented by the circuit according to Claim 2, which method includes a preliminary step (68) for placing the fourth switch (46) into the state of conduction in said second direction (F2), the third switch (42) being in the state of conduction in said second direction {F2).
10.- A driving method according to either Claim 8 or Claim 9 implemented by the circuit according to Claim 2, which method includes:
- a step (72) for placing the first (34) and the fourth (46) switches into the state of conduction in said second opposite direction (F2); and
- a step (72) for the delivery, by the current source (50, 57), of a current pulse in said second direction (F2).
11.- A driving method according to either Claim 7 or Claim 10 and implemented by the circuit according to Claim 3, in which the step (64, 72) for delivering the current pulse is implemented by the discharging of the capacitor (50),

12.- A driving method according to any one of Claims 5 to 11, in which the step for delivering a supply current (Ig) comprises a step {62, 70) for the gradual decrease over time in the supply current (Ig) according to a predefined profile.
13.- A device (24) for controlling at least one control circuit (26, 28. 30) according to any one of Claims 1 to 4, the control device (24) being suitable for receiving power controi instructions, and for controlling the control circuit (26, 28, 30) in order to open and close at least one power electronics component (12, 14, 16) according to the power control instructions, the device (24) comprising;
- a driving unit (79) able to convert power control instructions into signals for controlling the opening and/or closing of the switches (34. 36, 42, 46) and into signals for controlling the switching on and/or switching off of the current generators (40, 44) of the control circuit (26, 28. 30);
- a memory (80) for storing operating parameters (PI, P2. P3, P4, P5, P6. P7, PS) of the or each power electronics component (12, 14, 16), and control parameters for the current (Ig) intended to be applied to the gate electrode and to the emitter electrode of the or each power electronics component, said memory (80) being erasable and rewritable; and
- a peripheral logic unit (82) able to receive from said memory (30) the operating parameters and the control parameters for the supply current (Ig), the peripheral logic unit (82) being able to execute tasks for the driving unit (79) according to the received operating parameters and current control parameters.
14.- A control device (24) according to Claim 13, the device comprising at least one timer (92, 94) suitable for timing the moments of transmission of the control signals for opening and/or closing the switches (34, 36, 42, 46) based on the operating parameters and the control parameters received from the memory (80).
15.- A control device (24) according to either Claim 13 or Claim 14, the device comprising a regulating unit (94) suitable for delivering digital commands for varying the supply current (Ig) according to a predefined profile (P6) to a digital-to-analogue converter in order to control the current generators (40, 44).
16.- A control device (24) according to any one of Claims 13 to 15, the device comprising:

- a circuit (84) for acquiring information relating to the voltage (VCE) between
the collector electrode and the emitter electrode of the power electronics
component (12, 14, 16), and
- a time-domain filtering block (88) for filtering information acquired by the
acquisition circuit (84),
- the driving unit (79) being suitable for determining the state of the power
electronics component (12, 14, 16) based on information filtered by the time-
domain filtering block (88), the driving unit (79) being also able to control the
consistency between the power control instructions and the state of the power
electronics component (12, 14, 16).
17.- An igniter (6) comprising:
- a control device (24) according to any one of Claims 13 to 16, and
- an erasable and rewritable memory (23), said memory (23) being
equipped with electrical contacts suitable for being connected to a computer in
order to receive control parameters and operating parameters, said memory (23)
being connected to the memory (80) of the control device (24) in order to transmit
to it said control parameters and said operating parameters.
18.- An assembly comprising a control circuit (26, 28, 30) according to any one of Claims 1 to 4 and a control device (24) according to any one of Claims 13 to 16 for controlling this control circuit (26, 28, 30).