Claims:CLAIMS
I/We Claim, 1.A tri-level digital to analog converter (DAC) comprising:a first set of switches turned on to cause a first analog valuewith a first error as anoutput fora first digital value; anda second set of switches turned on to cause a second analog value with a second error as theoutput for a second digital value;wherein, both the first set of switches and the second set of switches are turned on to cause athird analog value, proportional to the first error and the second error, as the output for adigital value equal to zero, and both the first set of switches and the second set of switchesare turned off to cause a fourth analog value equal tozeroas the output for a fourth digitalvalue representing a reset state.2.The tri-level DAC of claim 1, further comprising:a positive reference voltage source, a negative reference voltage source and a common modevoltage source, in that, the first set of switches, the second set of switches and a first outputterminal are electrically coupled to each other to provide the first analog value, secondanalog value, third analog value and fourth analog value on the first output terminal,wherein the first error and the second error are due to mismatch within the first set ofswitches and the second set of switches.3.The tri-level DAC of claim 2, further comprising a third set of switches and a fourth set ofswitches electrically coupled with the positive reference voltage source, the negativereference voltage source, the common mode voltage source, the first set of switches, thesecond set of switches, the first output terminal and a second output terminal to form a
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differential DAC circuitry, in that, the first, the second, third, and the fourth analog values are provided across first output terminal and the second output terminal. 4.The tri-level DAC of claim 2, wherein the first digital value is represented in two bits as 01,second digital value is 10, third digital value is 00 and fourth digital value is 11, in that, twobits are coupled to the first, the second, the third, and the fourth set of switches such that“0” turns the switches on and “1” turns switches off to provide the first, the second, the thirdand the fourth analog value corresponding to the first, the second, the third, and the fourthdigital value.5.A high-speedanalog to digital convertor (ADC) comprising:
a subtractor configured to generate a difference signal as a difference of an input analogsignal and a feedback analog signal;
a loop filter configured to perform anti-aliasing filtering on the difference signal to providea filtered difference signal;
a sampler configured to generate a sequence of samples of the filtered difference signal;
an internal ADC with three level quantizer is configured to convert each sample tocorresponding one of a three digital values; and
a tri level digital to analog convertor (DAC) configured to generate the feedback analogsignal corresponding to the three digital values such that, an element mismatch error in thefeedback analog signal corresponding to one of the levels is a combination of the error in theother two levels.6.The high-speed ADC of claim 5, wherein the tri level DAC further comprising;a first set of switches turned on to cause a first analog value with a first error as an outputfor a first digital value; and a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state
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7.A method of converting the digital bits representing a positive, a negative and a zero valueto corresponding analogvalues comprising:converting the digital bits representing the positive value to first positive analog level;converting the digital bits representing thenegativevalue to first negative analog level;andconverting the digital bits representing the zero value to ananalog level that is centredbetween the positive analog level and the negative analoglevel even when the positiveanalog level and the negative analog level are shifted by a first error and a second error dueto an element mismatch.8.The method of claim 7, further comprising generating a zero analog value for a digital signalrepresenting a reset.9.A method, system, and apparatus providing one or more features as described in theparagraphs of this specification.Date: 16-09-2019 Signature………………………
(OMPRAKASH S.N)
Agent for Applicant
IN / PA - 1095 , Description:Form 2
The Patent Act 1970
(39 of 1970)
AND
Patent Rules 2003
Complete Specification
(Sec 10 and Rule 13)
Title
A Digital to Analog Converter Tolerant to Element Mismatch
Applicant(s)
Steradian Semiconductors Private Limited
Nationality
India
Address
216, Arcade at Brigade Metropolis, Whitefield Main Road,
Bangalore - 560048, Karnataka, India.
The following specification, particularly describes the invention and the manner in which it is to be performed.
2
DESCRIPTION
FIELD OF INVENTION
[0001] Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to Embodiments of the present disclosure relate to data processing data processing data processing data processing data processing data processing data processing data processing data processing data processing electronic deviceselectronic devices electronic deviceselectronic devices electronic deviceselectronic devices electronic devices electronic devicesand in and in and in particular particular particular relatesrelatesrelates relates to a Digital to Analog Converter igital to Analog Converter igital to Analog Converter igital to Analog Converter igital to Analog Converter igital to Analog Converter igital to Analog Converterigital to Analog Converter igital to Analog Converter (DAC) (DAC) tolerant tolerant tolerant tolerant to elements lements lements lements mismatch ismatchismatch .
RELATED ART
[0002] DACs are often employed to convert digital data to analog values. Particularly, in a high speed and high-resolution analog to digital convertor (ADC), the DACs are employed in a feedback loop of the ADC for noise shaping and for other benefits as is well known in the art.
[0003] Quantization noise is often reduced by implementing more number of quantization levels. In such case, implementing the DAC with higher number of levels presents a stringent requirement on matching the characteristics of the elements.On the other hand, implementing the DAC with fewer levels increases the quantization noise of the ADC. In one conventional implementation, a three level DAC (Tri-level DAC) is employed as a tradeoff. However, in such conventional Tri-level DAC, mismatch between the elements causes an error, thereby reducing the operational bandwidth and/or dynamic range of the ADC.
[0004] One conventional Tri-level DAC implementation is described in a paper titled “A 174.3dB FoM VCO-Based CT ?S Modulator with a Fully Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130nm CMOS” by Shaolan Li et.al published in the proceedings of IEEE , ESSCIRC 2016, which is incorporated herein by reference. As may be appreciated, in this conventional Tri-level DAC, three different paths are excited for the three codes/levels (+1,0,-1) and mismatch among elements such as switches, routing resistance, other sources, causes the transfer characteristics of the conventional DAC to be non-linear. Further, as may be seen, the signal dependent currents are drawn from Vrefp (DAC reference) resulting in distortion due to finite series impedance to Vrefp generator. Further, in this Tri-level CMOS DAC, control signals require to swing rail-to-rail, thereby rendering itnot suitable for low-voltage digital clock driver implementation.
[0005] Another conventional Tri-level DAC is disclosed in the US patent US 9397676, which is incorporated herein by reference. As may be appreciated, in this conventional Tri-level DAC,the level zero is implemented as diverting the DAC current to a reference path. Further a digital encoder/mapper block is incorporated to generate such control signals to control the DAC. As may be seen, any mismatch in level 1 (say 1+?) and -1 (say -1+?) is not compensated in level 0
3
and thus, resulting in a distortion. Also, this DAC has time-varying output impedance (in practical scenarios where current sources have finite output impedance) and hence when feeding its output to a continuous time circuit causes modulation.
SUMMARY
[0006] According to a According to aAccording to a According to a According to aAccording to aAccording to a According to an aspect, a tri n aspect, a trin aspect, a tri n aspect, a trin aspect, a trin aspect, a tri n aspect, a trin aspect, a trin aspect, a tri -level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to cause a first analog value with error as output for digital of switches turned on to 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of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value w value, a second set of switches turned on to cause analog value wvalue, a second set of switches turned on to cause analog value with a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as ith a second error as the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and the output for a second digital value, wherein, both first set of switches and switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, proportional the switches are turned on to cause a third analog value, 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proportional the switches are turned on to cause a third analog value, proportional the combination of combination of combination of combination of combination of combination of combination of first error first error first error first error first error first error and the second error, as outand the second error, as out and the second error, as out and the second error, as out and the second error, as outand the second error, as out and the second error, as outand the second error, as out and the second error, as out and the second error, as outand the second error, as outand the second error, as outand the second error, as outand the second error, as outand the second error, as out and the second error, as out put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of put for a digital value equal to zero, and both the first set of switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero switches and the second set of are turned off to cause a fourth analog value equal zero as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state. as the output for a fourth digital value representing reset state.
[0007] According to another According to another According to another According to another According to another According to another According to another According to another According to another According to another aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises aspect, a high speed analog to digital convertor (ADC) comprises subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and subtractor configured to generate a difference signal as of an input analog and a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform anti a feedback analog signal, loop filter configured to perform antia feedback analog signal, a loop filter configured to perform anti -aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on aliasing filtering on the difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate difference signal to provide a filtered signal, sampler configured generate sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, asequence of samples the filtered difference signal, asequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, a sequence of samples the filtered difference signal, an internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer internal ADC with three level quantizer is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one ofis configured to convert each sample corresponding one ofis configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of is configured to convert each sample corresponding one ofis configured to convert each sample corresponding one of a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri a three digital values; and tri level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal level digital to analog convertor (DAC) configured generate the feedback signal corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback corresponding to the three digital values such that, an element mismatch error in feedback analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the analog signal corresponding to the three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same. three digital values is substantially same.
[0008] According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting According to yet another aspect, a method of converting the digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a digital bits representing a positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the positive, a negative and zero value to corresponding analog values comprises converting the digital bits representing the digital bits representing the digital bits representing thedigital bits representing the digital bits representing the digital bits representing the digital bits representing the digital bits representing thedigital bits representing the digital bits representing the digital bits representing the digital bits representing thedigital bits representing thedigital bits representing thedigital bits representing thedigital bits representing the positive value to first analog level positive value to first analog level positive value to first analog level positive value to first analog levelpositive value to first positive analog level positive value to first analog level positive value to first analog levelpositive value to first positive analog level positive value to first analog level positive value to first analog level positive value to first analog level positive value to first analog level positive value to first analog level positive value to first analog levelpositive value to first positive analog levelpositive value to first positive analog level positive value to first analog level positive value to first analog levelpositive value to first positive analog levelpositive value to first positive analog level positive value to first analog level, converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits converting the digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the negative value to first analog level and converting digital bits representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive arepresenting the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive representing the zero value to a analog level that is centred between positive level and nalog level and nalog level and nalog level and nalog level and nalog level and nalog level and nalog level and nalog level and the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are the negative analog level even when positive and are shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch. shifted by a first error and second due to an element mismatch.shifted by a first error and second due to an element mismatch.
[0009] Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shouSeveral aspects are described below, with reference to diagrams. It shou Several aspects are described below, with reference to diagrams. It shou ld be understood ld be understood ld be understood ld be understood ld be understood ld be understood ld be understood that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full that numerous specific details, relationships, and methods are set forth to provide full understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will understanding of the present disclosure. Skilled personnel in relevant art, however, will
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readily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be pra readily recognize that the present disclosure can be pra readily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be prareadily recognize that the present disclosure can be pra readily recognize that the present disclosure can be practiced without one or more of the specific cticed without one or more of the specific cticed without one or more of the specific cticed without one or more of the specific cticed without one or more of the specific cticed without one or more of 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other methods, etc. In instances, well details, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, well details, or with other methods, etc. In instances, well details, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, well details, or with other methods, etc. In instances, well details, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, well details, or with other methods, etc. In instances, welldetails, or with other methods, etc. In instances, well -known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not known structures or operations are not shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure.shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure.shown in detail to avoid obscuring the features of present disclosure.shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure.shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure. shown in detail to avoid obscuring the features of present disclosure.
BRIEF DESCRIPTION OF DRAWINGS
[0010] FIG.1 is block diagram illustrating a high speed analog to digital converter (ADC) in an embodiment.
[0011] FIG. 2 is a block diagram illustrating a manner in which element mismatch error in a tri-level DAC may be reduced in an embodiment.
[0012] FIG. 3 illustrates the analog signal generated corresponding to the three digital values in an embodiment.
[0013] FIG. 4 is an example DAC providing analog signal with reduced error due to element mismatch in an embodiment.
[0014] FIG. 5 is a graph illustrating error in the feedback current in an embodiment.
[0015] FIG. 6A is an example of DAC in one embodiment providing differential analog signal.
[0016] FIG. 6B is an alternative embodiment of the DAC.
[0017] FIG. 7 is an example internal ADC with three quantization level in an embodiment.
[0018] FIG.8 is a latch providing interconnect between internal ADCand the DAC in an embodiment.
[0019] FIG. 9 is a graph illustrating the operation of the DAC in one embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EXAMPLES
[0020] FIG.1 is block diagram illustrating a high speed analog to digital converter (ADC) in an embodiment. The high-speed ADC 101 is shown comprising a subtractor 110, loop filter 120, sampler 130, internal ADC 140 and a DAC 150. Each block is described in further detail below.
[0021] The loop filter120 performsanti-aliasing filtering of the signal received on path 112 to removes the high frequency noise due to sampling, quantisation and other noise generated in the high-speedADC 101. The loop filter may be implemented as passive or active RC filters and perform integration operation on the difference signal received on path 112. Loop filter 110 provides the filtered signal on path 123.
[0022] The sampler 130 samples the filtered signal on path 123to generate samples of the filtered signal on path 134 for comparison. The sampler 130 may be implemented to sample at an oversampling rate (the sampling at a rate greater than minimum required rate referred as Nyquist
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rate as is well known in the art). Due to high sampling rate and noise shaping, the high-speed ADC 101 achieves a resolution of larger number of bits by incorporating a converter of fewer bits. For example, a one-bit converter or 1.5-bit converter may be employed to generate 12-16 bit digital signal by adapting the sampling rate that is higher than the required rate as is well known in the art. The samples are provided on the path 134.
[0023] The internal ADC 140 converts each sample to corresponding digital value. For example, the internal ADC 140 may be implemented with two levels quantizer (not shown) and a comparator (not shown) to generate a one-bit digital value. The comparator may compare the sampled value with two quantization levels to generate a digital 1 or 0 bit. Alternatively, the internal ADC may be implemented with three level quantizer and a three-level comparator to generate1.5 bit digital values.The digital values are provided on the path 145.
[0024] The DAC 150convertsthe digital values received on the path 145 to the corresponding analogsignal. The DAC may generate the analog signal with values correspondingto the received digital values in the form of a voltage or a current corresponding to the digital values received on the path145. The analogsignal may be generated as a differential signal or as a single ended common mode signal suitable for generating a difference signal by the subtractor 110. The analog signal is provided on path 151.
[0025] The subtractor 110 generates a difference of the input analog signal on path 105 and the signal received on path 151. The difference may be generated by subtracting the signal on path 151 from the input signal on path 105. The signal on the path 151 required to be faithful representation of the digital values on path 145 for high resolution and accurate conversion of the input analog signal to the digital values.
[0026] As mentioned earlier, the conventional DACs introduce error in the analog signal presented to subtractor due to non-linearity in the elements, there by not producing a faithful representation of the digital values to the subtractor. Such error causes reduction of both speed and resolution of the ADC.
[0027] In one embodiment, the DAC 150 is implemented to produce an analog value on path 151 with reduced error thereby enhancing the operable speed and resolution of the ADC 101. In that, the element mismatch error is reducedwhile converting the digital value to corresponding analog value. The ADC 101 provides the digital value on path 109 corresponding to the analog input signal received on path 105.
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[0028] FIG. 2 is a block diagram illustrating a manner in which element mismatch error in a tri-level DAC may be reduced in an embodiment. As shown, in the block 210, a firstanalog value corresponding to digital bits representing a positive level (+1) is generated. In that, the first analog value comprises first error due to element mismatch. In the block 220, a second analog value corresponding todigital bits representing a negative level (-1)is generated. In that, the second analog value comprises second error due to element mismatch. In the block 230, a thirdanalog value corresponding to digital bits representing a zero level (“0”)is generated. In that, third analog value is centred between the first and the second analog value so that, the three digital values are represented using three analog values such that the difference between first and the third analog value and the second and third analog values are same or substantially same. In the block 240, a fourth analog value corresponding to a reset signal is generated. In that, the fourth analog value is independent of the first, second and the third analog values. In one embodiment the fourth analog value is generated as equal to zero (voltage/current).
[0029] FIG. 3 illustrates theanalog signal generated corresponding to the three digital values in an embodiment. The level 310 represents a value of the analog signal generated corresponding to first digital value (for example, in binary form the first digital value may be represented as „01?). Similarly, level 320 represents a value of the analog signal generated corresponding to second digital value (for example, in binary form the second digital value may be represented as „10?). The level 330 represents a value of the analog signal generated corresponding to third digital value (for example, in binary form the third digital value may be represented as „00?).
[0030] The level 340 represents a value of the analog signal generated corresponding to a reset digital value (for example, in binary form the reset may be represented as „11?). As may be appreciated, the analogvalue 330 corresponding to thedigital zero (00) is positioned at the centre between levels 310 and 320, while the analoglevel 340 corresponding to the reset has a value zero. In one embodiment, analog values 310-340 represent a current provided as analog signal. In an alternative embodiment, the analog values 310-340 represent a voltage provided as analog signal. In yet another embodiment, the levels 310-340 may represent values of a parameter (say power, for example) other than voltage and current.
[0031] In contrast to the conventional DACs, at least, the DAC 150 provides a feedback signal with value 330 instead of a zero-valuecorresponding to a zero digital value. As a result, error due to elements mismatch is reduced while converting a digital zero to corresponding analog value.
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Further, the DAC produces a fourth level equal to zero analog signal for a reset. In one embodiment, this reset is used after sending each and every state to remove any memory effect.
[0032] FIG. 4 is an example DAC providing analog signal with reduced error due to element mismatch in an embodiment. The DAC 401 is shown comprising current source 410, first reference voltage terminal 420A and B, second reference voltage terminal 430, switches 440A-440D, and the analog signal output port 450. Each element is further described below.
[0033] In operation, for example, when digital value is 01, the switches 440B and Dare turned on and switches 440C&A are turned off, thereby allowing current 451 to flow to the analog signal port 450. Similarly, when digital value is 10, the switches 440B and D are turned off and switches 440C and A are turned on, thereby allowing a current 452 (negative current) to flow to the analog signal port 450. When digital value is 00, the switches 440BandC are turned on and 440A and D are turned off, thereby allowing current 453 (error current) to flow to the analog signal port 450.When digital value is 11 (or by any other reset signal), the switches 440A and D are turned on and 440B and C are turned off, thereby allowing zero current flow into the analog signal port 450.
[0034] As illustrated in FIG.5, considering a “+I” current as the required current value for digital value 01, the current 451, due to mismatch in the switches 440A-D may be represented as +I+?i1. Similarly,considering a “-I” current as the required current value for digital value 10, the current 452 due to mismatch may be represented as -I–?i2. Since the switches 440B and C are turned on for digital value 00, +I and –I cancels and the current 453 is equal to/proportional to ?i1+?i2. The current on port 450 may be provided to subtractor 110 on path 151 as a feedback current for more accurate conversion the input analog signal.
[0035] FIG.6A is an example of DAC in one embodiment providing differential analog signal. The differential DAC 601 is shown comprising supply 610, common mode supply 620A and B, reference voltage 630A and B, current source 640A and B, switches 650A-H, transconductance amplifier 660A and B, and differential analog signal output port 609A and B. Each element is further described below.
[0036] The supply 610 provides a positive voltage to the DAC 601. The supply 610 may be a drain voltage Vdd when the switches 650A-H are implemented with CMOS transistors. The reference voltage 630 provide supply sink to the DAC 601. The reference voltage 630 may be set to Vss or any other negative reference voltage when the 650A-H are implemented with CMOS transistors.
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[0037] The common mode supply 620A and B provide another reference voltage to adjust the output current/voltage corresponding to the digital value. For example,the common mode supply 620 may be adjusted to set the levels of the converted analog signal corresponding to digital values suitable for subtraction by the subtractor 110. Accordingly, the supply 610 (i.e., Vdd), the reference voltage 630 (Vss) and the common mode supply 620A and B are adjusted such that, the switches 650A-H turn on and off by a digital control signal.
[0038] In one embodiment, the current sources 640A and B operate to send a constant current through the path 641 and 642. The current sources 640A and B may be deployed by way of electronic circuitry (such as buffers) to maintain a constant current on the paths 641 and 642. The impedance mismatch between the switches 650A-H may result in unequal current division resulting in the mismatch error. The transconductance amplifier 660A and 660B is configured to convert voltage to current to provide current similar to the constant current sources 640A and B.
[0039] The switches 650A-H operate to cause a current proportional/corresponding to the digital value flow into and/or out (negative current) the differential port 609 A and B. In one embodiment, the switches are implemented as NMOS (Metal Oxide semiconductor transistor), accordingly, the gate terminal of the NMOS transistors is provided with control digital signal to drive the transistors to on and/or off to cause the analog signal current to flow to the differential port 609A and B.
[0040] In one embodiment, the switches 650B, C, E and G are turned on and switches 650A, D, F and H are turned off when the digital value is 01. The switches 650F, H, A and D are turned on and switches 650E, G, B and C are turned off when the digital value is 10. The switches 650 B, F, H and C are turned on and switches 650 A, E, G and D are turned off when the digital value is 00. The switches 650 A, E, G and D are turned on and switches 650 B, F, H and C are turned off when the digital value is 11. In that, the digital values 10, 01 and 00 are representing three quantization levels of the internal ADC 140 and digital value 11 representing the reset signal. FIG. 6B illustrates the alternative embodiment in which the transconductance amplifier 660A-660B is incorporated to reduce the switching voltage range. In FIG. 6A, the switching range of the switches 650C, D, H, and G is between Vdd and Vcm. Due to the position of the transconductance amplifier as in FIG. 6B, the switching range of the switches 650C, D, H, and G reduces to 0 to Vcm.
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[0041] FIG. 7 is an example internal ADC with three quantization levels in an embodiment. The internal ADC 701 is shown comprising two differential comparators 710 and 720 comparing the incoming differential analog value (Vp, Vm) with (+Vrp, +Vrm) and (-Vrp, -Vrm) respectively. In that, their quantisation levels correspond to value greater than or equal to (Vp, Vm), less than or equal to (-Vrp, -Vrm) and in between the values (+Vrp, +Vrm) and (-Vrp, -Vrm). Accordingly, the two bits differential representations (Dp0, Dp1) and (Dm0,Dm1) are provided on path 145. In one embodiment, the Dp0, Dp1 may be equal to: 01 when the analog value is greater than or equal to(Vp, Vm), 10 when the analog value is less than or equal to (-Vrp, -Vrm), 00 when the analog value is between (+Vrp, +Vrm) and (-Vrp, -Vrm).
[0042] FIG. 8 is a latch providing interconnect between internal ADC 701 and the DAC 601 in an embodiment. In the FIG. 8, standard electronic circuit representation conventions apply. The latch 801 latches the signal on ports 810A-D on to ports 820A-D and holds the signal till next clock signal. In one embodiment, the port 810A is coupled to Dm0,the port 810B is coupled to Dp1, the port 810C is coupled to Dm1 and the port 810D is coupled to Dp0. The switches 830A-D reset thelatch 801, in that, the port 820A-D is connected to ground potential (returned to zero). Thus, the ports 820A-Dare reset to zero potential when the switches 830A-D are turned on and the port 820A-D holds the digital values(Dp0, Dp1) and (Dm0,Dm1) when the switches are turned off.
[0043] The ports 820A-D are coupled to the DAC 601 to operate switches 650A-H. In one embodiment, the port 820A (and its complimentary) is configured to drives the switches 650A, B, G and H. As an alternative, the port 820A alone may drive switches 650A, B, G and H, when switches A and B are implemented as complimentary to G and H.
[0044] Similarly, the port 820B drives the switches 650 C, D, E and F. The ports 820C and D may be coupled to drive another DAC element similar to 601 in a dual DAC configuration (not shown) to reduce the peak to average ratio. In that, operation of the two DACs is time interleaved thereby reducing the peak to average ratio of the DAC.
[0045] FIG. 9 is a graph illustrating the operation of the DAC in one embodiment. The graph is shown comprising the clock signal 910, digital first bit 920A, digital second bit 920B, latched signals 930A and 930B, and analog signal 950. The clock signal 910 is shown comprising RZ state (return to Zero). In this state, the switches 830A-830D are turned on to force the value on path 820A-D to zero (ground potential). Also, in this RZ state, all the switches 650A-H are tuned
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off. Accordingly, no current flows into the port 609A/B. Thus, the analog signal 950 (current) shown with zero level in the RZ state also corresponds to reset state.
[0046] When the clock 910 is high, the signal on path 810A-D is respectively latched to the path 820A-D. Accordingly, the 3 digital values represented in two bitsby the signal 920A and 920B are provided on path 810A and 810B. For example, when 920A is digital 1 and 920B is digital 0, the two bits are 01 representing one of the three values, similarly, when 920A is digital 0 and 920B is digital 1 the bits are 10, and when both 920A and 920B are digital 0, then bits are 00.
[0047] The graph/signal 930A and 930B represents the digital values in the return to zero (RZ) format. The signal 930A and 930B drives the switches 650A-H on or off. For example, when the signal 930A is high the switches 650A and B (and 650 C and D) are turned on and other switches are turned off. Accordingly, current value through port 609A is depicted in the graph 650.
[0048] The graph 650 represents the current signal on terminal 609A. As may be appreciated, the current value corresponding to digital value zero (00) is shown as ?i, an error current due to elements mismatch in the DAC 601. The current 650 is shown to have value zero in the reset state and the current 650 is shown to have an error from the desired value +I and –I for the digital values 01 and 10.
[0049] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-discussed embodiments,but should be defined only in accordance with the following claims and their equivalents.