DESC:
TECHNICAL FIELD
[0001] The present disclosure relates generally to field effect transistors (FET). In particular, the present disclosure relates to a tunnel field effect transistor (TFET) with improved failure threshold.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Traditionally, scaling of complementary metal oxide semiconductor (CMOS) technology required a novel transistor concept beyond fin field-effect transistors (FinFETs) preferably in sub 10nm technologies. Thermionic injection being a road block for reduction in sub threshold swing (SS), a novel concept that works on tunnel-based injection or band to band tunnelling (BTBT) rather than thermionic injection has been identified to be the way forward, which has led to Tunnel Field Effect Transistors (TFET) that have the potential to offer steep turn-on by gate-controlled carrier tunnelling from valance band to conduction band and minimize sub-threshold swing.
[0004] TFET is an experimental type of transistor, wherein, even though its structure is similar to a metal-oxide-semiconductor field-effect (MOSFET), the fundamental switching mechanism differs, making this device a promising candidate for low power electronics. TFETs switch by modulating quantum tunneling through a barrier instead of modulating thermionic emission over a barrier as in traditional MOSFETs. The basic TFET structure is similar to a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. A conventionally know TFET device structure includes a P-I-N (p-type, intrinsic, n-type) junction, in which electrostatic potential of intrinsic region is controlled by a gate terminal. Further, in exemplary operation, TFET device is operated by applying gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, band-to-band tunneling (BTBT) occurs when the conduction band of the intrinsic region aligns with valence band of the P region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and current can flow across the device. As the gate bias is reduced, the bands become misaligned and current can no longer flow.
[0005] With growth and development of transistor technology, various experiments are being conducted on TFETs by researchers to introduce new and advanced types of TFETs in the market. For example, researchers tried using SiGe source, spacer engineering, highly doped abrupt source profiles, double gate architectures, Band gap engineering using III-V materials and vertical tunnelling to introduce variations in TFETs. FIG. 1A illustrates a point TFET device in planar technology and similarly, FIG. 1B illustrates an area scaled TFET device in planar technology, which is also referred as line TFET, STBFET and Binary TFET, Green TFET, as available in the prior-art.
[0006] Further, in recent times, efforts have been made by different groups/researchers to understand long term reliability of tunnel FET devices. Further, investigations on Electrostatic discharge (ESD) behavior of TFET devices have also been made, wherein ESD is one of the major reliability concerns in sub-14nm node technologies. While ESD is a fundamental reliability threat to Integrated circuits (IC’s), it may occur at any stage from IC manufacturing / processing to packaging to handling. Such explorations at an early stage not only reduce design time, but also allow development of ESD robust protection concepts and devices. ESD investigations of TFET devices available in prior-art reveal that TFET devices fail early compared to their counterparts, which was attributed to non-uniform BTBT along the width, causing early filament formation and thermal fail. More specifically, ESD investigations of TFET devices available in the prior-art show that TFETs are vulnerable to ESD events and fail at very low (sub 1mA/µm) current.
[0007] While TFETs can outperform FinFETs for low power applications, threat imposed by ESD can be a bottleneck for the TFETs. There is therefore a need to provide a new, improved, efficient, and technically advanced TFET device that significantly improves ESD robustness as compared to TFET devices available in the prior-art. Further, there is also a need to provide new TFET device that improves failure current as compared to TFET devices available in prior-art.
[0008] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0009] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0010] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0011] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.

OBJECTS OF THE INVENTION
[0012] A general object of the present disclosure is to provide a tunnel field effect transistor (TFET) with improved failure threshold.
[0013] Another object of the present disclosure is to provide a TFET able to turn-on at low drain fields.
[0014] Another object of the present disclosure is to provide a TFET with reduced filament formation.
[0015] Another object of the present disclosure is to provide a TFET with improved thermal stability.
[0016] Another object of the present disclosure is to provide a TFET that can offer protection against electrostatic discharge (ESD) in an integrated circuit.
[0017] Another object of the present disclosure is to provide a TFET that can act as an input-output driver in an integrated circuit.

SUMMARY
[0018] The present disclosure relates generally to field effect transistors (FET). In particular, the present disclosure relates to a tunnel field effect transistor (TFET) with improved failure threshold.
[0019] In an aspect, the present disclosure discloses a field effect transistor (FET), the FET comprising: a source region; a drain region, a gate; and a channel separating the source and drain regions. In an embodiment, the FET of the present disclosure can be a tunnel field effect transistor (TFET).
[0020] In another aspect, the source region can be of a first conductivity type and the drain region can be of a second conductivity type.
[0021] In an embodiment, the first conductivity type can be a p-type conductivity and the second conductivity type can be an n-type conductivity.
[0022] In another aspect, a channel separates the source region from the drain region. Said channel can be of a first conductivity type.
[0023] In another aspect, the silicide-blocking of the source and drain regions causes a lowering in current density across the FET and also causes current ballasting action across said FET. In another aspect, the silicide blocking of source and drain regions causes a delayed onset of electro-thermal instability, thereby improving failure threshold of the FET.
[0024] In another aspect, an epitaxial layer of the second conductivity type can be disposed within the source region and extending partially above said source region such that the epitaxial layer is sandwiched between the source region and the gate. Said epitaxial layer can be in direct contact with the channel, partially forming a p-n junction with the source region.
[0025] In another aspect, a pocket doped region of a second conductivity type can be disposed under the source region, which forces a band to band tunnelling (BTBT) under the source region to support the conduction of an injected drain current.
[0026] In another aspect, the pocket doped region under the source region further pre-empts an avalanche assisted BTBT at the drain-channel junction to allow uniform current to flow through the junction.
[0027] In another aspect, due to the BTBT at the source region, the device turn-on happens earlier, and at a lower drain voltage, as compared to FET known in the art without with avalanche assisted BTBT. Further, lower drain voltage further results in lower self-heating of the FET.
[0028] In another aspect, the source region and the drain region can be, independently, either partially or fully silicide-blocked from the gate. This delays the onset of eletro-thermal instability and improves failure threshold of the FET.
[0029] In an embodiment, the proposed FET can be inserted in an integrated circuit to offer electrostatic discharge (ESD) protection. In a further embodiment, the FET can also be used as an input-output driver in an integrated circuit.
[0030] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0031] FIG. 1A illustrates a point TFET device in planar technology as available in the prior-art.
[0032] FIG. 1B illustrates an area scaled TFET device in planar technology as available in the prior-art
[0033] FIG. 2A illustrates a cross-sectional view of proposed pocket TFET with drain side silicide blocking in Point Tunnel Filed effect transistor configuration in accordance with an exemplary embodiment of the present disclosure.
[0034] FIG. 2B illustrates a cross-sectional view of proposed pocket TFET with drain side silicide blocking in an area scaled / vertical tunnel filed effect transistor configuration in accordance with an exemplary embodiment of the present disclosure
[0035] FIG. 3A illustrates transmission line pulsing (TLP) characteristics of proposed Point TFET in accordance with an exemplary embodiment of the present disclosure compared with a TFET device as available in the prior-art for determining thermal failure current.
[0036] FIG. 3B illustrates transmission line pulsing (TLP) characteristics of proposed Point TFET with different drain side silicide blocking length (DOP)in accordance with an exemplary embodiment of the present disclosure compared with a TFET device as available in the prior-art for determining thermal failure current.
[0037] FIG. 4A illustrates a cross-sectional view of proposed TFET with silicide blocking and without pocket implant in Point Tunnel Filed effect transistor configuration in accordance with an exemplary embodiment of the present disclosure.
[0038] FIG. 4B illustrates a cross-sectional view of proposed TFET with silicide blocking and without pocket implant in an area scaled / vertical tunnel filed effect transistor configuration in accordance with an exemplary embodiment of the present disclosure.
[0039] FIG. 5A illustrates a cross-sectional view of proposed pocket TFET without silicide blocking and with pocket implant in Point TFET configuration in accordance with an exemplary embodiment of the present disclosure.
[0040] FIG. 5B illustrates a cross-sectional view of proposed pocket TFET without silicide blocking and with pocket implant in an area scaled / vertical TFET configuration in accordance with an exemplary embodiment of the present disclosure.
[0041] FIG. 6A illustrates an input/output (I/O) pad using proposed Point TFET device in accordance with an exemplary embodiment of the present disclosure.
[0042] FIG. 6B illustrates an input/output (I/O) pad using proposed Area Scaled / Vertical TFET device in accordance with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION
[0043] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0044] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0045] The present disclosure relates generally to field effect transistors (FET). In particular, the present disclosure relates to a tunnel field effect transistor (TFET) with improved failure threshold.
[0046] Electrostatic discharge is a fundamental reliability threat to Integrated circuits (IC’s), wherein ESD may occur at any stage from IC manufacturing/processing to packaging and from packaging to its handling. Tunnel FETs, on one hand, can outperform FinFETs for low power applications, but on the other hand, threat imposed by ESD can be a bottleneck as ESD investigations of conventional TFET devices show that TFETs are vulnerable to ESD events and fail at very low (sub 1mA/mm) current.
[0047] Thus, it an object of the present disclosure to solve the technical problems as recited above. Accordingly, the present disclosure proposes a TFET device that offers significantly improved ESD robustness. In an embodiment, the proposed TFET device solves the technical problem of ESD available in the TFET device of the prior-art by introducing a source side pocket and by introducing drain side silicide blocking.
[0048] In an exemplary embodiment, source side pocket can increase carrier tunneling at source-pocket junction, which offers a current ballasting action across the device width by mitigating non-uniform BTBT. Further, the source side pocket can mitigate early current filamentation due to absence of non-uniform BTBT. Furthermore, the source side pocket can lower the drain side field required to support the injected current, therefore enabling reduction in self-heating. Thus, the source side pocket helps in improving ESD robustness.
[0049] In an exemplary embodiment, drain side silicide blocking can delay onset of thermal filament and lowers self-heating, which in turn shifts thermal snapback and failure to higher currents.
[0050] In an embodiment, while recognizing that tunnel FET is being considered as a strong contender to replace FinFETs in sub-7nm node CMOS technologies, the present disclosure provides an improved TFET design that offers 5-6 times higher ESD robustness as compared to TFET devices that are available in the prior-art, without sacrificing performance.
[0051] Aspects of the present disclosure provide a new, improved, efficient, and technically advanced TFET device that significantly improves ESD robustness as compared to TFET devices available in the prior-art. Further, the proposed TFET device in the present disclosure improves failure current as compared to TFET devices that are available in the prior-art. In an embodiment, the proposed TFET device improves electrostatic discharge (ESD) robustness of TFET devices, and improves failure current by at least 6 times when compared to failure current of TFET devices that are available in the prior-art. In an embodiment, failure current can be further improved preferably by 3times when silicide blocking is deployed to TFETs, when compared to the failure current of TFET devices available in the prior-art.
[0052] An aspect of the present disclosure provides a field effect transistor having a fully silicided source and a fully silicided drain of a first conductivity type and a second conductivity type respectively, the source and drain being separated by a channel, wherein the fully silicided source and the fully silicided drain are disposed over a substrate. The proposed field effect transistor can further include a new conductivity type pocket region that is of a second conductivity type and is configured below the first conductivity type source.
[0053] In another aspect, the new conductivity type pocket region forms a p-n junction with the first conductivity source above it. In an aspect, the first conductivity type is p-type and the second conductivity type is n-type.
[0054] In an aspect, the proposed field effect transistor increases carrier tunneling at the junction of the fully silicided source and the new conductivity type pocket region, which offersa current ballasting action across the field effect transistor width by mitigating non-uniform BTBT, mitigates early current filamentation due to absence of non-uniform BTBT, and lowers drain side field required to support the injected current thereby reducing self-heating. In another aspect, carrier tunneling at the junction of the fully silicided source and the second conductivity type region (a pocket region) enables improvement of ESD robustness.
[0055] Another aspect of the present disclosure provides a field effect transistor having a fully silicided source and a fully silicided drain of a first conductivity type and a second conductivity type respectively, wherein the source and the drain are separated by a channel, and wherein the fully silicided source and the fully silicided drain are disposed over a substrate. The proposed field effect transistor can further include a new conductivity type pocket region that is of a second conductivity type and is configured below as well as partially above the first conductivity type source, wherein the new conductivity type pocket region that is partially above the first conductivity type source forms a p-n junction with the source and is sandwiched between the source and gate dielectric and is in direct contact with the channel. In an aspect, the first conductivity type is p-type and the second conductivity type is n-type.
[0056] Another aspect of the present disclosure provides a field effect transistor having a partially silicided source and a partially silicided drain of a first conductivity type and a second conductivity type respectively, wherein the source and the drain are separated by a channel, and wherein the partially silicided source and the partially silicided drain are disposed over a substrate. The proposed field effect transistor can further include a silicide blocked region between a silicided region and a gate. In an aspect, a new conductivity type pocket region can be provided below the first conductivity type source such that the new conductivity type pocket region forms a p-n junction with the first conductivity source above it. In an aspect, the first conductivity type is p-type, and the second conductivity typeis n-type.
[0057] Another aspect of the present disclosure provides a field effect transistor having a partially silicided source and a partially silicided drain of a first conductivity type and a second conductivity type respectively, wherein the source and the drain are separated by a channel, and wherein the partially silicided source and the partially silicided drain are disposed over a substrate. The proposed field effect transistor can further include a new conductivity type pocket region that is of a second conductivity type and can be configured below as well as partially above a first conductivity type source forming a p-n junction with the source and is sandwiched between the source and gate dielectric and is in direct contact with channel. The proposed field effect transistor can further include a silicide blocked region between a silicided region and a gate.
[0058] In an aspect, the new conductivity type pocket region can be provided below the first conductivity type source. In another aspect, the new conductivity type pocket region forms a p-n junction with the first conductivity source above it.In an aspect, the first conductivity type is p-type and the second conductivity type is n-type.
[0059] In an embodiment, the proposed field effect transistor can be used as an ESD protection device in input-output pad of an Integrated Circuit(IC). In another embodiment, the field effect transistor can be used as an I/O driver in input-output pad of an Integrated Circuit. In an exemplary instance, one or more of the proposed the field effect transistors can be used together as ESD protection devices or as I/O drivers in an Integrated Circuit.
[0060] FIG. 2A illustrates a cross-sectional view of proposed pocket TFET with drain side silicide blocking in Point Tunnel Field Effect Transistor configuration, in accordance with an exemplary embodiment of the present disclosure. FIG. 2B illustrates a cross-sectional view of the proposed pocket TFET with drain side silicide blocking in an area scaled/ vertical tunnel filed effect transistor configuration, in accordance with an exemplary embodiment of the present disclosure.
[0061] In an embodiment, as shown in FIGs. 2A and 2B,the proposed pocket TFET can include a similar structure as that of a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. FIG. 2B differs from FIG. 2A by having an n-Epi (epitaxial) layer. An existing TFET device structure consists a P-I-N (p-type, intrinsic, n-type) junction over a semiconductor wafer in which electrostatic potential of the intrinsic region is controlled by a gate terminal. In an exemplary embodiment, the proposed TFET can also operate by applying gate bias so that electron accumulation occurs in the intrinsic region, which can be in similar manner as existing TFETs available in the prior-art operates. At sufficient gate bias, band-to-band tunneling (BTBT) occurs when the conduction band of the intrinsic region aligns with the valence band of the p-type region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region, and current can flow across the device. As the gate bias is reduced, the bands become misaligned and current can no longer flow.
[0062] In an embodiment, apart from the source and drain terminals, and a P-I-N (p-type, intrinsic, n-type) junction over a semiconductor wafer, the proposed TFET according to the present disclosure is provided with a source side pocket202 and source side and drain side silicide blocking206a and 206b respectively.
[0063] In an exemplary instance, when grounded gate TFETs available in the prior-art are stressed under ESD condition, drain field increases to support the injected current through avalanche generated excess carriers. At higher stress conditions that result in higher drain field, Band to Band tunneling (BTBT) aids the impact ionization process, which is termed as avalanche assisted BTBT. The excess electrons due to avalanche assisted BTBT are collected at the drain terminal, however the holes flow through a substrate (semiconductor wafer), which increases substrate potential. Increased substrate potential causes band bending at the source-channel junction, which initiates BTBT at the source-channel edge. This leads to device turn-on. In TFET devices available in the prior-art, such a turn-on, which occurs at very high voltage may lead to immediate filament formation due to source side non-uniform BTBT, which significantly increases lattice temperature and leads to an early snapback and failure.
[0064] In an embodiment, in order to overcome this technical issue in the TFET devices available in the prior-art, the present disclosure proposes a TFET device 200 with pocket region 202 underneath the source 204, and silicide blocking 206a, 206b at the source side and drain side respectively. Proposed device 200 with pocket region 202 causes forced BTBT at the source side at an early drain voltage, which supports the conduction of injected drain current. An early source side BTBT avoids avalanche assisted BTBT at the drain-channel junction, which eventually allows uniform current conduction, attributed to missing non-uniform BTBT and filamentation. Dominance of BTBT action at the source 204 side, in the proposed structure/device, allows device turn-on at lower drain fields (or drain voltage) as compared to the field required for avalanche assisted BTBT in TFET devices available in the prior-art.
[0065] In an embodiment, due to lower turn-on fields, the proposed device experiences lower self-heating, which increases the failure current significantly. The source204 diffusion length can be increased further to increase the tunneling area and improve the failure current as shown in FIG. 3A. FIG. 3A illustrates transmission line pulsing (TLP) characteristics of proposed pocket TFET in accordance with an exemplary embodiment of the present disclosure compared with a TFET device as available in the prior-art for determining thermal failure current. As shown in FIG. 3A, the proposed device according to the present disclosure depicts 6 times improvement in thermal failure current.
[0066] In another embodiment, ESD robustness of the state of art TFET device can be increased by introducing drain side silicide blocking, as depicted in Fig. 3B. Silicide blocking increases the onset of thermal instability, which improves failure threshold further. FIG. 3B illustrates transmission line pulsing (TLP) characteristics of proposed silicide blocked TFET with different drain side silicide blocking length (DOP), in accordance with an exemplary embodiment of the present disclosure, compared with a TFET device as available in the prior-art for determining thermal failure current. As shown in FIG. 3B, the proposed device according to the present disclosure having DOP depicts 3 times improvement in failure current when compared to point TFET as available in the prior-art. For the purpose of experimentation, the source side silicide blocking length (SOP) was kept constant at 100nm to obtain results of FIG. 3B.
[0067] FIG. 4A illustrates a cross-sectional view of proposed TFET with silicide blocking in Point TFET configuration, in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 4A, the proposed TFET device is provided with silicide blockings206a and 206bat source side and drain side respectively.
[0068] FIG. 4B illustrates a cross-sectional view of proposed TFET with silicide blocking in an area scaled / vertical tunnel filed effect transistor configuration in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 4B, the proposed TFET device is provided with silicide blockings 206a and 206b at source side and drain side respectively, in accordance with an embodiment of the present disclosure.
[0069] In an embodiment, the introduction of silicide blockings206a and 206bdelays the onset of thermal filament and lowers the self-heating of the thermal filament, which in turn shifts thermal snapback and failure due to higher currents in the proposed TFETs.
[0070] FIG. 5A illustrates a cross-sectional view of proposed pocket TFET without silicide blocking and with pocket implant in Point TFET configuration in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 5A, the proposed TFET device is provided with a pocket implant 202 below source 204.
[0071] FIG. 5B illustrates a cross-sectional view of proposed pocket TFET without silicide blocking and with pocket implant in an area scaled / vertical tunnel filed effect transistor configuration, in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 5B, the proposed TFET device is provided with a pocket implant 202 below source 204, in accordance with an embodiment of the present disclosure.
[0072] In an embodiment, the introduction of source side pocket 202increases carrier tunneling at the source-pocket junction, which offers a current ballasting action across the device width by mitigating non-uniform BTBT, mitigates early current filamentation due to absence of non-uniform BTBT and lowers the drain side field required to support the injected current hence reduced self-heating. These attributes together help in improving the ESD robustness.
[0073] FIG. 6A illustrates an input/output (I/O) pad using Point TFET device, in accordance with an exemplary embodiment of the present disclosure. FIG. 6A shows the proposed TFET devices being used as an ESD protection device 602 and driver transistors 604, respectively inside an I/O pad. In an implementation, for ESD protection the proposed TFET with a pocket implant is used while for I/O driver the proposed TFET with silicide blocking is used.
[0074] FIG. 6B illustrates an input/output (I/O) pad using Area Scaled / Vertical TFET, in accordance with an exemplary embodiment of the present disclosure. FIG. 6B shows the proposed TFET devices being used as an ESD protection device 602 and driver transistors 606, respectively inside an I/O pad. In an implementation, for ESD protection the proposed TFET with a pocket implant is used while for I/O driver the proposed TFET with silicide blocking is used.
[0075] In an exemplary embodiment, the proposed pocket TFET devices can consider parameters and their range of values listed in Table 1 below as workable range of values for the parameters of said devices. However, it may be appreciated that such parameter and workable range may vary from one application to other application and from one structure to other. Any such variation in the parameters and the associate range still falls within the scope of the present disclosure.

Parameter Range
Gate length 50-400 nm
Junction depth 10-50 nm
SOP 10-100 nm
DOP 50-700 nm
Source diffusion length 100-700 nm
ND 5x1018 atoms.cm-3 - 1x1020 atoms.cm-3
NS 5x1019 atoms.cm-3 - 1x1021 atoms.cm-3
EOT 0.3 nm - 2 nm
Ge mole fraction in source 10% - 30%

Table 1: workable range of values for different parameters of a TFET device.

[0076] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0077] The present disclosure provides a tunnel field effect transistor (TFET) with improved failure threshold.
[0078] The present disclosure provides a TFET able to turn-on at low drain fields.
[0079] The present disclosure provides a TFET with reduced filament formation.
[0080] The present disclosure provides a TFET with improved thermal stability.
[0081] The present disclosure provides a TFET that can offer protection against electrostatic discharge (ESD) in an integrated circuit.
[0082] The present disclosure provides a TFET that can act as an input-output driver in an integrated circuit.

,CLAIMS:
1. A field effect transistor (FET) comprising:
a gate dielectric;
a source region of a first conductivity type wherein said source region is incorporated with a silicide-blocked region between the gate and source contact;
a drain region of a second conductivity type wherein said drain region is incorporated with a silicide-blocked region between the gate and drain contact; and
a channel separating said source region and said drain region,
wherein the silicide-blocking of said source region and drain region delays onset of Band to Band tunnelling (BTBT) Assisted thermal instability in said FET by offering lower current density across the said FET.

2. The FET as claimed in claim 1, wherein said FET is a tunnel field effect transistor (TFET).

3. The FET as claimed in claim 1, wherein an epitaxial layer of second conductivity type is disposed within and extending partially above the source region such that said epitaxial layer is sandwiched between the source region and the gate oxide and is in direct contact with channel, partially forming a p-n junction with the source region.

4. The FET as claimed in claim 1, wherein a pocket doped region of the second conductivity type is disposed under the source region to pre-empt avalanche assisted band to band tunnelling (BTBT) at drain-channel junction.

5. The FET as claimed in claim 1, wherein the source region is fully or partially silicide-blocked from the gate.

6. The FET as claimed in claim 1, wherein the drain region is fully or partially silicide-blocked from the gate.

7. The FET as claimed in claim 1, wherein first conductivity type is p-type.

8. The FET as claimed in claim 1, wherein first conductivity type is n-type.

9. The FET as claimed in claim 1, wherein said FET is an electrostatic discharge (ESD) protection device in an integrated circuit.

10. The FET as claimed in claim 1, wherein said FET is an input-output driver in an integrated circuit.