DESC:TECHNICAL FIELD
[0001] The present disclosure generally relates to the field of neuromorphic chips. In particular, it relates to a neuromorphic chip that is flexible and atomically thin and that can mimic true synaptic behaviour.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Neuronmorphic chip is a used for simulating structure and function of biological brain. Synapses are the only nodes that transmit information between neurons. At present, the construction and simulation of artificial neural synaptic and neural network systems are mostly implemented in the transistors or memorisistors. However, the coupling coefficient between the input and output electrical signals is fixed for the transistor or memristor in the form of electric excitation simulation, which is not conducive to the realization of complex computing functions. In order to solve this problem, the research group uses the material with adjustable performance to design the device structure, such as using torsional bilayer graphene to construct field effect transistor in the same device to achieve the neuronal excitement and inhibition of two functions, and by adjusting the gate pressure control synaptic plasticity. But the real neuron system is a set of data acquisition and information processing in one, the current artificial synapses in the absence of data-aware module will lead to a large number of redundant circuit and non-essential power generation, and therefore also limits the artificial neuron system Construct.
[0004] Neuromorphic computing is a rapidly growing field which involves developing technology for complex brain like circuits. It precisely deploys understanding of signal flow and computations occurring in real biological circuits called neurons to mimic behaviour of biological circuits. The driving factors for such a chip are tremendous demand for data and data analytics, miniaturization of sensors, sensors in military and medical fields, integration of artificial intelligence into machines without depending on massive supercomputing interfaces, and high cost of further miniaturization of integrated circuits. Other applications can range from gaming to driverless vehicles, drones to air transport and biotech/biomed/brain emulation, eye and ear implants etc.
[0005] Conventional neuromorphic chips such as IBM’s True north are volatile in nature. It means one need to train the neural network every time there is change in data set and store the synaptic weights on a digital flash memory. This is a manual process which requires human intervention. Moreover, every time the chip is turned-on, the synaptic weight is loaded from an external flash to on-chip memory (SRAM). Besides, due to digital nature of synaptic weight and analog nature of synaptic multiplication, the digital to analog (and vice versa) conversion further adds design and Si real state overhead and also consumes more power for their operation.
[0006] There is, therefore, a requirement in the art for a neuromorphic technology platform that is flexible, atomically thin and scalable in the third dimension, and that offers an adaptive, analogue synaptic behaviour.

OBJECTS OF THE PRESENT DISCLOSURE
[0007] It is an object of the present disclosure to provide a truly analog neuromorphic chip that can be with reduced size and hardware.
[0008] It is an object of the present disclosure to provide a flexible neuromorphic chip that can allow expansion in 3rd dimension and a biological organ like flexible form-factor.
[0009] It is an object of the present disclosure to provide a truly analog, flexible, and adaptive neuromorphic chip which consumes less power.

SUMMARY
[0010] The present disclosure generally relates to the field of neuromorphic chips. In particular, it relates to a neuromorphic chip that is flexible and atomically thin and that can mimic true synaptic behaviour.
[0011] An aspect of the present disclosure relates to a neuromorphic chip. The neuromorphic chip includes one or more analog neurons further including one or more integrators and one or more comparators. The one or more analogue neurons interconnected using a plurality of wired synaptic connections, in a same way as biological neurons. One or more non-volatile analog memory configured with the plurality of wired synaptic connections to add weighting parameter. The one or more non-volatile analog memory is configured to retain the added weighting parameter to facilitate quick training of the neuromorphic chip.
[0012] In an aspect, the one for more non-volatile analog memory may include any or combination of a tunnel field-effect transistor (TFET) and a metal oxide semiconductor field effect transistor (MOSFET).
[0013] In an aspect, the one or more non-volatile analog memory may be used in a signal path of the analog neurons.
[0014] In an aspect, the weighing parameter may be selected by any or the combination of programming of the one or more non-volatile analog memory, and an ON-state resistance of the one or more non-volatile analog memory in the signal path.
[0015] In an aspect, the ON-state resistance may be a function of a gate to source voltage and a threshold voltage of the one or more non-volatile analog memory.
[0016] In an aspect, the one or more non-volatile analog memory may include a first gate covered with grapheme, and may be configured to program and erase the one or more non-volatile analog memory, and a second gate may be configured to control program state of the one or more non-volatile analog memory.
[0017] In an aspect, gates of the one or more non-volatile analog memory may be kept opposite to each other and normal to the source-drain current flow direction are used.
[0018] In an aspect, channel of the one or more non-volatile analog memory may include material form a group of Transition Metal Dichalcogenide (TMD) semiconductors.
[0019] In an aspect, at least one of said one or more analog neurons may be developed using any or a combination of 2D material based CMOS or 2D material heterostructure based n/p-TEFTs.
[0020] In an aspect, the chip may be designed by integrating any or a combination of one or more neuron cell modules, axon modules, dendrite modules, synapse weight modules, ion integrator module, spike router module, and memory block module, at least one of these modules being designed and fabricated using said 2D material.
[0021] In an aspect, the neuromorphic chip may include an input layer operatively coupled to receive data from an interface controller. A neutral processing unit may be configured to receive the data from the input layer and process the received data. The neutral processing unit may include one or more neuro-cores. Each of the one or more neuro-cores may further include an array of neurons and synapses, the array being integrated with any or a combination of a router, spike decoder, spike encoder, and memory.
[0022] In an aspect, the router may enable formation of a 2D mesh of at least a part of the one or more neuro-cores. Nodes may be the neuro-cores and edges may be formed by connection of adjacent neuro-cores. Connection of a first neuron in a first neuro-core to a second neuron in a second neuro-core may be implemented by virtually sending a spike event through the network of routers.
[0023] In an aspect, the spike decoder may convert spike rate information into data required for computations inside the neuron. The spike encoder may convert the data back to spike information.
[0024] In an aspect, the neuron may integrate post-synaptic spikes, and may compare the integrated post-synaptic spikes with a threshold / membrane potential (Vmp) to produce a spike if the post-synaptic spikes are greater than membrane potential. The synapse may scale the pre-synaptic spikes according to synaptic strength / weight and transmit it to post-synaptic terminal.
[0025] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0027] FIG. 1A and 1B illustrates a biological neuron and a biological synapse respectively.
[0028] FIG. 1C illustrates an exemplary representation of a system level representation of a biological neuron, in accordance with an embodiment of the present disclosure.
[0029] FIG. 1D illustrates an exemplary representation of a system level representation of a biological neural network, in accordance with an embodiment of the present disclosure.
[0030] FIG. 2A illustrates an exemplary representation of Schematic of TMDC based point TFET and FIG. 2B illustrates an exemplary representation of Schematic of TMDC based Line TFET, in accordance with an embodiment of the present disclosure.
[0031] FIG. 3A illustrates an exemplary representation of proposed analog memory 300, FIG. 3B illustrates an exemplary representation of programmed threshold voltage vs. back control gate voltage of the proposed analog memory 300, AND FIG. 3C illustrates an exemplary representation of cell or schematic view of proposed analog memory 300, in accordance with an embodiment of the present disclosure.
[0032] FIG. 4 illustrates a typical Neuromorphic chip architecture.
[0033] FIG. 5 illustrates an exemplary representation of proposed neuromorphic chip architecture, in accordance with an embodiment of the present disclosure.
[0034] FIG. 6 illustrates an exemplary representation of block level architecture of neuro-core, in accordance with an embodiment of the present disclosure.
[0035] FIG. 7A illustrates digital implementation of integrate and fire Neuron, FIG. 7B illustrates digital representation of synapse, and FIG.7C illustrates analog implementation of neuron and synapse, in accordance with an embodiment of the present disclosure.
[0036] FIG. 8 illustrates an exemplary representation of a summary of the flow and methodology to realise the proposed flexible, analogue, adaptive and non-volatile neuromorphic chip technology platform, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0037] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0038] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0039] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0040] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
[0041] The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non – claimed element essential to the practice of the invention.
[0042] The present disclosure generally relates to the field of neuromorphic chips. In particular, it relates to a neuromorphic chip that is flexible and atomically thin and that can mimic true synaptic behaviour.
[0043] An embodiment of the present disclosure elaborates upon a neuromorphic chip. The neuromorphic chip includes one or more analog neurons further including one or more integrators and one or more comparators. The one or more analogue neurons interconnected using a plurality of wired synaptic connections, in a same way as biological neurons. One or more non-volatile analog memory configured with the plurality of wired synaptic connections to add weighting parameter. The one or more non-volatile analog memory is configured to retain the added weighting parameter to facilitate quick training of the neuromorphic chip.
[0044] In an embodiment, the one for more non-volatile analog memory can include any or combination of a tunnel field-effect transistor (TFET) and a metal oxide semiconductor field effect transistor (MOSFET).
[0045] In an embodiment, the one or more non-volatile analog memory can be used in a signal path of the analog neurons.
[0046] In an embodiment, the weighing parameter can be selected by any or the combination of programming of the one or more non-volatile analog memory, and an ON-state resistance of the one or more non-volatile analog memory in the signal path.
[0047] In an embodiment, the ON-state resistance can be a function of a gate to source voltage and a threshold voltage of the one or more non-volatile analog memory.
[0048] In an embodiment, the one or more non-volatile analog memory can include a first gate covered with grapheme, and can be configured to program and erase the one or more non-volatile analog memory, and a second gate can be configured to control program state of the one or more non-volatile analog memory.
[0049] In an embodiment, gates of the one or more non-volatile analog memory can be kept opposite to each other and normal to the source-drain current flow direction are used.
[0050] In an embodiment, channel of the one or more non-volatile analog memory can include material form a group of Transition Metal Dichalcogenide (TMD) semiconductors.
[0051] In an embodiment, at least one of said one or more analog neurons can be developed using any or a combination of 2D material based CMOS or 2D material heterostructure based n/p-TEFTs.
[0052] In an embodiment, the chip can be designed by integrating any or a combination of one or more neuron cell modules, axon modules, dendrite modules, synapse weight modules, ion integrator module, spike router module, and memory block module, at least one of these modules being designed and fabricated using said 2D material.
[0053] In an embodiment, the neuromorphic chip can include an input layer operatively coupled to receive data from an interface controller. A neutral processing unit can be configured to receive the data from the input layer and process the received data. The neutral processing unit can include one or more neuro-cores. Each of the one or more neuro-cores can further include an array of neurons and synapses, the array being integrated with any or a combination of a router, spike decoder, spike encoder, and memory.
[0054] In an embodiment, the router can enable formation of a 2D mesh of at least a part of the one or more neuro-cores. Nodes can be the neuro-cores and edges can be formed by connection of adjacent neuro-cores. Connection of a first neuron in a first neuro-core to a second neuron in a second neuro-core can be implemented by virtually sending a spike event through the network of routers.
[0055] In an embodiment, the spike decoder can convert spike rate information into data required for computations inside the neuron. The spike encoder can convert the data back to spike information.
[0056] In an embodiment, the neuron can integrate post-synaptic spikes, and can compare the integrated post-synaptic spikes with a threshold / membrane potential (Vmp) to produce a spike if the post-synaptic spikes are greater than membrane potential. The synapse can scale the pre-synaptic spikes according to synaptic strength / weight and transmit it to post-synaptic terminal.
[0057] FIG. 1A and 1B illustrates a typical biological neuron and a biological synapse respectively.
[0058] FIG. 1C illustrates an exemplary representation of a system level representation of a biological neuron, in accordance with an embodiment of the present disclosure.
[0059] FIG. 1D illustrates an exemplary representation of a system level representation of a biological neural network, in accordance with an embodiment of the present disclosure.
[0060] As illustrated, as illustrated in FIG. 1A and 1B, an average human brain has about 86 billion biological neurons (or nerve cells) and many more neuroglia (or glial cells) which serve to support and protect the neurons. Each neuron may be connected to up to 10,000 other neurons, passing signals to each other via as many as 1,000 trillion synaptic connections. Estimates of the human brain’s memory capacity vary wildly from 1 to 1,000 terabytes. A typical biological neuron 100 includes a soma (a cell body 102 which contains the cell nucleus 104), dendrites 108 (long, feathery filaments attached to the cell body 102 in a complex branching 140 “dendritic tree”) and a single axon 114 (a special, extra-long, branched cellular filament, which maybe thousands of times the length of the soma). Every neuron 100 maintains a voltage gradient across its membrane. This is due to metabolically-driven differences in ions of sodium, potassium, chloride and calcium within the cell, each of which has a different charge.
[0061] If the voltage changes significantly, an electrochemical pulse called an action potential (or nerve impulse) is generated. This electrical activity can be measured and displayed as a waveform called brain wave or brain rhythm. This pulse travels rapidly along the cell’s axon 114 and is transferred across a specialized connection known as a synapse 118 to a neighbouring neuron, which receives it through its dendrites. A synapse 118 is a complex membrane junction or gap (the actual gap, also known as the synaptic cleft, 108 is of the order of 20 nanometres, or 20 millionths of a millimetre) used to transmit signals between cells, and this transfer is therefore known as a synaptic connection. Although axon-dendrite synaptic connections are the norm, other variations (e.g. dendrite-dendrite, axon-axon, dendrite-axon) are also possible. A typical neuron fires 5 – 50 times every second.
[0062] As illustrated, in an embodiment, the functionality of biological neurons 100 and synapses 118 can be mimicked by using CMOS VLSI. A neuron 200 (also referred as a analog neurone 200, herein) can be designed by using an integrator 136 (also referred as one or more integrators 136, herein) and a comparator (also referred as one or more comparators, herein). Similar synapse 118 can be designed using a weighting function and multiplier block, where the weights 138 can be stored in an analog memory is available, the weight 138 can be directly replaced by the analog memory (also referred as non-volatile analog memory, herein), whereas the weighting parameter (also referred as synaptic weights, herein) is defined by the extent to which the analog memory is programmed. Once a single neuron 200 and required infrastructure for synaptic connection is ready, it can be used in any neuron model, as depicted in FIG. 1D.
[0063] FIG. 2A illustrates an exemplary representation of Schematic of TMDC based point TFET and FIG. 2B illustrates an exemplary representation of Schematic of TMDC based Line TFET, in accordance with an embodiment of the present disclosure.
[0064] As illustrated, in an embodiment, the proposed neuromorphic chip can include one or more analog neurons 200 further including one or more integrators 136 and one or more comparators. The one or more analogue neurons 200 can be interconnected using a plurality of wired synaptic connections, in a same way as biological neurons. One or more non-volatile analog memory can be configured with the plurality of wired synaptic connections to add weighting parameter. The one or more non-volatile analog memory can be configured to retain the added weighting parameter to facilitate quick training of the neuromorphic chip.
[0065] In an embodiment, the one or more non-volatile analog memory can include any or combination of a tunnel field-effect transistor (TFET) and a metal oxide semiconductor field effect transistor (MOSFET) and can be used in a signal path of the analog neurons 200. TFETs specially can offer sub-threshold region operation, which can significantly improve the power – performance trade-off. The weighing parameter 138 can be selected by any or the combination of programming of the one or more non-volatile analog memory, and an ON-state resistance of the one or more non-volatile analog memory in the signal path. The ON-state resistance can be a function of a gate to source voltage and a threshold voltage of the TFET and MOSFET. The ON-state resistance can be proportional to 1/(VGS-VT):
Where:
VGS = Gate to Source voltage, and
Vt = Threshold voltage
The analog neurons 200 can be developed using any or a combination of two-dimensional 2D material based CMOS or 2D material heterostructure based n/p-TEFTs. The 2D materials can be but not limited to grapheme, MoS2-xOx, and graphene.
[0066] As illustrated in FIG. 2A and FIG. 2B, the TFETs can include a source, a drain, and a gate. The channel can be made of transition metal dichalcogenide material.
[0067] FIG. 3A illustrates an exemplary representation of proposed analog memory 300, FIG. 3B illustrates an exemplary representation of programmed threshold voltage vs. back control gate voltage of the proposed analog memory 300, AND FIG. 3C illustrates an exemplary representation of cell or schematic view of proposed analog memory 300, in accordance with an embodiment of the present disclosure.
[0068] As illustrated, in an embodiment, analog neurons 200 mimicking brain like synapse operation (non-volatile, analog synapse) can be designed with the availability of an analog memory 300 (also referred as one or more non-volatile analog memory 300, herein). FIG. 3A illustrated a possible archetecture of the analog memory 300 can include a source 316, a drain 318, a front control gate 314 (also referred as a first gate 314, herein), and a back control gate 302 (also referred as a second gate 302, herein). The front control gate 314 and back control gate 302 can be placed in front of each other and normal to the source-drain current flow direction are used. Here the front control gate 314 can be encapsulated with graphene layers 310 and can be used for program and erase operation. The back control gate 302 can be used to control programed state of the analog memory 300. A channel of the analog memory 300 can be made from Transition Metal Dichalcogenide (TMD) or any other 2D material-based semiconductor. FIG. 3B depicts that the with the increase in back control gate voltage there is a linear increase in the programming voltage.
[0069] In an embodiment, the FIG. 3C depicts a schematic diagram of the proposed analog memory cell 300. The proposed solution with the use of analog memory 300, as explained above, can offer truly an analog and adaptive / re-configurable behaviour, which can behave exactly like biological brain. In this case, the analog memory 300 can be used in the signal path where the ON-state resistance, which can be proportional to 1/(VGS-VT), of the analog memory 300 is used a weighting parameter 138 (also referred as synaptic weight 138, herein). As the Vt can be tuned linearly as a function of program voltage for the proposed analog memory, the ON-resistance can be programmed in an adaptive fashion.
[0070] FIG. 4 illustrates a typical Neuromorphic chip architecture.
[0071] FIG. 5 illustrates an exemplary representation of proposed neuromorphic chip architecture, in accordance with an embodiment of the present disclosure.
[0072] FIG. 4 illustrates an analog memory integration in a typical Neuromorphic chip architecture 400 with i × j neurons and i × j × n synaptic connections. Where ‘i' represents the number of nodes in each layer and j represents the number of layers. An analog memory to mimic synaptic operation can be used in between each neural connection, and a back-propagation block can be used to drive the program and erase operation as well as controls the programming of synaptic weight in a controlled way. The architecture can include a back propagation or feedback block 402, an input block 404, an output block 406, and a control block 408 that can control programming and biasing of the memory 412.
[0073] FIG. 5 illustrates proposed neuromorphic chip architecture 500 to implement digit recognition system. The neuromorphic principle based digit recognition chip 500 is proposed as a vehicle to validate the feasibility of the proposed approach. The prpoposed architecture can include a communication interface 502, an interface controller 504, an input layer 506, and an output layer 514. The input layer along with a router 508, a decoder 510, an encoder 512, and memory 300 can be referred as a neuro-core. The proposed architecture 500 can include an array of neuro-cores. The memory can be referred as a combination of analog representation of the neurone 200.
[0074] The architecture 500 can be realized from Input layer 506 till output layer 514 over a flexible platform. The interfacing with the external world can be performed using the interface controller 504 and communication interface 502. The communication interface can be but not limited to a FPGA board. The communication interface 502 can communicate with the external world like sensors, which are the source of data for neuromorphic computation. Interface controller 504 can act like an interpreter between external world and Neuro-core. In configuration mode, the interface controller 504 can configure connectivity between neurons 200 and initialise various network, neuron 200 and synaptic parameters. In run mode, the interface controller 504 can receive data and can forward it to the input layer 506. The interface controller 504 can also allow user to read states of network and neuron parameters.
[0075] In an embodiment, the input layer 506 can receive data from the interface controller 504 and encodes it into a rate of spike and sends it to destination axon 114 which is also configured during the configuration mode. The neuro-cores can include an array of neurons 200 & synapses 118, which is integrated with blocks like router 508, spike decoder 510, spike encoder 512 and memory 300. Multiple neuro-cores can be tiled to form a Neural Processing Unit.
[0076] FIG. 6 illustrates an exemplary representation of block level architecture of neuro-core, in accordance with an embodiment of the present disclosure.
[0077] As illustrated, the neuro-core architecture can include a router 508, a spike decoder 510, a synaptic memory 300, an accumulator or integrator 138, and a spike encoder 512. The synaptic memory 300 and the accumulator or integrator 136 can form an array of integrate and fire neurones. The router 508 can enable formation of a 2D mesh of neuro-cores 600. In the 2D mesh, nodes can represent neuro-cores 600 and edges can be formed by connection of adjacent cores. Connection of a neuron X in core A to a neuron Y in acore B can be implemented by virtually sending a spike event through a network of routers. This 2D mesh network of neuro-cores 600 can enable realization of complex interconnected neural networks.
[0078] In an embodiment, the spike decoder 510 can convert the spike rate information into data required for computations (integrate and fire) inside the neuron 200, and can convert the data (neuron output) back to spike information. This can allows a shared axon architecture to reduce number of axon wires from N to log2(N), to transmit N spikes into N axons. The spike decoder 510 can enable connectivity from one neuron 100 in a core to any other neuron 200 in any other core.
[0079] FIG. 7A illustrates digital implementation of integrate and fire Neuron, FIG. 7B illustrates digital representation of synapse, and FIG.7C illustrates analog implementation of neuron and synapse, in accordance with an embodiment of the present disclosure.
[0080] As illustrated, the neuro-core 500 can include an array of neurons 200 and synapses 118. Neuron can integrate post-synaptic spikes 704 and can compare it with a threshold / membrane potential using a comparator 708. A spike 710 can be produced if the post-spike 704 is greater than membrane potential as illustrated on FIG. 7A. The synapse block 720 can scale pre-synaptic spikes according to synaptic strength/weight 138 and can transmit it to post-synaptic terminal. A simple digital implementation of synapse 118 is shown in FIG. 7B. A simple multiplexer 706 can work as synapse 118 as the input is a digital. Select lines of the multiplexer 706 can be spike, and one of the input to the multiplexer 706 can be weight 138 assigned to the synapse 118. An output of the multiplexer 706 can represent post synaptic signal/signal 704. As illustrated in FIG. 7C, the analog neuron 200 and synapse 118 can include an integrator 134 which can be referred as a combination of a capacitor 712 and a first operational amplifier 716 and a comparator 140. The integrator 138 and the comparator 140 (also referred as one or more comparators 140, herein) can be used for mimicking neuron operation. Whereas resistors R1, R2,.. Rn can represent programable weights 138, which mimics the synapse operation. The synaptic weights 138 can be implemented using the analog memory 300. The synaptic weights 138 can be calculated in a simulation environment, and can then be loaded into the hardware memory, which can be transferred to neuro-core memory at the time of system initialization.
[0081] FIG. 8 illustrates an exemplary representation of a summary of the flow and methodology to realise the proposed flexible, analogue, adaptive and non-volatile neuromorphic chip technology platform, in accordance with an embodiment of the present disclosure.
[0082] As illustrate, the method involves growth of 2D materials for flexible technology, component (FETs, memory, passives and interconnect) development, library/PDK development. Component development deals with development and optimization of various unit processes involved, including minimizing device / process variability and improving device reliability. PDK development will deal with device as well as standard cell library characterization.
[0083] In an embodiment, once the technology platform, component library and required PDK are ready, they can be directly used by circuit designers to develop various modules of the neuromorphic chip such as, but not limited to neuron cell, axon, dendrite, synapse weight, ion integrator, spike router, memory block, etc. once the modules, which are the building blocks of the neuromorphic chip, are ready, they can be integrated into the design library.
[0084] In another embodiment, a neuromorphic chip is then designed by integrating the library components, as basic building blocks, as per a requirement. Applicationn specific architectures can then result into unique neuromorphic compute functionalities. After integration of individual modules as per the architecture requirement, chip can be fabricated and passivated with polymer material before it is taken out for testing and qualification. Thus, the present disclosure provides a methodology for a flexible, analogue, adaptive and non-volatile neuromorphic chip and technology platform, where the chip can be realized on a flexible substrate. Graphene/TMD based analogue non-volatile memory is used to realize non-volatile synapse and 2D materials such as TMD based Tunnel FETs can be used for analogue neuron architecture. High performance 2D materials based transistors are used for various neural network operations and the different components are integrated to realise a back-propagation based adaptive architecture.
[0085] The present invention helps overcome the problems of existing prior arts including but not limited to missing analog storage capability, missing adaptive and self-learning capability, not being practical for implementation of complex neural networks, missing brain like up-scaling in 3rd dimension, missing brain like flexible technology platforms, requirement of large silicon real estate to mimic a brain equivalent capability, interconnection of synapse becoming a serious concern to a brain like scale, stability, yield, and reliability at a brain like scale.
[0086] The present invention provides/facilitates for a technology platform that is atomically thin, flexible, scalable to 3rd dimension, and offers low power solution with a non-volatile, adaptive and analog synaptic / memory cell, can address most of the shortcoming listed above. An exemplary key aspect to neural processing is the synaptic connections (synapse) that store and adjust analog weights during the training/learning process of a neuron. To enable this, a technology that is flexible, atomically thin and 3D in nature is needed that allows scale-up to a computational level of brain without significantly increasing chip size. Furthermore, the requirement to mimic brain’s function, besides information of brain’s complex neural network architecture and required nature of technology, is an analog storage capability with a storage capacity up to 1000 terabytes. This makes it fundamentally analog in nature.
[0087] The proposed invention is truly analog in nature, very much like the way brain works. The existing solutions intrinsically use a digital technology to mimic neuron behaviour, which adds significant overhead in terms of power and chip area and limits the upward scaling to realize solutions of realistic size or scale. The proposed technology is flexible in nature, similar to the way neurons or biological systems look like, which allows expansion in 3rd dimension and a biological organ like flexible form-factor. The present invention is almost mass less, which allows upward scalability. For example, let’s say a human brain like capability may require ~1 trillion synaptic connections across 40B neurons. Using proposed technology, such a massive network of neurons – keeping a conservative estimate, will not be bigger than 7cm × 7cm × 7cm. The same solution however using existing state of the art technology and approach (IBM’s TrueNorth chip) would be atleast 70m x 70m x 7m, which is almost impossible to design, realize and manufacture. The present invention is adaptive and non-volatile, wherein existing solutions, example the most advance by IBM (TrueNorth chip), are volatile in nature. It means one needs to train the neural network every time or store the synaptic weights on a digital flash memory. The digital to analog (and vice versa) conversion further adds design and Si real state overhead. However, the proposed solution offers truly an analog and adaptive / re-configurable nature, which would behave exactly like a human brain. The present invention is based on ultra-low power requirement wherein existing state-of-the-art solution would require 100s of kW electrical power for a computational capability equivalent to 1 trillion synaptic connections. This makes it impractical for mobile applications. However, due to true analog nature of proposed solution, it is expected to consume few 10s of watts of power.
[0088] In an aspect, the present invention provides a flexible, analog, adaptive and non-volatile neuromorphic chip and technology platform wherein the chip is realized on flexible substrate, and wherein Graphene/TMD based analog non-volatile memory is used to realize non-volatile synapse. The proposed chip also uses TMD or 2-Dimentional materials (eg. WS2/MoS2/WSe2) based Tunnel FETs and MOSFET for analog neuron architecture, and high performance transistors are realized using 2-Dimentional materials (eg. WS2/MoS2/WSe2), used for various neural network operation. All these elements/components are integrated to realize a back-propagation based adaptive architecture Neuromorphic, wherein analog non-volatile memory consists of TMD or similar 2D material-based semiconductor (eg. WS2/MoS2/WSe2) as a channel material, Graphene or similar material as floating gate which stores program charge, and two gates placed parallel to each other on the opposite sides of channel, and normal to the source-drain current flow direction, where one of the gate with encapsulated graphene layers (to form floating gate) is used for program and erase operation, whereas other gate, which has no floating gate is used to control programmed state of analog memory.
[0089] In another aspect, the analog memory used in the synaptic path are configured such that threshold voltages of individual memory cells are tuned individually using a back-propagation block which enables online training capability. Furthermore, a set of layers of neural networks can be realized over unique/different flexible substrates, while using the proposed platform. All these substrates can then be integrated vertically by using vertical interconnects to complete the neural network.
[0090] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive patent matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “includes” and “including” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practised with modification within the spirit and scope of the appended claims.
[0091] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0092] The proposed invention provides a truly analog neuromorphic chip that can be with reduced size and hardware.
[0093] The proposed invention provides a flexible neuromorphic chip that can allow expansion in 3rd dimension and a biological organ like flexible form-factor.
[0094] The proposed invention provides a truly analog, flexible, and adaptive neuromorphic chip which consumes less power.
,CLAIMS:1. A neuromorphic chip (500), the neuromorphic chip (500) comprising:
one or more analog neurons (200) comprising one or more integrators (136) and one or more comparators (140), the one or more analogue neurons (200) interconnected using a plurality of wired synaptic connections, in a same way as biological neurons (100); and
one or more non-volatile analog memory (300) configured with the plurality of wired synaptic connections to add weighting parameter (138), wherein the one or more non-volatile analog memory (300) is configured to retain the added weighting parameter to facilitate quick training of the neuromorphic chip (500).
2. The neuromorphic chip (500) as claimed in claim 1, wherein the one for more non-volatile analog memory (300) comprises any or combination of a tunnel field-effect transistor (TFET) and a metal oxide semiconductor field effect transistor (MOSFET).
3. The neuromorphic chip (500) as claimed in claim 1, wherein the one or more non-volatile analog memory (500) is used in a signal path of the analog neurons (200).
4. The neuromorphic chip (500) as claimed in claim 1, wherein the weighing parameter (138) is selected by any or the combination of programming of the one or more non-volatile analog memory (300), and an ON-state resistance of the one or more non-volatile analog memory (300) in the signal path.
5. The neuromorphic chip as claimed in claim 4, wherein the ON-state resistance is a function of a gate to source voltage and a threshold voltage of the one or more non-volatile analog memory (300).
6. The neuromorphic chip as claimed in claim 1, wherein the one or more non-volatile analog memory (300) comprises:
a first gate (314) covered with grapheme (310), and configured program and erase the one or more non-volatile analog memory (300), and
a second gate (302) configured to control program state of the one or more non-volatile analog memory (300).
7. The neuromorphic chip (500) as claimed in claim 5, wherein gates of the one or more non-volatile analog memory (300) are kept opposite to each other and normal to the source-drain current flow direction are used.
8. The neuromorphic chip (500) as claimed in claim 6, wherein channel (306) of the one or more non-volatile analog memory (300) comprises material form a group of Transition Metal Dichalcogenide (TMD) semiconductors.
9. The neuromorphic chip (500) as claimed in claim 1, wherein at least one of said one or more analog neurons is developed using any or a combination of 2D material based CMOS or 2D material heterostructure based n/p-TEFTs.
10. The neuromorphic chip (500) as claimed in claim 1, wherein said neuromorphic chip (500) is designed by integrating any or a combination of one or more neuron cell modules, axon modules, dendrite modules, synapse weight modules, ion integrator module, spike router module, and memory block module, at least one of these modules being designed and fabricated using said 2D material.
11. A neuromorphic chip (500) as claimed in of claim 1, wherein the neuromorphic chip (500) comprising:
an input layer (506) operatively coupled to receive data from an interface controller (504); and
a neutral processing unit configured to receive the data from the input layer (506) and process the received data, the neutral processing unit comprising one or more neuro-cores (600), each of the one or more neuro-cores (600) comprising an array of neurons (200) and synapses (118), the array being integrated with any or a combination of a router (508), spike decoder (510), spike encoder (512), and memory (300).
12. The neuromorphic chip (500) as claimed in claim 11, wherein the router (508) enables formation of a 2D mesh of at least a part of the one or more neuro-cores (600), wherein nodes are the neuro-cores (500) and edges are formed by connection of adjacent neuro-cores (600), wherein connection of a first neuron in a first neuro-core to a second neuron in a second neuro-core is implemented by virtually sending a spike event through the network of routers.
13. The neuromorphic chip (500) as claimed in claim 11, wherein the spike decoder (510) converts spike rate information into data required for computations inside the neuron (200), and wherein the spike encoder (510) converts the data back to spike information.
14. The neuromorphic chip (500) as claimed in claim 11, wherein the neuron integrates post-synaptic spikes (704), and compares the integrated post-synaptic spikes with a threshold / membrane potential (Vmp) to produce a spike (710) if the post-synaptic spikes (704) are greater than membrane potential, and wherein the synapse scales the pre-synaptic spikes according to synaptic strength / weight and transmit it to post-synaptic terminal.