TITLE "A FPGA AND DSP BASED CONTROL BOARD (FDCB) FOR A DIGITAL CONTROLLER"
FIELD OF INVENTION
The invention relates to a FPGA and DSP based control board (FDCB) for a digital
controller and to the field of electronic and digital control system. The device is
in the form of an electronics and digital control board (FDCB) based on FPGA
(field programmable gate arrays) and DSP (Digital signal processor) with a
printed circuit board (PCB) for the application of digital control electronics, in
particular.
BACKGROUND QF THP jNVENTIQN QF PRIQR ART
A digital controller generally requires few analog signal input for monitoring and
measuring physical parameters like speed, acceleration, displacement, voltage,
current, temperature etc. Few digital input in form of ON state (Digital high =1)
and off state (digital low = 0) to define state of condition of system.
Similarly analog output is generated by the digital controller as per the
requirement of user/system under control. Digital outputs (as state 1 = high or 0
= low) are also required to be generated by a digital controller to satisfy the
logics of the system like START (Say, logic high = 1), STOP (say, logic Low = 0).
Controlled pulses (periodic high = some definite voltage and low = less than
some predefined voltage) also required from a digital controller to switch on and

switch off a semiconductor switch which can handle several amperes. A
semiconductor switch works like a physical switch when it's gate (control input)
is energized with electrical signal (voltage/current). It means current through a
semiconductor switch is given way and blocked by controlling it's gate i.e
controlled input. Thus a semiconductor switch can be controlled by feeding the
periodic pulses in the control input (gate) of the switch.
Therefore, there are requirement of controlled pulses like pulse width modulation
(PWM) for controlling the semiconductor switches. Pulse Width Modulation is a
technique where the periodicity of pulse cycle is fixed but the duration of the "on
time" and "off time" is varied depending on pre defined condition.
Communication ports are required in a digital controller so that a controller can
communicate with other subsystem or a supervisory controller for various status
and parameter sharing. And this is done with predefined pattern with checking
the authenticity of data. There are several types of communication protocol exist
like RS 232, RS 485, control area network (CAN) bus etc.
Control power supply is required to energies the semiconductor devices used the
electronics control card. Depending on the requirement of the control voltage
level by the semiconductor devices, multiple power sources are required in the
control card.
A microcontroller based card, as in the prior art type PPB511B01, based on a
microcontroller (80C196KC) and ASIC's (Application specific IC) named PCW3
and BAP2/3 has deficiency of having no DEAD BAND Control for pulse

interlocking (complementary). The Card PPB511B01 has only 2 nos PWM
available output ports. Besides that there is limitation of having communication
Protocol, for example only 1 nos. RS 232 and MICAS based communication
protocol exist in PPN511 card. The above limitation of said controller restricts its
digital application.
OBJECT OF INVENTION
To overcome the drawbacks of the prior art, the innovative remedial actions are
under-taken and as such objects of the invention are summarized below:
The primary object is to propose an FPGA and DSP based control board (FDCB)
which can be used for digital control application. The FPGA is used for I/O
expansion, memory interface, communication and interfacing with DSP.
Another object is to propose an FPGA and DSP based control board (FDCB) with
a 32 bit DSP type TMS320F2812 and two nos. FPGA Type EP2C5Q208 and with
two RS232 port and with one no RS485 port and a CAN bus Port.
Further object is to propose an FPGA and DSP based control board (FDCB) which
can be implemented in more complex digital system, which require maximum -

- 24 PWM outputs
with DEAD BAND controller
- 24 digital output (Open Collector)
- 24 Digital input
- 16 analog input (12 bit resolution)
- 8 analog input (10 bit resolution)
Still further object is to propose an FPGA and DSP based control board (FDCB)
developed on a multilayer Printed Circuit Board named as PCB-FDCB-06C-001.
SUMMARY OF THE INVENTION
The control FDCB designed with a PCB named PCB - FDCB - 06C - 001 and
using FPGA and DSP in the present invention. The PCB is designed for a digital
controller.
A clear picture of development over the prior art, is depicted in a comparison
table, shown as under.

A FPGA and DSP based control board (FDCB) is designed on a printed circuit
board named PCB - FDCB - 06C - 001.
The Electronics control board with PCB named PCB - FDCB - 06C - 001 is
developed based on a DSP (as for example, TMS320F2812 DSP of make Texas
Instruments) and two nos. FPGA as for example, EP2C5Q208C Cyclone II FPGA
of make Altera).
This is a Electronic hardware platform. Using the electronic control board (FDBC),
application in field of digital control electronics can be developed by suitably
programming the DSP and FPGA's.
For DSP programming JTAG port is provided in connector for programming and
real time simulation with the help of programming software DSP as for example,
Texas Instrument programming software, "CODE COMPOSURE - STDIO
(CCStudio version 3.1 or higher").
The FPGA and DSP based control board is developed based on latest available
technology in form of very large scale Integrated semiconductor chip. The PCB
named PCB-FDCB-06C-001 is designed to suit such high speed application and
increased nos. of analog and digital I/o's and communication and programming
headers are made available.

The electronic control board (FDCB) contains a Digital Signal processor (as for
example, TT's Texas Instrument) and FPGA's (as for example, Altera Cyclone II)
which provides around 5000 Logic Element and 119, 808 Memory bits. Board
provides flexibility to implement DSP algorithms in processor or FPGA's, for
example TI's Processor or Altera FPGA's. Board contains industrial
interconnection, Memory Sub system, Multiple clock domains for system, JTAG
connection, support for DSP real time emulation, user define input/output. There
are 24 PWM channels for implementing motor control application, also this board
contain 10 bit, 8 channels ADC and DCA with fast 80 ns conversion rate. Board
provides two RS - 232, one RS - 485, one CAN, McBSP port for communication
with external media.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Fig. 1 shows the placement of the components and location of the connectors
headers and their device reference on the top side of the board (1).
Fig. 2 shows placement of the components on the bottom side of the board (1).
Fig. 3 block shows diagram and signal flow of electronic printed circuit board (1)
i.e., : PCB - FDCB - 06C - 001, through the inter connectivity between input
outputs (I/OS), DSP, FPGA1 and FPGA2 and other control modules of the board.
Fig. 4 shows the 16 channel Analago inputs to DSP Ports.

Fig. 5 shows Analog Processing through ADC (U33) and FPGA2.
Fig. 6 shows DAC output through FPGA1
Fig. 7 shows digital inputs.
Fig. 8 shows PWM block with DSP
Fig. 9 PWM block with FPGA2
Fig. 10 shows RS 232 and can bus communication port with DSP.
Fig. 11 shows RS 485 communication protocol with FPGA
Fig. 12 shows DSP JTAG header.
Fig. 13 shows DSP external interface.
DETAIL DESCRIPTION AND INTER CONNECTIVITY OF COMPONENTS
OF THE INVENTION
The invention will now be described with help of the accompanying drawings
which depicts an exemplary embodiments of the invention. However, there can

be several other embodiments, all of which are deemed covered by the
description.
The electronic card PCB-FDCB-06C-01 is designed for digital control application.
The card is having 32 analog input channels, 8 analog output channel, 24 digital
output, 24 digital input channels, 24 PWM output channel, 2 nos RS-232, 1 nos
RS-485,1 no. CAN Bus communication port.
Fig. 3 shows with the help of block diagram the interconnectivity between input
outputs (I/O's), DSP, FPGA1 and FPGA2 and other control modules of the board.
Details of the interconnection different control modules of the card is
described below:
The following are the features of FPGA and DSP control board;
A. ANALOG INPUT CHANNELS: 24 CHANNELS
Analog input channels are for processing the analog signals and suitable
conversion to equivalent digital signal.
The 16 nos of analog signals designeated as adc_in_ch0 to adc_in_chl5
are filtered with a RC network and a clamping circuit pulled up with
shotkey diode (LL103A) to 3.3volt and feed to DSP ADC inputs designated
as dsp_adc_ch0 to dsp_adc_chl5. This input analog signal level is
restricted within 0 to 3.3Volts (VCC_3.3_DSP_A).
GND_DSP_A is Ground plane which is at 0 potential.

Analog input signals adc_in_ch0 to adc_in_ch15 is electrically connected
to the 32X3 euro connector named FDX1. After processing through
protection and filter circuit the analog inputs are connected with DSP
analog input ports ADCINAO ....ADCINA15 as shown in Fig. 4
16_ch_Analago input to DSP Ports
The pin nos. of the connector FDX1 with the analog signals are as
following:

Another 8 nos analog channels are also available in the card which can
handle the signals from OV to 5V level. The 8 nos of analog signals
designated as adc_in_chl6 to adc_in_ch23 are filtered with a RC network

and a clamping circuit pulled up with shotkey diode (LL103A) to 5.0volt
and feed to a 10 bit ADC IC inputs designated as fpga2_adc_ch0 to
fpga2_adc_ch7. This input analog signal level is restricted within 0 to
5.0Volts (VCC_5_ADC_A).
GND_ADC_A is ground plane which is at 0 potential as shown in Fig. 5
Analog input signals adc_in_chl6 to adc_in_ch23 is electrically connected
to the 8X2 berg stick connector (Female) named FDX3. After processing
through above ckt the same are connected with an analog input ports of
DC ic TLV1578(U33) for further processing in FPGA2. FDX3 Header (F) Pin
Discretion.


B. ANALOG OUTPUT (DAC), 8 CHANNELS:
Analog outputs are generated by a Digital to analog converter,
AD7809BST (U34) with lObit data from DAC control block of FPGAL
These are routed through a voltage follower circuit designed with
operational amplifier (OPAMP, U36 and U36A) and resistors and finally are
connected with Header FDX1.
The 8 nos of analog signals from a DAC designated as dac_out_ch0 to
dac_out_ch7 are processed through buffer circuits as shown in example.
Output of the buffer circuit designated b_dac_out_ch0 to b_dac_ch7 are
electrically connected to the connector FDX1 as shown in Fig 6.
DAC OUT PUT THROUGH FPGA1
The pin nos. of the connector, FDX1 with the analog signals (DAC) are as
following:


C. Digital outputs
There are 24 digital output on FPGA and DSP control Board. These digital
outputs are assigned in pins of the connector FDX1. All the digital out puts
are often collector type, suitable pull-up resistor with limiting current 10
milli amp with max pull-up voltage 24V can be used simultaneously in all
the digital outputs. The digital outputs are designated as doO to do23. The
pin nos. of the connector, FDX1 with the digital out puts are as following:

All the digital outputs are programmable by both the DSP and FPGA'S and
all the 24 channels are routed through FPGA2, levels shifters (U24, U25
and U24), driver Ic's (U29, U30, U31 and U32).

D. DIGITAL INPUTS (24 CHANNELS)
There are 24 digital input on FPGA and DSP Development Card. All digital
input support +5V TTL standard logic. The digital inputs are designated as
dil to di23 and assigned in pins of the connector FDX1. The pin nos. of the
connector, FDX1 with the digital inputs are as following:

Digital inputs
All the digital inputs are pulled up with resistors to 5V in the control board
and routed to FPGA2(U8) through 3 nos (U21, U22 and U23) 10 bit bus FET
switching level shifting IC's as shown in the block diagram, Fig. 7.

E. PWM (Pulse Width Modulation) Channels
FPGA and DSP Development Card provides 12 PWM channels which is
connected to TI DSP's PWM module and another 12 PWM channels which
is connected to FPGA2 (as shown in Fig 8 and 9). All 24 PWM channels are
open collector output.
PWM outputs are configure as pair. That means there two PWM pulses
shall be generated by the controller simultaneously but both the pulses
are complementary to each other. Thus, Channel designated as pwmO is
complementary to pwm_n0, and similarly pwm2 is complementary to
pwm_n2 and so on.
12 PWM out puts (6 pairs) are being generated by the DSP chip being
used in the card and another 12 PWM puts (6 pairs) are being generated
through FPGA1 chip. Out of total 24 PWM output (12 pairs), 22 channels
(11 pairs) from pair pwm0 + pwm_n0 to pwm10 + pwm_n10 are
assigned in 20x2 connector, FDX2.

Complementary PWM out put are generated in DSP and FPGA based on
software logic depending on projects. The levels of the PWM outputs are
shifted to 5 vols with 10 bit FET switching level shifter IC's U16, U17 (for
DSP PWM) and U26 and U23 (for FPGA PWM). After level shifting the
PWM signals are fed to base of high frequency transistors (Q2 to Q13 for
DSP PWM) and Q14 to Q25 for FPGA PWM block) thorough resistor divider
circuit. The final outputs are connected to Headers as per above
mentioned Table.
F. COMMUNICATION
There are total 4 nos. communication ports are made available in our
present development board.
RS 232 and CAN BUS COMMUNICATION PORT WITH DSP AS
SHOWN IN FIG 10.
• CAN (CONTROL AREA NETWORK) PORT:
CONS is CAN connector, CAN is different serial bus line which is originally
designed by connecting electronic control unit. Tl DSP's eCAN module is fully
compliant with CAN protocol, version 2.0B
CAN transmit and receive pin are converted to differential line by TI's CAN
Half Duplex Transceiver SN65HVD235D (U39).

The Table show the connector pin out for CAN

• SERIAL PORTS CONNECTORS:
CON2, CON3, CON4 are standard DB9 connectors (9 pin D-type connector),
CON2 and CON3 connectors are RS-232 standard and CON4 are RS485
standard.
Two nos. RS 232 communication ports are realized with DSP RS-232
controller and same are connected to connectors CON2 and CON3 through a
dual RS232 Transreceiver MAX3232ID(U37).
The Table shows the pin out of CON2 connector


The Table shows the pin out of CON3 connector.

one no. RS 485 communication port is realized with FPGA2 and same is
connected to connectors CON4 through a RS485 Transreceiver SN75176BD
(U38) as shown in Fig 11.
The Table shows the pin out of CON4 connector.


G. GENERAL CONNECTORS/HEADERS
• Active Serial (AS) and JTAG Header (J6,37,38,39)
On FPGA and DSP Development Card AS configuration scheme is combined
with JTAG based configuration. This set up uses two 10-pin download cable
headers on the board for each FPGA. The first header (37 for FPGA1 and
39 for FPGA2) programs the serial configuration device in-system via the AS
programming interface, and the second header (J6 for FPGA1 and J8 for
FPGA2) configures the Cyclone II FPGA directly via the JTAG interface.
• JTAG Emulator Header for DSP (J5)
DSP.JTAG HEADER AS SHOWN IN FIG 12
FPGA and DSP Development Board supplied with 14-Pin header for JTAG
Emulation interface to communicate Texas Instruments DSPs TMS320F2812
DSP support real-time mode of operation whereby the contents of memory,
peripheral and register locations can be modified while the processor is
running and executing code and servicing interrupts. The user can also signal
step through non-time critical code while enabling time critical interrupts to
be serviced without interference.
H. PERIPHERAL CONTROL BLOCK:

DSP EXTERNAL INTERFACE AS SHOWN IN FIG 13
In this board, there are three main controllers which are DSP, FPGA1 and
FPGA2. In the invention the DSP is being used as master controller, FPGA
being used for memory mapping and Peripheral controller and FPGA2 is
mainly used for I/O processing as well as for expansion of I/O's and control
logic implementation.
For any application the DSP is required to be communicated with other two
controllers. DSP (TMS320F2812, U5) has 19 bit external interface (XINTF)
address bus (XA[0] to XA[18]) and 16 bit external interface data bus (XD[0]
to XD[15]. Three chip select lines, XZCSOAND1_n, XZCS2_n and
XZCS6AND7_n.
The chip-select lines are mapped to five external zones, Zones 0, 1, 6, and 7.
Zones 0 and 1 share a single chip-select; Zones 6 and 7 also share a single
chip-select. Each of the five zones can be programmed with a different
number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The
programmable wait-state, chip-select and programmable strobe timing
enables glue less interface to external memories and peripheral.

I. CONTROL POWER SUPPLY
This section describes information about the power supply, power
regulator and power supply connector on FPGA and DSP Development
Card. To energies the electronic card control voltage power supply to be
feed to the card, this supply then distributed throughout the card at
different levels as per specified requirement of semiconductor chips in the
card.
The control voltage (DC) supplies +1.2V, +1.8V, +3.3V, +5V, +15V and -
15V with respect to a common ground (GND) are required in the card. Out
of 6 level of power supplies, 3 supplies, +5V, +15V and -15V are fed from
external source and rest 3 levels (1.2V, 1.8V, 3.3V) are generated in the
card. Therefore, external power supply through assigned connector pins,
either in FDX1 or JP7 to be fed to energize the board.


Once all power supplies are set, the card is ready to perform. Following
different voltage supply are used on FDDC.
• +3.3v for cyclone II Device 1.0 Standard and DSP I/O Voltage
• +1.8 V DSP Core Voltage
• +1.2 V Cyclone II Device Core Supply Voltage
• +5V for ADC, DAC and Digital input and output
• +15V and -15V for Analog signal processing circuit
J. USER INTERFACE
• LED(Light emitting diodes)
LED1 is power supply indication. LED2 and LED3 is indication of FPGA1 and
FPGA2 configuration done respectively. These two LED'Ss are not used as user
define LEDS. Table shows the pin mapping of user LED to FPGA and DSPLED4,
LED5, LED6, LED7 are individual LED which are connected to DSP's (as for
example, TI's TMS320F2812) general purpose I/O with current limiting register.
LED8 and LED9 are connected to FPGA1 and FPGA2 (as for example, Altera's
Cyclone II Device) respectively.


• Push Button Switch
Swl is momentary contact push button switch which is connected to Altera's
Cyclone II FPGA1. This switch is connected to FPGA1 with pull-up register.

The Pin out of push button switch

DESCRIPTION OF THE COMPONENTS OF FDCB CARP
The major components on the FDCB board and the related interfaces, are
annexed in Table 1.
The electronic control board (1) with PCB (printed circuit board, PCB-FDCB-06C-
001 and with PCB details as below:
o 6 layer PCB
■ Layerl: Top signal layer
■ Layer2:Ground (GND) plane layer
■ Layer3: Power plane layer
■ Layer4: Ground plane layer
■ Layers: Power plane layer
■ Layer6: Power plane layer

o Overall thickness of the bare PCB is 1.6mm
o The PCB dimensions: 167mm (long) X 145 mm(width) X 1.6mm(thick)
o Mounting holes (4 mm dia) are marked as "a" in the drawing of the
bottom view (Fig 2)
o Placement of the components on the top side of the card are shown in the
TOP View (Fig 1)
o Placement of the components on the bottom side of the card are shown in
the Bottom View (Fig 2)
o Location of the connectors, headers and their device reference are shown
in the TOP View (Fig 1).

WE CLAIM
1. An electronic printed circuit board (PCB) based on field programmable
gate arrays (FPGA) and digital signal processor (DSP) for a digital
controller, comprising:
- a pair of FPGAs (U7, U8); and
- a DSP (U5)
wherein said FPGAs (U7, U8) are provided with I/O expansion ports,
application software logic implementation and memory interface for
communication with the DSP for status and parameter sharing with
various subsystems of an digital electronic controller;
and
wherein said I/O ports comprise 24 PWM outputs with dead band
controller, 24 digital inputs, 16 analog inputs of 12 bit resolution and 8
analog input of 10 bit resolution for use with subsystems of complex
digital electronic controller.
2. The controller as claimed in claim 1, wherein said 24 PWM outputs
comprising;

- 12 nos. PWM outputs, generated through DSP, and
- 12 nos. PWM outputs, generated through FPGA.
3. The controller as claimed in claim 1, wherein the PCB (1) (Printed circuit
board) has at least 6 layers comprising;
- top signal layer,
- ground (GND) plane layer,
- power plane layer,
- ground plane layer,
- power plane layer,
- bottom signal layer,
the layers being arranged in above order.
4. The controller as claimed in claim 1, wherein said DSP (U5) being
provided as a master controller, is connected to the system interfacing
with PFGAs (U7 and U8) and other subsystems like 12 CRTC (Serial Access
Time Keeper) (U12), memory subsystem comprising;

- SRAM (Static random access memory) (U12),
- 12 CEEPROM (Electrical erasable programmable read only memory)
- Flash memory (U11), and
Connected protocol RS-232, RS-485, CAN bus, MCBS etc. for
communication with external media.
5. The controller as claimed in claim 1, wherein said FPGAs (U7 and Us)
being controllers, are interconnected mutually and with DAC (U34) and
ADC (U33) respectively and to the DSP master controller, (U5) through
other components eg. SRAM (U12), flash memory (Ull), 12 CEEPROM
(U13) and 12 CRTC (U15), the FPGAs being provided for memory mapping
and peripheral controller and FPGA2 (U8) in particular for I/O processing
as well as expansion of I/O's and control logic implementation.
6. The controller as claimed in claim 1, is provided with 10 bit, 8 channel
ADC (U33) and DAC (U34) with the fast 80 ns conversion rate.
7. The controller as claimed in claim 1, is provided with 24 PWM channels for
implementing motor control application.
8. The controller as clamed in claim 1, is provided with TTAG (joint test
action group) port in connector for programming and real time simulation
of DSP.

9. The controller as claimed in claim 1, is provided with chip manufactured
with very large scale integrated semiconductor technology.
lO.The controller as clamed in claim 1, wherein said connectors, jumpers and
headers are provided for connectivity, compatible with communication
protocols RS 232, RS 485, CAN bus and MC BS for communication to
external media.
11.The controller as claimed in claim 3, wherein the dimensions of said
PCB(l) are 167 mm (long) x 145 mm (width) x 1.6 mm (thick).
12.The controller as claimed in claim 11, wherein said PCB(l) is provided
with a plurality of mounting holes (A) preferably 4 nos. of diameters, 4
mm.

An electronic printed circuit board (PCB) based on field programmable gate
arrays (FPGA) and digital signal processor (DSP) for a digital controller,
comprising a pair of FPGAs (U7, U8); and a DSP (U5) wherein said FPGAs (U7,
U8) are provided with I/O expansion ports, application software logic
implementation and memory interface for communication with the DSP for status
and parameter sharing with various subsystems of an digital electronic controller;
and wherein said I/O ports comprise 24 PWM outputs with dead band controller,
24 digital inputs, 16 analog inputs of 12 bit resolution and 8 analog input of 10
bit resolution for use with subsystems of complex digital electronic controller.