FIELD OF INVENTION:
The present invention relates to a FPGA based single phase high frequency inverter. The present invention provides a single chip solution for implementation of various complex digital control functions in hardware.
PRIOR ART
FPGA are semiconductor devices consisting of programmable logic components which can be configured & re-programmed to perform wide range of functionalities of digital circuits. A computational architecture can be implemented inside the FPGA by interconnection of the logic blocks using programmable interconnect resources. The complexity of these digital circuits varies from simple logic gates to complex combinational & sequential circuits.
The ability of re-programming the FPGA allows a user to not only design customized architectures but also gives access to more complex integrated circuit designs without getting involved in high engineering & development costs associated with ASIC development. It also provides the scope for improvement or any modifications that are required after the completion of the design.
Field programmable gate arrays (FPGA) is making considerable inroads into the digital signal processing marketplace. They are increasingly growing because of the shorter development time involved in providing a complete digital control solution which in turns leads to faster time-to-market.
Prior-art modular formats have been defined around the requirements of conventional microprocessors and digital signal processors. The DSP/microcontrollers are based on architectures having limited functionality and fixed peripheral set. The sequential execution of the code is another major drawback in such devices which leads to time sharing of the peripherals & other resources, thus resulting in considerable drop of performance. With FPGA there is no such fixed architecture present instead customized & concurrent architectures are implemented in order to achieve high degree of parallelism. Algorithms are implemented directly in hardware using these reconfigurable logic gates. This not only enhances the timing & performance but also eradicates any architectural compromises present in conventional microcontroller or DSP based systems.
FPGA also provides the advantage of future upgradation as per the dynamic needs of the user. New peripherals can be implemented inside the FPGA to meet new standards and protocols. So in this backdrop DSP/microcontroller based systems becomes obsolete as they fail to match up the dynamic needs & changing standards.
Reference to be made to a publication by Yogesh Aggarwal, Electronics For You, August 2006 which discloses FPGA design of a controller for three-phase inverters. It is a universal designed controller for three-phase inverters. The chip is designed in very high-speed integrated hardware description language (VHDL) and implemented on a field-programmable gate array (FPGA).
Reference may be made to a publication by M. N. Md Isa et.al, American Journal of Applied Sciences, 2007. This discloses FPGA based SPWM bridge inverter. This explains methodology to generate sinusoidal pulse width modulation (SPWM) signal using FPGA

technology with number of switching pulses 38, switching frequency 2 KHz and switching time 500 us.
Further, reference may be made to a publication by S. Mekhilef, Engineering e-Transaction, December 2006, disclosing Xilinx FPGA based multilevel PWM single phase inverter. A Xilinx FPGA based multilevel PWM single-phase inverter was constructed by adding bidirectional switches to the conventional bridge topology. The inverter can produce three and five different output voltage levels across the load.
Yet further, reference may be made to a publication by Kharrat M. W et.al, directing to FPGA based-IC design for inverter with vector modulation technique. This paper presents an application of a xilinx FPGA device, in the CX4000 family, producing Pulse Width Modulation (PWM) signals with the vector modulation technique for an IGBT inverter.
Reference may be made to a publication by Eftichios Koutroulis et.al, Journal of Systems Architecture June 2006 relating to high frequency pulse width modulation implementation using FPGA and CPLD ICs. This paper explains the development of high-frequency PWM generator architecture for power converter control using FPGA and CPLD ICs. The resulting PWM frequency depends on the target FPGA or CPLD device speedgrade and the duty cycle resolution requirements. The post-layout timing simulation results are presented, showing that PWM frequencies up to 3.985 MHz can be produced with a duty cycle resolution of 1.56%.
Reference to be made to a publication by Yokoyama T et.al, The 29th Annual Conference of the IEEE, 2003 which discloses an instantaneous dead beat control for PWM inverter using FPGA based hardware controller. This article explains a new approach for real time digital feedback control of PWM inverter, in which an ideal instantaneous deadbeat control is realized without any sampling compensation method using FPGA based hardware controller.
Reference to be made to a publication by Lentijo, S, Power Electronics Specialists Conference, June 2004 which discloses FPGA based sliding mode control for high frequency power converters. This paper explains the use of high switching speed power switches. This requires additional efforts in control development.
US patent no 7,274,243 is adaptive gate drive for switching devices of inverter. This inverter includes control circuitry having a field programmable gate array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a trench gate insulated gate bipolar transistor (IGBT device).
US patent no 6,995,548 is asymmetrical multiphase DC-to-DC power converter. There is a multiphase DC-DC converter architecture, in which different channels have different operational performance parameters. These different parameters are selected so as to enable the converter to achieve an extended range of high efficiency
US patent no's 7126409 and 6838925 are three level inverter. This invention relates to a high efficiency three-level inverter apparatus containing both bipolar and field effect transistors.

US publication no 20060120121 is interleaving control method for AC inverter including a waveform generator to generate a predetermined waveform.
CNl01005211 is high frequency emergency power system. This belongs to high frequency inversion including fly back converter based charger, push-pull DC-DC boost converter and half bridge driver.
In the present invention micro-controller & DSP based systems are replaced by Field Programmable Gate Arrays (FPGA). This invention provides a single chip solution for implementation of various complex digital control functions in hardware. The FPGA also communicates with user interface devices. The information to the user is also provided in the form of audio messages. In the present invention, full bridge topology is used for DC-AC inverter stage.
OBJECT OF THE INVENTION
Primary object of the present invention is to provide field programmable gate arrays (FPGA) based high frequency inverter for generation of AC power signals from a DC source at the time of power failure of the AC line source.
It is another object of the present invention to generate multiple pulse width modulated signals at different frequencies and duty cycles together with control signals for handling various power stages involved in high frequency inverter.
It is another object of the present invention to generate multiple pulse width modulated signals with dead band control using the FPGA for driving MOSFETs in H-bridge configuration.
It is still another object of the present invention to eliminate the need of external PWM controller required for maintaining constant DC bus output voltage of DC-DC boost converter by use of field programmable gate arrays.
It is another object of the present invention to generate fixed frequency pulse width modulated signals using FPGA for power supply circuit required for MOSFET drivers without using dedicated control integrated circuit.
It is another object of the present invention to replace micro-controller & DSP based systems by field programmable gate arrays, thus providing a single chip solution for implementation of various complex digital control functions in hardware and thereby eliminating the software overhead present in conventional microcontroller based systems.
It is another object of the present invention to provide control & generation of pulse width modulated signals for switch mode power supply (SMPS) based battery charger using the FPGA.

It is another object of the present invention to provide control for LCD/TFT and smart panel based display using FPGA for displaying the information to the user. This dedicated hardware control implementation eliminates any architectural or software compromises required for handling slow peripherals such as LCD display in the conventional microcontrollers.
It is also an object of the present invention to use FPGA with internal flash memory for storage of the configuration bit stream internally and also provides flash memory space for other applications, thus eliminating the risk of storing configuration data externally and reducing the cost of external programmable memory (PROM).
It is another object of the present invention to provide communication with PC using FPGA for providing useful information to the user such as mains failure, mains low/high, overload, short circuit, fuse blown, battery low etc. It also provides a PC based Graphical User Interface for configuring various parameters such as battery low cut & charging current, input mains voltage & frequency window setting etc.
Yet another object of the present invention is to provide future-up-gradation by using FPGA which can be reprogrammed for any changes required in the hardware configuration of the control logic depending on the specific needs of the product.
STATEMENT OF INVENTION
According to this invention there is provided a FPGA Based Single Phase High Frequency Inverter comprising of a DC-DC converter which converts the battery voltage to high DC voltage. This high DC voltage is fed to DC-AC Inverter section comprising of MOSFETs in H-bridge configuration. Pulse width modulated signals with dead band control are generated using the FPGA for driving these MOSFETs. Multiple pulse width modulated signals at different frequencies and duty cycles together with control signals are generated for handling various power stages involved in High Frequency Inverter.
SUMMARY OF THE INVENTION
These and other objectives of this invention are accomplished by providing a high frequency inverter which includes field programmable gate array (FPGA) for handling control operations and generation of multiple pulse width modulated signals. Dedicated hardware control logic is implemented inside the FPGA for handling switching devices of multiple power stages & also for achieving rest of the functionality of the high frequency inverter.
Various voltage & current signals are sensed and fed to an analog to digital converter which converts these analog signals to the digital format required by the FPGA. On the basis of these feedback signals, control logic decisions are made inside the FPGA in order to have the desired output. This analog to digital converter can be external to the FPGA or a mixed signal FPGA can be used with in-built ADC.

The FPGA regulates the fixed frequency PWM duty cycles used in DC-DC converter. A constant DC bus output voltage is maintained by either increasing or decreasing the duty cycle of the PWM outputs depending upon the state of the DC bus. Any decrement in the DC bus voltage, either due to decrease in input battery voltage or reduction in output load of DC-DC converter, is compensated by increasing the duty cycle. In a similar manner, any increment in the DC bus voltage either due to increase in battery voltage or the output load, is compensated by reducing the duty cycle of the PWM outputs
The output of this DC-DC converter is connected to the input of DC-AC inverter. A sine modulated PWM signal is generated for handling MOSFETs in the H-bridge. These PWM signals have programmable deadband to avoid any short circuit condition appearing due to switching of upper & lower MOSFETs at the same time.
The charger section of the inverter comprises of SMPS charger which operates in forward converter topology and charges the battery in constant current & constant voltage mode. Other charging topologies like the fly back control & two transistor methods can also be adapted in this system. Apart from generating the pulse width modulated signal, FPGA also monitors the other feedback parameters such as battery current & charging current for controlling the operation of the charger. If the battery is completely charged, FPGA switches the charger from a boost cum absorption state to a float state. The charger has a built-in over current and under/over input AC voltage protection.
The FPGA also communicates with devices such as the LCD/TFT display, touch screen/smart panel and other user interface. Dedicated display controller is implemented inside the hardware for controlling the operation of these display/smart panels. The communication with PC is used for monitoring, setting and data logging of various system parameters required for the analysis of the system performance & power quality etc. Various other protocols can also be used while communicating with the rest of the systems.
In an embodiment of the present invention, control for other display devices such as TFT, Touch Screen/Smart Panel and other user interface can also be provided.
In the other embodiment of the present invention, a 16-bit or higher 32-bit CPU can be implemented inside the FPGA, as per the control application requirement & features provided with the system.
In the other embodiment of the present invention, other communication interface can also be used based on different communication protqcols such as RS-422, RS-485, Universal Serial Bus interface (USB) & 10/100 Ethernet access.
In another embodiment of the present invention, mixed signal FPGA with in-built ADC can be used in place of external ADC.
Yet another embodiment of the present invention, different bit resolution of ADC can be used such as 8-bit, 12-bit or 14-bit.

In the other embodiment of the present invention, various schemes can be used for DC-DC Boost converter.
In other embodiment of the present invention, information to the user can be provided in the form of audio messages.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Further objects and advantages of this invention will be more apparent from the ensuing description when read in conjunction with the accompanying drawings and wherein:
FIG. 1 shows a block diagram of FPGA based high frequency inverter.
FIG. 2 shows an internal block diagram of FPGA.
FIG. 3 shows a circuit diagram of DC-DC power supply.
FIG. 4 shows a circuit diagram of DC-DC boost converter with DC bus sense.
FIG. 5 shows a circuit diagram of Battery current & charging current sense
FIG. 6 shows a circuit diagram Battery voltage sense.
FIG. 7 shows a circuit diagram of MOSFET drivers with signal conditioning circuitry & H-bridge DC/AC converter.
FIG. 8 shows a circuit diagram of Power supply for signal conditioning circuitry
FIG. 9 shows a circuit diagram of Output voltage sense.
FIG. 10 shows a circuit diagram of Output current sense.
FIG. 11 shows a circuit diagram of Input AC & zero cross sense.
FIG. 12 shows a circuit diagram of Charger on/off relay switch.
FIG. 13 shows a circuit diagram of Transfer switch for load.
DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING DRAWINGS
FIG. 1 is the block diagram of FPGA based high frequency inverter 100. The inverter consists of a DC-DC converter 101 which converts the battery 102 voltage to high DC bus voltage 103. This high DC bus voltage 103 is fed to the DC-AC inverter 104 which involves

MOSFETs arranged in H-bridge configuration. Pulse width modulated signals with dead band control are generated using the FPGA 105 for driving these MOSFETs.
The FPGA also communicates with devices such as the LCD/TFT display, touch screen/smart panel 106 and other user interface. Information is provided to the user in the form of audio messages/ buzzer beeps/ sounds 107 etc. A keypad based user interface 108 is also present where controls for the inverter like start/stop, reset etc are provided to the user. The communication interface 109 is primarily based on RS-232 protocol.
This invention consists of Analog to digital converter 110 which converts the analog signals to digital format. Various voltage & current sensing circuits such as DC bus sense 112, battery current 113 and battery voltage 114 sense are also present. The FPGA 105 is powered up by the supply section 111.
The secondary side of the inverter consists of MOSFET drivers 115 arranged in H bridge configuration. LC filter 116 is provided to remove the desired high frequency component from H-bridge output. The power supply 117 is required for signal conditioning circuitry present in the secondary side prior to the H-Bridge. Output voltage sense section 118 senses the output AC voltage level in inverter mode. Similarly output current sense 119 senses the corresponding current level.
The primary side also consists of sensing circuits such as Input voltage sense 120 & zero cross/phase sense 121. Charger ON/OFF switch 122 enables the SMPS charger 123 in case of a grid supply failure or if the grid supply 124 is out of the specified region.
The present invention comprises of transfer switch 125, charging current sense circuit 126, load 127, circuit breaker 128, surge protection 129 & heat sink temperature sensing 130.
FIG. 2 is the internal block diagram of the FPGA 105. Separate hardware modules such as DC-DC boost controller 201, power supply controller 202, H-bridge controller 203, SMPS controller 204, display controller 205, keypad interface 206 & communication interface 207 are implemented inside the FPGA 105.
The control unit 208 provides the necessary logic & control signals required to achieve the overall functionality of the high frequency inverter. A central processing unit (CPU) 209 is also used in conjunction with the control unit 208 which has access to the internal flash memory 210. This internal flash memory 210 not only provides the storage space for FPGA configuration bit stream but also provides space for storing user application bits required by the CPU 209. The data processing capability of the CPU 209 is 8-bit but the flexibility of programmable system architecture & control unit 208 allows the implementation of 16-bit or higher 32-bit CPU as per the control application requirement & features provided with the system.
The display controller 205 provides control for LCD/TFT & touch screen/smart panel 106. Smart panels 106 and touch screens 106 provide bi-directional interface where information is processed & displayed on the basis of human feedback. Other display systems can be easily accommodated with modifications in the display controller 205. A keypad based user interface 108 is also present where controls for the inverter like start/stop, reset etc are provided to the user.

Other Information regarding various parameters & conditions such as 'No Load', 'Full Load' and 'Overload' are provided to the user in the form of audio messages/ buzzer beeps/ sounds 107 etc.
The communication interface is primarily based on RS-232 protocol which is commonly used in communication with the PC 109. This communication can be achieved at different baud rates selected by the user. Other communication protocols such RS-422, RS-485 & 10/100 ethernet access can also be used as per the application requirement.
The analog signals are fed to analog to digital converter 110 which converts these signals into digital format so that they can be processed by the control unit inside the FPGA 105. The bit resolution for ADC 110 can vary from current 10-bit resolution to lower 8 bit or higher 12-bit or more depending upon the system requirement. A plurality of ADC 110 channels are used for other analog feedback signals measured at various stages of the high frequency inverter.
A Real Time Clock (RTC) is also used in this system. Continuous operation of this clock is achieved by an alternate source of power even if the primary source is not available. This RTC is driven by an external crystal oscillator.
FIG. 3 is the circuit diagram of DC-DC power supply 111. This is the supply section required to power-up the FPGA 105. Three DC-DC step-down regulators (Rl, R2, R3) provides the auxiliary supply voltage, internal core supply voltage and I/O banks supply voltage required by the FPGA 105. The outputs of these supplies are cascaded in a way that the output of the first supply enables the second supply & output of the second in turn enables the third one. The cascading is based on the sequencing requirement of the configuration mode used for successful power-on of the FPGA 105. The input voltage for these regulators is generated by a supply 301 which takes power from the battery 102 and one of the bias winding of isolated DC-DC boost converter 101.
FIG. 4 is the circuit diagram of a DC-DC boost converter 101 with DC bus sense 112. The FPGA 105 monitors the DC bus 103 and regulates the fixed frequency PWM duty cycles used in DC-DC converter 101. A constant DC bus output voltage is maintained by either increasing or decreasing the duty cycle of the PWM outputs (PWMA & PWMB) depending upon the state of the DC bus 103. Any decrement in the DC bus voltage either due to decrease in input battery voltage or reduction in output load of DC-DC converter 101 is compensated by increasing the duty cycle. In the similar manner, any increment in the DC bus voltage either due to increase in battery voltage or output load 127 is compensated by reducing the duty cycle of the PWM outputs.'The PWM signals as well as necessary control signals are generated by FPGA 105, thus eliminating the need of external integrated control circuitry.

The opto isolation 405 is required to maintain isolation between the input low DC voltage and the output live power stages (high voltage DC bus 103 and AC power section). The output from opto isolator is fed to the ADC 110.
Fig 5 is the circuit diagram for battery current 113 & charging current sense 126. The upper section generates the corresponding analog signal with respect to current level of the battery 102. The lower section provides the charging current sense required to operate the SMPS charger 123. The analog signals are fed to ADC 110 which samples the analog signal at a fast sampling rate to obtain the equivalent digital signal.
FIG. 6 is the circuit diagram for a battery voltage sense 114. It generates the corresponding analog voltage signal, which is again fed to the ADC 110. The resistor network prior to the ADC 110 ensures that the signal falls between the operating ranges of the ADC 110. The FPGA 105 monitors the battery voltage periodically & generates the necessary control signals on the basis of this feedback signal.
FIG. 7 is the circuit diagram of H-bridge DC/AC converter 104 with MOSFET drivers 115 & signal conditioning circuitry prior to the MOSFETs. The output of the DC-DC converter 101 is connected to the input of DC-AC inverter 104. Sine modulated PWM signals (PWM_LH, PWM_LL, PWM_RH & PWM_RL) are generated by the FPGA 105 for handling MOSFETs (Ml, M2, M3, M4) in the H-bridge 701. These PWM signals have programmable dead band in order to avoid any short circuit condition appearing due to switching of upper & lower MOSFETs at the same time. The output of this DC-AC inverter 104 is passed through a filter 116 to obtain pure sinusoidal output.
FIG. 8 is the circuit diagram of the power supply 117. This power supply is required for the signal conditioning circuitry present in the secondary side prior to the H-Bridge DC/AC converter 104. Fixed frequency PWM signal (PWMPS) is generated by the FPGA 105 in order to control the corresponding switching device used in the circuit.
Fig. 9 depicts the output voltage sense section 118 of the system. It converts the output AC voltage level to corresponding analog signal in the inverter mode. This analog signal is fed to the ADC 110 which samples these analog signals at a fast sampling rate to obtain the equivalent digital signal. The resistor network prior to the ADC 110 ensures that the signal falls between the operating ranges of the ADC 110. The FPGA 105 compares this signal with an internal reference signal (corresponding to constant output voltage) and modulates the PWM signals of the H-bridge converter 104 according to the output feedback error in order to maintain the regulated output voltage.
Fig 10 is the circuit diagram of the output current sense 119. It senses the load current levels of the single phase inverter in the inverter mode. This analog signal is fed to the ADC 110 which samples the analog signal at a fast sampling rate to obtain the equivalent digital signal. The FPGA 105 measures this digital signal to ensure that the output AC current of the single phase inverter 100 is within the permissible range. If the received values fall outside the tolerance band, FPGA 105 generates a warning of overload through display and buzzer beep.

The FPGA 105 also checks the conditions of No Load', 'Full Load' and 'Overload' against this parameter.
A pulse by pulse current limiting circuit has been used to limit the inrush current through MOSFET devices (Ml, M2, M3, M4) of H-bridge converter 104 in case of an increase in the output current over a certain level. This condition mainly arises either due to short circuit condition in the output of system or load characteristics or transient load.
When the load current exceeds this level, FPGA 105 limits the current pulse within a few microseconds by disabling the PWMs. If the overload or the short circuit condition persists N times, then the FPGA 105 will shut down the inverter (DC-DC boost 101 & H-bridge converter 104) operation permanently. The user can restart the system by resetting it manually though the user interface panel 108 of the system.
FIG. 11 is the circuit diagram for input voltage 120 & zero cross/phase sense 121. The upper section 120 of the circuit senses the input AC voltage level. This analog signal is fed to the ADC 110 which samples these analog signals at a fast sampling rate in order to obtain the equivalent digital signal. The resistor network prior to the ADC 110 ensures that the signal falls between the operating ranges of the ADC 110. The lower section 121 of the circuit generates the zero cross signal corresponding to the input grid supply 124. This zero cross signal is fed to one of the I/Os of FPGA 105 to detect phase and frequency of the input grid supply 124.
Fig 12 is the circuit diagram of charger on/off relay switch 122. During the presence of grid supply 124, FPGA 105 enables the SMPS charger 123 by the relay switch. In case of a grid supply failure or if the grid supply 124 is out of the specified region, the FPGA 105 disables the charger 123 by disconnecting the grid supply 124 through the charger ON/OFF relay switch.
Fig 13 is the circuit diagram of a transfer switch 125 for load 127. The FPGA 105 periodically senses the grid supply 124 voltage and frequency. If the grid supply 124 is available within the specified limits, then the FPGA 105 will first disable the DC-DC boost 101 & the bridge converter 104 and then switch the position of the transfer switch 125 to bypass mode in order to run the output load 127 directly from the grid supply 124. In this case, both line out and neutral out from H-bridge converter 104 remain disconnected from the grid supply 124 line and neutral.
If FPGA 105 detects that the grid supply 124 has failed or it is outside the specified limits, then it disconnects the charger 123 and switches the position of the transfer switch 125 to run the load from H-bridge 701 output.
It is to be noted that the present invention is susceptible to modifications, adaptations and changes by those skilled in the art. Such varjant embodiments employing the concepts and features of this invention are intended to be within the scope of the present invention, which is further set forth under the following claims:-

WE CLAIM:
1. A FPGA Based Single Phase High Frequency Inverter comprising of a DC-DC converter which converts the battery voltage to high DC bus voltage, which is fed to the DC-AC inverter which involves MOSFETs arranged in H-bridge configuration wherein Pulse width modulated signals with dead band control are generated using the FPGA for driving the MOSFETs arranged in H-Bridge configuration and Multiple pulse width modulated signals at different frequencies and duty cycles together with control signals in high frequency inverter handle various power stages.
2. A FPGA Based Single Phase High Frequency Inverter as claimed in claim 1 wherein the FPGA comprising of separate hardware modules such as DC-DC boost controller, power supply controller, H-bridge controller, SMPS controller, display controller, keypad interface and communication interface.
3. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims comprising of control unit providing the necessary logic and control signals required to achieve the overall functionality of the high frequency inverter wherein the control unit is used in conjunction with a central processing unit, which has access to internal flash memory such as herein described.
4. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which provides a single chip solution for implementation of various complex digital control functions in hardware.
5. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which eliminates the need of external PWM controller required for maintaining constant DC bus output voltage of DC-DC boost converter by use of Field Programmable Gate Arrays, thus eliminating external control circuitry.
6. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which generates fixed frequency Pulse Width Modulated signals using FPGA for power supply circuit required for MOSFET drivers without using dedicated control integrated circuit.
7. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which replaces Micro-Controller & DSP based systems by Field Programmable Gate Arrays, thus providing a single chip solution for implementation of various complex digital control functions in hardware and thereby eliminating the software overhead present in conventional microcontroller based systems.

8. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which provides control & generation of Pulse Width Modulated signals for Switch Mode Power Supply (SMPS) based battery charger using the FPGA.
9. A FPGA Based Single Phase High Frequency Inverter as claimed in any of the preceding claims which provides control for LCD/TFT and Smart Panel based display using FPGA for displaying information to the user and this dedicated hardware control implementation eliminates any architectural or software compromises required for handling slow peripherals such as LCD display in conventional micro-controllers.
10. A FPGA Based Single Phase High Frequency Inverter substantially as herein described with reference to the accompanying drawings.