Claims:We Claim:

1. A high power regulated pulse generator circuit, the circuit comprising of:
a first voltage source for supplying DC bias voltage;
a second voltage source for supplying DC input voltage;
a pulse generator for supplying a pulse command;
a gate driver integrated circuit configured for controlling the flow of the DC input voltage through a high-side switch on the basis of the pulse command;
a driving arrangement coupled to the voltage source and configured for driving the high-side switch;
a bootstrap circuit coupled to the driving arrangement for providing necessary biasing voltage to the high-side switch; and
a regulating arrangement coupled to the high-side switch for regulating the voltage amplitude of output pulse signal.
2. The circuit as claimed in the claim 1, wherein the gate driver integrated circuit is connected to the pulse generator for receiving the pulse command.
3. The circuit as claimed in the claim 1, wherein the high-side switch is selected from a list comprising of an N channel MOSFET or a P channel MOSFET.
4. The circuit as claimed in the claim 1, wherein the regulating arrangement comprises of parallelly connected differential transistors for providing feedback to the driving arrangement.
5. The circuit as claimed in the claim 1, wherein a Zener diode is connected to the differential transistors for setting a reference voltage.
, Description:A HIGH POWER REGULATED PULSE GENERATOR CIRCUIT
FIELD OF INVENTION
The invention generally relates to the field of pulse generators and particularly to a high power regulated pulse generator circuit.
BACKGROUND
A pulse generator is an electronic circuit used for generating rectangular pulses. The pulses need to be regulated for low frequency applications. In one prior art, a pulse voltage regulator is disclosed. The regulator includes a transformer having a primary winding disposed to receive pulses of high voltage energy and a secondary winding disposed for providing output load pulses in response to input pulses. A diode and a capacitor are coupled, in series, across the said transformer secondary winding. The anode of said diode being coupled to one side of said transformer and a resistance network coupled across said capacitance. A zener diode and switching means coupled in series across said capacitance for selectively discharging said capacitance to a predetermined level. The regulator filters out the ripple in low power pulse signal and regulates the signal amplitude. The disadvantages associated with this prior art are, the regulator is only applicable for low power loads and regulates only amplitude of the pulses. In another prior art, a microcontroller based high voltage pulse electric field generator for generating high voltage pulse signal from the step-down AC input supply is disclosed. The main disadvantage of this prior art is that it is not applicable for DC source applications.
Hence, there is a need for a pulse generator circuit for generating high power and regulated output pulse signal for low frequency applications.
BRIEF DESCRIPTION OF DRAWINGS
So that the manner in which the recited features of the invention can be understood in detail, some of the embodiments are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG.1 shows a block diagram of a high power regulated pulse generator circuit, according to an embodiment of the invention.
FIG.2 shows a schematic diagram of a high power regulated pulse generator circuit, according to an embodiment of the invention.
FIG.3 shows input and output signals of the high power regulated pulse generator circuit, according to an embodiment of the invention.
FIG.4a shows a graphical representation of rising time of the output pulse signal, according to an embodiment of the invention.
FIG.4b shows a graphical representation of falling time of the output pulse signal, according to an embodiment of the invention.
SUMMARY OF THE INVENTION
The invention provides a high power regulated pulse generator circuit. The circuit includes a first voltage source for supplying DC bias voltage, a second voltage source for supplying DC input voltage and a pulse generator for supplying a pulse command. A gate driver integrated circuit is configured for controlling the flow of the DC input voltage through a high-side switch based on the pulse command. A driving arrangement is coupled to the voltage source and is configured for driving the high-side switch with faster rise and fall times. A bootstrap circuit is coupled to the driving arrangement for providing necessary biasing voltage to the high-side switch. A voltage regulating arrangement is coupled to the high-side switch for regulating the voltage amplitude of an output pulse signal. The power of the output pulse signal is in the range of 50W and can be configured for higher power by changing the high-side switch with higher current capacity.
DETAILED DESCRIPTION OF THE INVENTION
Various embodiments of the invention provide a high power regulated pulse generator circuit. FIG.1 shows a block diagram of a high power regulated pulse generator circuit, according to an embodiment of the invention. The high power regulated pulse generator circuit includes a first voltage source 1 for supplying DC bias voltage 1a, a second voltage source 2 for supplying DC input voltage 2a, and a pulse generator 3 for supplying a pulse command 3a. In one example of the invention, the first voltage source 1 and the second voltage source 2 are made as a single voltage source for supplying both the DC bias voltage 1a and DC input voltage 2a, when the input voltage requirement is in the acceptable range of gate driver circuit. The acceptable range is 8V to 18V. Further, in another example of the invention, the first voltage source 1 and second voltage source 2 are made separate, when the input voltage & the output voltage requirement are below or above the acceptable range. A gate driver integrated circuit 4 is connected to the pulse generator 3 for receiving the pulse command 3a. The gate driver integrated circuit 4 is configured for controlling the flow of the DC input voltage 2a through a high-side switch 5 based on the pulse command 3a. The high-side switch 5 described herein includes but is not limited to a high-side N channel MOSFET or high-side P channel MOSFET. In one example of the invention, the high-side switch 5 is the high-side N channel MOSFET. A driving arrangement 6 is coupled to the voltage source 1 and is configured for driving the high-side switch 5 with faster rise time and fall time. A bootstrap circuit 7 is coupled to the driving arrangement 6 for providing necessary biasing voltage. A voltage regulating arrangement 8 is coupled to the high-side switch 5 for regulating the voltage amplitude of an output pulse signal 5a.
FIG. 2 shows a schematic diagram of a high power regulated pulse generator circuit, according to an embodiment of the invention. The circuit includes a first voltage source (not shown) for supplying DC bias voltage 1a, a second voltage source (not shown) for supplying DC input voltage 2a and a pulse generator (not shown) for supplying a pulse command 3a. A gate driver integrated circuit 4 is connected to the pulse generator for receiving the pulse command 3a. The gate driver integrated circuit 4 is configured for controlling the flow of the DC input voltage 2a through a high-side switch 5 based on the pulse command 3a. The high-side switch 5 described herein includes but is not limited to a high-side N channel MOSFET or high-side P channel MOSFET. In one example of the invention, the high-side switch 5 is the high-side N channel MOSFET M1. A driving arrangement 6 is coupled to the voltage source 1 and configured for driving the high-side switch 5 with faster rise time and fall time. The driving arrangement includes diodes (D2, D3), resistors (R1, R2, R3, R4 and R5), a first transistor Q1 and a second transistor Q2. A bootstrap circuit 7 is coupled to the driving arrangement 6 for providing necessary biasing voltage to the second transistor Q2 thereby driving the high-side N channel MOSFET M1. The bootstrap circuit 7 includes a diode D1 and a capacitor C1. A voltage regulating arrangement 8 is coupled to the high-side switch 5 for regulating the voltage amplitude of an output pulse signal 5a. The DC input voltage 1a charges the bootstrap capacitor C1 through the diode D1 and resistor divider R9 & R10. The gate driver integrated circuit 4 turns OFF and ON the first transistor Q1 during respective high and low signal of the pulse command 3a. The turning OFF of the first transistor Q1 allows the bootstrap circuit 7 to provide the necessary biasing voltage to the second transistor Q2 through the resistor R3. The second transistor Q2 turns forward bias and turns ON the high-side N channel MOSFET M1 through the resistor R4. The turning ON of the first transistor Q1 causes reverse bias of the second transistor Q2 and results in turning OFF of the high-side N channel MOSFET M1. The turning ON and OFF of the high-side N channel MOSFET M1 generates an output pulse signal 5a. In one example of the invention, the power of the output pulse signal is 50W and in another example of the invention, the power of the output pulse signal is 100W. The circuit can be configured for higher power by changing the high-side switch 5 with higher current capacity. The voltage regulating arrangement 8 is coupled to the high-side N channel MOSFET M1 for regulating the voltage amplitude of the output pulse signal 5a. The voltage regulating arrangement 8 includes parallelly connected differential transistors (Q3 and Q4) for providing feedback to the driving arrangement 6. A base voltage of the second transistor Q2 is adjusted based on the feedback provided by the differential transistor Q3. A Zener diode Z1 is connected to the differential transistors (Q3 and Q4) for setting a reference voltage. The output pulse signal 5a is regulated based on the resistor divider R9 & R10. The output pulse signal 5a has a rise time & fall time of around 420nS as per simulation results.
FIG.3 shows input and output signals of the high power regulated pulse generator circuit, according to an embodiment of the invention. The DC voltage 12V, represented by 1a & 2a and the pulse command 5V, represented by 3a, are supplied to the circuit. The circuit generates an output pulse signal 5a of 10V. The output pulse signal 5a has duration of 1mS ON time and 1mS OFF time. The output pulse signal is regulated to 10V and can be ON or OFF based on the pulse command 3a.
FIG.4a shows a graphical representation of rise time of the output pulse signal, according to an embodiment of the invention. The output pulse signal has the rise time of 420nS as per simulation results.
FIG.4b shows a graphical representation of fall time of the output pulse signal, according to an embodiment of the invention. The output pulse signal has the fall time of 420nS as per simulation results.
Hence the circuit generates regulated high power output pulse signal. The circuit can be used in low frequency applications with faster rise and fall times. The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.