PRIOR ART I
[0028] The subtraction operation for unsigned numbers is carried out using Ripple Borrow Subtractor (RBS). A conventional 16-bit ripple borrow subtractor, in which the bits BO through B15 bits are subtracted from the bits A0 through A15, is shown in Fig.l. The structure consists of 16 full subtractor (FS) blocks in cascade supplied with an input borrow bit Bin. It generates the difference bits SO through 575, and the borrow bits bO through Bout, to be propagated to the next block in order. In other words, the first block performs subtraction and produces the difference bit SO and the borrow bit bO. This bO bit is applied as input to the next block.
[0029] The subtraction operation for signed numbers is performed using the conventional addition method by the two's complement method. The subtraction of A - B is done by taking the 2's complement of B and adding it to A. The 2's complement is obtained by taking the l's complement or flipping all the bits, and then adding a 7' to the complemented value. The l's complement can be created using inverters. In the signed number system, the most significant bit (MSB) indicates the sign bit. If the MSB bit is zero (0), then it is recognized as a positive number. Else, it is considered as a negative number.
|0030] The structure of an half subtractor using an inverter, one XOR and one AND gate is shown in Fig. 2a and it incurs a maximum of two latency to produce the output. The generation of difference D needs one latency and that of borrow B incurs two latency as shown in Fig. 2a. The structure of an half adder is shown in Fig. 2b, and it takes one latency to produce the sum bit S and carry bit C. The 2-bit binary to excess-1 converter (BEC) shown in Fig. 2c can add a / to the 2-bit data.
100311 The internal structure of the conventional full subtractor block is shown in Fig. 3. It incurs 2 latency values (when data goes through the 2 XOR gates) to produce the difference bit (D) and 4 latency values (through inverter, AND gates and OR gate) to produce the borrow bit (B). Thus, each block of this subtractor shown in Fig. 1 incurs a delay in waiting for the previous borrow to perform its operation and pass the borrow bit to the next block, i.e., for the signal bO of FS1 to pass to FS2, and so on, up to the point when bl4 passes through FS16. For the 16 bit full subtractor shown in Fig. 1, it thus takes 16*4= 64 latency values to produce the last borrow bit Bout.
10032] Consider a 4-bit subtraction process (1001 - 0111) using conventional ripple borrow subtractor (RBS). The subtrahend of 0111 is subtracted from the minuend 1001 using the conventional RBS and the process is as shown in Fig. 4a. The borrow bit ripples from least significant bit (LSB) position towards the most significant position (MSB) all through the whole word length. This prior art, namely, the conventional ripple borrow subtractor hence requires more time and it increases linearly as the number of bits increases also.
DETAILED DESCRIPTION OF THE INVENTION
[0033] The fact that the rippling borrow acts as the primary factor that determines the time spent in the subtraction process set in motion the conceptualization and implementation of the present invention. The hypothesis of generating the difference without waiting for the borrow bit generated by the previous bit stage has been employed in the design.
|0034] The following details present the embodiment of the present invention, namely, the Borrow Select Subtractor (BSLS). Fig. 4b embodies the 4-bit subtraction process. Considering unsigned numbers, the BSLS operates by independently generating the outputs, considering both the cases of (1) the borrow bit being present or a logic 7' and (2) the borrow bit being absent or a logic '0', or without the borrow from

the previous stage. The lower 2 bits of the subtrahend 11 are subtracted from the lower 2 bits of the minuend 01. This operation produces a borrow and the borrow bit so generated is applied as a select signal to a multiplexer, as shown in Fig. 5.
[0035] Considering the subtraction operation in the upper 2 bits, the BSLS operates without waiting for the borrow bit from the lower two bits, in parallel with the subtraction process of the lower 2 bits. As explained above, both the outputs, considering the borrow bit being a '/' or '0', are generated in parallel and applied as inputs to a multiplexer. To elaborate, considering an existing borrow bit of logic 1, the upper subtrahend bits (01) are incremented by one (i.e., 01+1=10) as shown inside the circle and the result generated from the process is subtracted from the upper minuend bits (10) as shown in Fig. 4b and the result is applied to one of the two inputs of the multiplexer.
[0036] In an embodiment of the borrow select subtractor, as depicted in Fig. 4c, considering no borrow bit (logic '0') from previous stage, the most significant subtrahend bits (01) are subtracted from the most significant minuend bits (11) and the resultant bit is applied to the second input of the multiplexer. Thus, both the outputs, without and with borrow difference are applied to the multiplexer inputs. Based on the borrow input obtained from the previous stage, that acts as the select line for the multiplexer, the correct difference is sent as the final output.
10037] In an embodiment, the Boolean expressions depicting the 4-bit BSLS operation can be listed as follows:
Diff[l:0] = A[1:0]- B[1:0]
{Bout, Diff[3:2]} = A[3:2] - B[3:2] Considering no borrow bit
Diff[1:0] = A[1:0]- B[1:0]
{Bout,Diff[3:2]} = A[3:2]- (B[3:2] + 1 Considering the borrow bit
|0038] In an embodiment, the BSLS may be used as 16-bit subtractor for unsigned numbers.
[0039| In an embodiment, the BSLS may be used as 16-bit subtractor for signed numbers.
10040] In an embodiment, the BSLS may be used as 16-bit subtractor.
[0041] In an embodiment, Group 1 may act as a 2-bit subtractor.
[00421 In an embodiment, Group 2 may act as a 2-bit subtractor.
(0043] In an embodiment, Group 3 may act as a 3-bit subtractor.
[0044] In an embodiment, Group 4 may act as a 4-bit subtractor.
|0045] In an embodiment, Group 5 may act as a 5-bit subtractor.
[0046] The BSLS logic may be used in a multi-bit subtractor circuit.
(0047) The inventive embodiments from [0034] to [0046] can be used in a variety of applications involving arithmetic operations. A typical application where the present invention can readily be implemented is digital signal processing, and also for any architecture involving subtraction, multiplication, division etc.

[0048] To elaborate the application of BSLS for subtraction operation of unsigned binary numbers, consider the 16-bit borrow select subtracter shown in Fig. 5. It consists of five groups of gradually increasing and varying bit sizes of ripple borrow subtractors (RBS). The sizes of the RBS blocks are decided as per the requirement. For instance, an 8-bit borrow select subtractor may use RBS blocks of sizes 2:3:3. In the group 1, the RBS consists of two full subtractors applied with input data A[1:0], B[1:0] and the borrow bit Bin. It generates the difference bits DO and Dl by subtracting the bits BO and Bl from the bits A0 and Al.
|0049] The borrow bit bl is given as a select line to the multiplexer of Group 2. Now, consider Fig. 6a which shows the internal structure of the Group 2. It has two sets of 2-bit RBS, catering to the bits B[3:2] and A[3:2]. It consists of one half subtractor (HS), one full subtractor (FS), a 2-bit BEC, an half adder (HA) and 6:3 multiplexer (MUX6:3) for producing the output of D[3:2] and the borrow bit b2 as shown in Fig. 5 and Fig. 6a.
[0050] In an embodiment, the 2-bit binary to excess-1 converter (BEC) shown in Fig. 2c forms a component of the Group 2. It is used to add a 1 to the two most significant subtrahend bits, namely, B2 and B3, and produce the outputs marked 1, 2 and 3. When both the most significant subtrahend bits are high before the BEC operation, then the BEC output will be (11+1=100). In such a case, it will produce the output after a latency of 1. The 3rd bit output of BEC, namely, the wire 3 is connected to the HA as one of its inputs as shown in Figs. 5 and 6a. The least significant 2-bits (wires 1 and 2) are subtracted from the two most significant bits A2 and A3 of the minuend as shown in Fig. 6a. The borrow bit b of the subtractor of Fig. 6a and the upper bit wire 3 of the BEC output are applied to the HA to produce the relevant borrow bit. The HA as shown in Fig. 2b takes one latency to produce the sum bit S and the carry bit C. The carry bit of the HA is not considered and marked (NC) in Fig. 5, since only the borrow bit from HA is required as shown in Fig. 6a.
[0051 ] The output generated by HS (Half Subtractor) and FS (Full Subtractor) block, which has been generated without considering the borrow bit, is directly applied as inputs to the multiplexer as shown in Fig. 6a. A second input is supplied to the multiplexer, generated considering the borrow bit from the previous Group 1. And, as may be observed, the previous Borrow bit bl selects the correct output. It may be noted that the bits are identified with the same symbols, viz., D2, D3 and b2 for the bits processed for with and without the borrow bit from previous stage.
[0052] The embodied Groups 3, 4 and 5 works on the same principle as the Group 2. The structure of the respective groups 3,4 and 5 are shown in Figs. 6b, 6c and 6d respectively.
[0053] The following descriptions presents the embodiment of the Signed Borrow Select Subtractor as applied for subtraction of signed binary numbers.
[0054| To perform comparison with the prior art, the embodiments of the unsigned BSLS and the signed BSLS are compared with the ripple borrow subtractor and subtraction using addition by two's complement method respectively.
[0055] Unsigned numbers:
1. Firstly the subtrahend bits (B0 through B15) are converted into its two's complement form. The two's complement part consists of the inverter unit followed by the BEC unit as shown in Fig. 7.
2. The result so obtained is added to the minuend bits (A0 to A15) through the carry select adder (CSLA).

3. The carry bit Cout is applied as select signal to the multiplexer as shown in Fig. 7.
4. If the carry bit Cout is zero, then the result (SO to S15 and Cout) obtained is converted into its two's complement form.
5. If the carry bit Cout is logic 'P then it is inverted or flipped (made logic '0') to indicate that the obtained result is a positive value.
6. The Bout bit may be a logic 'P, in which case, it indicates that the final output (DO to D15) is a negative value.
[0056) The proposed signed BSLS is embodied as shown in Fig. 8. The BSLS (unsigned) block produces the unsigned subtraction output, dO through dl5, with the borrow bit b. If the subtrahend (BO through B15) is greater than the minuend (A0 through A15), then the proposed signed subtractor output must be a negative value. Hence, the design is so augmented that whenever the borrow bit b is high, which indicates that the obtained result is a negative value, the output of the unsigned BSLS is converted into its two's complement form. And, the borrow bit b with a logic '1' is propagated to the output to indicate that the output result is negative.
[0057] The two's complement structure consisting of the inverters and BEC accomplishes the conversion of the bits dO through dl5 to the two's complement value. The two's complement circuit part will function only when the bit b is high, with an activating signal low at the node X. However, when the bit b is zero, it indicates that the output result is a positive value. Thus, the embodiment will not need to convert the output into its two's complement form.
[0058] The bits dO through dl 5 reach the output through the multiplexer. The Bout indicates the sign bit. The borrow bit b is applied as select line to the multiplexer that enables selecting the correct output.
COMPARISON WITH PRIOR ARTS
|0059| The validation of the proposed method is carried out using 90nm technology library files from UMC. Cadence® EDA tools have been employed for the purpose. The various circuit parameters, such as the delay, power and circuit latency are found out and tabulated in Table 1 for comparison. The proposed unsigned BSLS and signed BSLS are compared with the ripple borrow subtractor and subtraction using addition by two's complement methods respectively, as shown in Table. 1.
[0060] Unsigned Numbers..The delay of the BSLS is found to be 48.1% of that incurred by the ripple borrow subtractor with a circuit latency of 44 against the 64 stages of latency of its counterpart. Hence, it is justifiably validated that the proposed circuit can provide excellent speed performance for unsigned subtraction operations. The delay comparison of the two types of circuits is depicted through Fig. 9a.
[0061] Fig. 9b depicts the power dissipation comparison of the BSLS against the RBS. As also indicated in Table 1, the power dissipation of BSLS is 5.15uW against the 5.54uW of RBS, gaining 7% power reduction. As can be noted from Table 1, the number of devices used in the design of BSLS is 282 against the 112 of that of RBS. Hence, this aspect of increased number of devices for realizing increased speed, all the while enjoying reduced power dissipation can be considered a major advantage and a positive trade-off posed by the design. To emphasize this point and to further validate the proposed scheme, the power-delay products of the two structures are calculated and depicted in Table 1. The power-delay product of BSLS is 51. 8% less than that of the ripple borrow subtractor. This attribute is a major advantage for the proposed structure.

[0062] Signed Numbers: In reference to Fig. 9b, the BSLS incurs only 44.98% of the power consumed by the conventional subtraction method through the addition of two's complemented subtrahend for the signed number operation, with 20.75uW of power consumed by BSLS against the 37.72uW of its counterpart, as embodied in Table 1. However, the worst case delay incurred by the BSLS is 1565ps against the 1425ps of its counterpart, with 9.8% increase in delay time as shown in Fig. 9a. This is due to the increased latency of 65 versus 57 of the conventional structure. As can be noted, the enhanced low power performance advantage of 44.98% well overcomes the slighter decrease in speed performance. To drive home this aspect, consider the power-delay product comparison between the two circuits. Fig. 9c depicts the power-delay product of BSLS against that of its counterpart. With a circuit delay of 1565 ps and a power dissipation of 20.75uW for BSLS, against the delay of 1425ps and power consumption of 37.72uW for the subtraction by its counterpart circuit, the PDP of 32.47fJ for BSLS is 39.6% lower than PDP of 53.75 lfl incurred by the later.
[0063] As discussed above, it may be noted that the rise in delay incurred by the BSLS architecture for signed numbers is only due to the two's complement part that becomes active when the subtrahend is greater than the minuend. In other words, the delay so calculated indicates the worst possible delay. For the best possible case, on the other hand, when the subtrahend is less than the minuend, the rise in delay would be only due to the path through the multiplexer. Hence, the latency and the resulting delay would be less than the counterpart.
[0064) The power-delay product is reduced by 51.75% and 32.47% for the unsigned and signed number
subtractions respectively as shown in Fig. 9c.
[0065) The proposed BSLS architecture for signed numbers achieves 44.99% reduced power than its
counterpart with a slightly larger delay of 8.94% due to the increased latency of 65 versus 57 of the
conventional structure. However, it may be noticed that the increased latency is the worst case delay that
could occur while passing through the two's complement part. In order to appreciate the design better, it
may be pointed out that the power-delay product of the proposed BSLS is reduced by 51.75% and 32.47%
for unsigned and signed operations respectively, which indicates the benefit of the method over the
conventional methods.
REFERENCES:
1. Neil H Weste and Kamran Eshragan, Principles of CMOS VLSI Design: A Systems Perspective II Edition, Addison-Wesley.
2. B. Ramkumar and Harish M Kittur, "Low-Power and Area-Efficient Carry Select Adder," IEEE Transactions on Very Large Scale integration (VLSI) Systems, Vol. 20, No. 2, February 2012.

A High Speed Borrow Select 16-Bit Subtractor
FIELD OF INVENTION
[0001] Field of invention is the high-speed digital logic circuits used for arithmetic operations in Very Large Scale Integrated Circuits for use in the processer architectures.
BACKGROUND OF THE INVENTION
[0002] Design of the high-speed data path logic systems is a niche area of research in VLSI system design. With the rapid evolution of silicon technology, the transistor size continues decreasing remarkably and the chips grow in functionality, complexity and switching frequencies. The ultimate performance of all such circuits is determined by the processing speed of data. All the communication and the signal processing applications involve digital circuits for the basic arithmetic operations such as addition, subtraction, multiplication, division etc. The elemental or modular designs of such arithmetic circuits make great strides in the culmination of efficient circuit architectures.
100031 Adders and subtractors form two of the primary circuit structures in the processor design. The speed of subtraction in digital subtractors is limited mainly by the time required in propagating the borrow bit through the subtractor. The difference between the corresponding two bits of the subtrahend and minuend respectively in an elementary subtractor is generated sequentially. In other words, the borrow bit out of tH position is generated by subtracting the ih subtrahend bit from the f minuend bit, and propagated to (i+l)'h position. This process can happen only after the previous bit position (i-1) has finished its subtraction with its borrow bit, if available, propagated into its next, or the (h position [6]. Thus, the speed of operation of the subtraction process is determined by the speed of the carry propagation. Higher the number of bits, more is the time for the borrow bit propagation.
OBJECTIVE OF THE INVENTION
[0004] The main objective of this invention is the design of a novel, subtractor circuit namely, the Borrow Select Subtractor (BSLS). The design shown here for the 16-bit data operations aims to alleviate the problem of borrow propagation delay by independently generating the bit differences, considering without borrow and with borrow from the previous bit position, and selecting the appropriate difference using the previous borrow bit as a select line of a multiplexer fed with both the bit difference values. Subtractors of any larger bit length can be implemented in the same line of design. Thus, this method offers a promising alternative to the conventional subtractor designs that accomplishes the process of subtraction either by the bit-by-bit subtraction process with the borrow bit propagated from right to left, or by using addition by the two's complement method for signed numbers.
STATEMENT OF INVENTION
[0005] The claimed Borrow Select Subtractor (BSLS) operates at low power. Higher speed of operation for the subtractor, while operating with both the unsigned and signed numbers has been realized through the novel design of the circuit.
[0006| For subtraction of typical unsigned numbers, the 16-bit BSLS architecture has been developed and compared with the conventional Ripple Borrow Subtractor (RBS). For subtraction operation on signed

numbers, a variant of the 16-bit BSLS architecture has been developed and compared with the conventional method subtraction through the two's complement method using addition.
|0007| The proposed architectures have been proved for increased speed, low power, reduced delay and less latency for the circuits against the prior art, with a moderately increased number of devices in the circuits. The performance analyses of the designs are made using 90nm CMOS process technology library files. The results demonstrate that the proposed architectures are superior to the conventional RBS and subtraction using 2's complement addition methods.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008) The facet, attributes and the advantages of the present invention will be believable from the
following description of the invention with reference to the attached drawings.
[0009] Fig. 1 depicts the prior art of the 16-bit Ripple Borrow Subtractor (RBS)
[0010| Fig. 2a embodies the prior art of the Half Subtractor (HS)
[00111 Fig. 2b embodies the prior art of the Half adder (HA)
[0012| Fig. 2c embodies the prior art of the 2-Bit Binary-to-Excess 1 Code converter
[0013] Fig. 3 depicts the prior art of the Internal Structure of Full Subtractor (FS)
[0014] Fig. 4a expounds the Ripple borrow subtractor
[0015) Fig. 4b illustrates the BSLS operation with borrow bit from previous stage
[0016) Fig. 4c depicts the BSLS operation with no borrow bit from previous stage
[0017) Fig. 5 develops the 16-bit Borrow Select Subtractor (BSLS)
[0018] Fig. 6a expounds the Group 2 of the 16-bit Borrow Select Subtractor (BSLS)
[0019] Fig. 6b expounds the Group 3 of the 16-bit Borrow Select Subtractor (BSLS)
|0020] Fig. 6c expounds the Group 4 of the 16-bit Borrow Select Subtractor (BSLS)
|0021] Fig. 6d expounds the Group 5 of the 16-bit Borrow Select Subtractor (BSLS)
[00221 Fig. 7 expounds the implementation of subtraction using the prior art, namely, the addition by
two's compliment method
[0023) Fig. 8 embodies the proposed 16-bit Signed Borrow Select Subtractor
[0024] Fig. 9a embodies the delay comparisons
[0025] Fig. 9b depicts the Power Comparisons
[0026| Fig. 9c embodies the Power-Delay-Product (PDP) Comparisons
|0027] Table 1 embodies the comparative observations made from the design of prior art and BSLS.

Claim 1: The 16-bit borrow select subtractor for operating with unsigned numbers comprises of 5
groups consisting of three 1:0 ripple borrow subtractors (RBS), two 2:0 RBSs, two 3:0 RBSs, two 4:0 RBSs, 2-bit binary-to-excess-code converter (BEC), 3-bit BEC, 4-bit BEC, 5-bit BEC, 6:3 multiplexer, 8:4 multiplexer, 10:5 multiplexer, 12:6 multiplexer connected with four half adders (HA). Inputs A[1:0] and B[1:0] are connected to the 1:0 RBS as inputs. Inputs A[3:2] and B[3:2] are connected to the 1:0 RBS at its input terminals. Inputs A[6:4] and B[6:4] are connected to the 2:0 RBS as inputs. Inputs A[10:7] and B[10:7] are connected to the 3:0 RBS as inputs. Inputs A[15:ll] and B[15:ll] are connected to the 4:0 RBS as inputs. Output of the 1:0 RBS is available as the difference D[l :0]. The borrow bit bl from group 1 is connected to the 6:3 multiplexer as select line, whose output is available as D[3:2]. The borrow output b2 is connected as the select line input of 8:4 multiplexer, whose output bits are D[6:4], and the borrow b3 from this stage is connected to the 10:5 multiplexer whose outputs are D[10:7] and bit b4 applied as select line to 12:6 multiplexer, that produces the difference bits D[15:l 1] and final borrow output Bout.
Claim 2: The borrow select subtractor arrangement for subtraction operation for signed numbers
comprises of BSLS as used for unsigned operation. Its output is directly connected to one set of two inputs of the multiplexer (MUX34:17) and another input set is connected through the two's complement circuit part, which is activated by the signal at node X.
Claim 3: The upper RBS blocks takes in 0 as the borrow bit and calculates the result, namely, 3, 4,
5 and 6 bits from the respective upper RBSs. Two parallel stages of subtraction process happen with 0 as input borrow bit and 1 as input borrow bit. The RBS consists of one full subtractor FS and one half subtractor HS.
Claim 4: The group 2 as claimed in claim 1 consists of the 1:0 RBS and multiplexer MUX6:3 to
produce the output D[3:2] with 0 as borrow bit. As claimed in claim 1, the group 2 consists of 2-bit BEC, HA and 1:0 RBS, which in turn comprises of 2 full subtractors and one half subtractor, along with the multiplexer MUX6:3 to produce difference bits D[3:2] with borrow bit from previous stage taken as 1.
Claim 5: The group 3 as claimed in claim 1 consists of the 2:0 RBS and multiplexer MUX8:4 to
produce the output D[6:4] with 0 as borrow bit. As claimed in claim 1, the group 3 consists of 3-bit BEC, HA and 2:0 RBS, which in turn comprises of 2 full subtractors and one half subtractor, along with the multiplexer MUX8:4 to produce difference bits D[6:4] with borrow bit from previous stage taken as 1.
Claim 6: The group 4 as claimed in claim 1 consists of the 3:0 RBS and multiplexer MUX10:5 to
produce the output D[10:7] with 0 as borrow bit. As claimed in claim 1, the group 4 consists of 4-bit BEC, HA and 3:0 RBS, which in turn comprises of 3 full subtractors and one half subtractor, along with the multiplexer MUX 10:5 to produce difference bits D[10:7] with borrow bit from previous stage taken as 1.
Claim 7: The group 5 as claimed in claim 1 consists of the 4:0 RBS and multiplexer MUX12:6 to
produce the output D[15:l 1] with 0 as borrow bit. As claimed in claim 1, the group 5 consists of 5-bit BEC, HA and 4:0 RBS which in turn comprises of 4 full subtractors and one half subtractor, along with the multiplexer MUX 12:6 to produce difference bits D[ 15:11 ] with borrow bit from previous stage taken as 1.
Claim 8: The borrow select subtractor for signed subtraction operation as claimed in claim 2,
consists of BSLS (unsigned block) whose outputs are directly connected to the multiplexer (MUX34:17). The multiplexer is operated by the select signal borrow bit b as coming from the unsigned BSLS.
Claim 9: As claimed in claim 2, when the borrow it b is 1, the two's complement circuit part is
connected to the output from BSLS (Unsigned).The first stage of two's complement part is 16 sets of

inverters and the outputs of inverters are connected the 16-bit binary-to-excess code converter BEC. The output of BEC are connected to the multiplexer MUX34:17 as the second set of inputs.
Claim 10: As claimed in claim 2, claim 8 and claim 9, the output of the multiplexer is DO through
D15 with the borrow bit Bout. The inputs to the multiplexer MUX34:17 are connected from BSLS (Unsigned) directly as claimed in claim 1, and from the two's complement circuit part which is the two's complemented value of dO to dl5 from BSLS (Unsigned) of claim 1.