A LOW POWER CLOCK DISTRIBUTION SCHEME
Field of The invention
The invention relates to clock distribution in electronic circuits. In particular the invention relates to reduction of power consumption by selective enabling of clock signals.
Background of Invention:
A vast majority of digital electronic circuits include synchronous sequential logic circuits that require a clock signal for their operations. One or more clock signals are distributed to every part of the circuit containing such synchronous sequential logic circuits. For large circuits it is a general practice to organize the clock distribution as a hierarchical arrangement in the form of a "clock tree" that distributes the clock over the entire circuit.
The power consumption of an electronic circuit is largely dependant on the switching of the logic circuits in response to the clock signal as the static power consumption especially for CMOS circuits that are widely used in electronic devices, is extremely low. The predominant dynamic power consumption is the result of charging and discharging of internal and external capacitors. Increased power dissipation also results in reduced reliability as the circuit components operate at a higher temperature. The increased power dissipation may also require the use of expensive packaging and/or heat dissipation arrangements to manage the heat generated, thereby resulting in increased cost.
In several applications or under certain conditions in a given application some synchronous, sequential logic circuits are not in use. This condition may arise frequently in programmable devices such as Field Programmable Gate Arrays (FPGAs) depending on the program used. Current circuit arrangements supply
'the clock signal to all points whether or not the synchronous sequentially logic at those points is in use. For example, the clock signal in a clock tree is supplied to all branches and leaves regardless or whether a particular leaf or branch is in use or not. This scheme results in wasted power. In the case of FPGAs this inefficiency can result in limitations on gate density and/or max clock speed. The consumption of power can be reduced by selectively enabling only the clock to only those leaves or branches of the clock tree that are connected to active sequential circuits.
US Patents 5652529 and 5703498 disclose a method for selective enabling of a clock tree by selectively switching of the clock in column and sector arrangements. However these inventions merely provide a selection mechanism leaving the actual selection of branch and leaf to the programmer. This results in a process that is relatively complex and inefficient to control the clock tree.
The Object and Summary of the invention:
The object of the invention to provide an improved clock distribution architecture that reduces power consumption.
Another object of the invention is to provide a mechanism that implements the
selection or deselection of the clock signals automatically based in circuit
operation.
Yet another object of the invention is to provide a scheme that implements
selective clock enabling in a multi-level hierarchical clock tree.
To achieve the said objective, this invention provides in an electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising:
disabling means for disabling the clock input to each deselected synchronous sequential logic block.
The said identifying means is a logic circuit that receives the select / deselect signal for each synchronous sequential logic block as an input and provides a defined logic signal when all its inputs are in the deselected state.
The said disabling means in a logic circuit for gating the clock signal to said synchronous sequential logic blocks.
The clock distribution is arranged in a hierarchical structure and an identifying means and a disabling means is provided for each level of clock hierarchy.
The said identifying means for a higher level of the clock hierarchy receives the outputs from the disabling means at the next lower level of the clock distribution hierarchy at its inputs.
The said disabling means for a particular level of the clock hierarchy receives the output from the identifying means at the same level of the clock hierarchy.
The instant invention also provides in a programmable gate array (PGA) containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising:
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.
The said identifying means is a logic circuit that receives the select / deselect signal for each synchronous sequential logic block as an input and provides a defined logic signal when all its inputs are in the deselected state.
The said disabling means in a logic circuit for gating the clock signal to said synchronous sequential logic blocks.
The clock distribution is arranged in a hierarchical structure and an identifying means and a disabling means is provided for each level of clock hierarchy.
The said identifying means for a higher level of the clock hierarchy receives the outputs from the disabling means at the next lower level of the clock distribution hierarchy at its inputs.
The said disabling means for a particular level of the clock hierarchy receives the output from the identifying means at the same level of the clock hierarchy.
The present invention further provides in a programmable logic device containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising:
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to
"The said identifying means is a logic circuit that receives the select / deselect
signal for each synchronous sequential logic block as an input and provides a defined logic signal when all its inputs are in the deselected state.
The said disabling means in a logic circuit for gating the clock signal to said synchronous sequential logic blocks.
The clock distribution is arranged in a hierarchical structure and an identifying means and a disabling means is provided for each level of clock hierarchy.
The said identifying means for a higher level of the clock hierarchy receives the outputs from the disabling means at the next lower level of the clock distribution hierarchy at its inputs. The said disabling means for a particular level of the clock hierarchy receives the output from the identifying means at the same level of the clock hierarchy. The present invention also provides a method for reducing power consumption in an electronic circuit containing one or more digital synchronous sequential logic blocks at least one or which is either selected or deselected during operation, comprising the steps of:
identifying the select / deselect state of each deselectable logic block, and disabling the clock input to each deselected logic block.
The select / deselect state of each deselectable logic block is determined by monitoring its select / deselect control signal.

'The clock input to each deselected logic block is disabled by gating it with a control signal
The above method is applied to a hierarchical clock distribution arrangement wherein the identification and disabling is implemented for each level of the clock hierarchy.
The disabling for a particular level of the clock hierarchy is based on the monitoring of the disabling signals for the lower levels of the clock hierarchy.
Brief Description of Drawings:
The invention will now be described with reference to the accompanying drawings.
Fig 1 shows a block diagram of a conventional programmable logic block (PLB) using sequential elements (flip flops/latch).
Fig 2 shows a conventional clock tree using buffers (or inverters).
Fig 3 shows an example of a hierarchical clock tree in a programmable logic device.
Fig 4 shows an implementation of the invention in a PLB.
Fig 5 shows the invention as applied to a hierarchical cluster of PLBs.
Fig 6 shows application of the invention to a clock tree.

"Fig 7 shows another implementation of the invention for a clock tree
Fig 8 shows a scheme for implementation of the invention using the switch matrix of an FPGA.
Detailed description of the drawings
Figure 1 shows the block diagram of a Programmable Logic Block (PLB) 30, of the type used in an FPGA, according to the prior art. The PLB contains one or more Look Up Tables (LUTs) 31 that define programmable Combinational logic functions. The output of each LUT is connected to a Flip Flop / Latch 32-32a. All the latches in a PLB share a common clock signal Clk 33-33a. Various combinational or sequential logic functions can be obtained by programming the LUT suitably and selecting either the latched output or the combinational signal at the input of the latch.
Figure 2 shows a typical clock tree structure 10, according to prior art, used for supplying the clock signal to the PLBs. External clock Clk 14 supplied to the entire device is buffered by buffer 12 and then distributed by first level distribution buffers 13a to 13d. Each first level distribution buffer in turn supplies the clock signal to second level distribution buffers that supply the clock signal 16a to 16d to a set of PLBs 11.
Figure 3 shows an implementation of a conventional clock tree in a programmable logic device 52 such as an FPGA. Clock pin 53 of the device receives the clock signal 51 from an external source. First level buffer 54 supplies the clock signal to second level buffers 55a to 55d. The output of each second level buffer 56a to 56d drives a set of third level buffers 57a to 57d. Each third level buffer supplies the clock to a PLB 60. Often only some of the PLBs 60 utilize sequential elements for desired functions while other PLBs 58
do not utilize sequential element. The clock supplied to these PLBs with unused sequential elements remains active thereby resulting in unnecessary power dissipation in these PLBs.
Figure 4 is a block diagram of a programmable logic block 68 of an FPGA according to the present invention. A programmable logic block 68 consists of a number of Look Up Table (LUT) 61 with an equal number of sequential elements (flip flops/latches) 65 each of which is associated with a LUT 61. Each LUT 61 has N inputs 71 and one output 62. The output 62 can be connected to the external routing channel directly or after registering by a sequential element 65. This selective connection is implemented by a configurable multiplexer 63, which selects the final output 64 for external routing. Multiplexer 63 is controlled by configurable element output SI 72. If select signal SI 72 for multiplexer is "0" then logic element output 61 is connected to final output 64 while if select signal SI 72 is "1" then the registered output is selected for final output 64. hi other words, select signal S1 72 is" 1" when a sequential function is required while it is "0" when only combinatorial output is desired. If all the sequential elements in a PLB are not used then all the respective select signals SI to Sn are "0". Connecting the select signal 72 to a control logic (here simply an OR gate) 67 provides a control output 69 that can be used to gate the clock tree output to the PLB.
Figure 5 is a block diagram for implementing the invention in a hierarchy of programmable logic blocks. A cluster 75 of 'n' programmable logic block 68 according to the present invention receives a common block signal CLKP1 85. Each programmable logic block receives T inputs 82 and generates 'P' outputs 81. At the same time, each programmable logic block also generates a control signal "Ol" to "On" 83 that is "0" if no sequential element 65 is used in that programmable logic block 68 and is a "1" if at least one sequential element is
used. The control signals "Ol" to On" are connected to control logic 76 that enables/disables clock signals CLKPl 85 for the entire cluster. If all the control signals "Ol" to "On" are "0", it implies that none of the PLBs uses any sequential elements and the control logic 76 therefore disables the CLKPl signal by outputting a "0" as "EN" 77.
Figure 6 shows a clock tree 100 according to the present invention for reducing the power consumption in an FPGA device. A clock signal 102 supplied to the clock input is first buffered by buffer 101 and then distributed by a tree using control gates 103 and buffers 104. At the first level these control gates 103 are controlled by individual enable signals EN1 to ENn 77 that enable or disable individual branches of the clock tree. If signal EN1 77 is inactive, it disables clock signal CLKPl, which in turn disables clock signals CLK1 to CLKn at the leaves of that branch. The enable signals are generated by the clock control logic in the PLB cluster of the associated branch as described in figure 5. Similarly enable signals Ol to On to On 69 control the gate to enable or disable individual branches of the clock signals CLK1 to CLKn 66. The enable signals are generated by the clock control logic in the PLB of the associated branch as described in
figure 4.
Figure 7 shows another arrangement for controlling a clock tree 100 using tri-state buffer 110 instead of control gates. The enable signals EN1 to ENn controls the enable/disables inputs of the associated tri-state buffers. These enable signals are generated by the clock control logic in the PLB cluster of the associated branch as described in figure 5. Similarly, control signals Ol to On control the enable/ disable inputs of the tri-state buffers at the final level (leaves) of the clock tree. These enable signals are generated by the clock control logic in the PLB of the associated branch as described in figure 4.
Figure 8 shows the implementation of the control signal generation circuitry for a PLB 168 in an FPGA using the programmable switch matrix of the FPGA. The output of each flip flop 163 as well as the output from the LUT 162 are brought out to the programmable switch matrix where these are selectively connected to the routing matrix by control switches SI to Sn. The control signals for these switches SI to Sn are also connected to control element 167 for generating the control output 69.
The programmable array may also include blocks made of sequential elements other than PLB e.g. I/O blocks for accepting the clock signals from clock distribution networks.

Claims:

1. In an electronic circuit containing one or more digital synchronous
sequential logic blocks at least one of which is either selected or
deselected during operation, an improved clock distribution scheme that
reduces power consumption, comprising:
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.
2. An electronic circuit as claimed in claim 1 wherein said identifying
means is a logic circuit that receives the select / deselect signal for each
synchronous sequential logic block as an input and provides a defined
logic signal when all its inputs are in the deselected state.
3. An electronic circuit as claimed in claim 1 wherein said disabling means
in a logic circuit for gating the clock signal to said synchronous
sequential logic blocks.
4. An electronic circuit as claimed in claim 1 wherein the clock distribution
is arranged in a hierarchical structure and an identifying means and a
disabling means is provided for each level of clock hierarchy.
5. An electronic circuit as claimed in claim 4 wherein said identifying
means for a higher level of the clock hierarchy receives the outputs from
the disabling means at the next lower level of the clock distribution
hierarchy at its inputs.
6. An electronic circuit as claimed in claim 4 wherein said disabling means
jr.
for a particular level of the clock hierarchy receives the output from the
identifying means at the same level of the clock hierarchy.
7. In a programmable logic device containing one or more digital
synchronous sequential logic blocks at least one of which is either
selected or deselected during operation, an improved clock distribution
scheme that reduces power consumption, comprising:
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.
8. A programmable logic device as claimed in claim 7 wherein said
identifying means is a logic circuit that receives the select / deselect
signal for each synchronous sequential logic block as an input and
provides a defined logic signal when all its inputs are in the deselected
state.
9. A programmable logic device as claimed in claim 7 wherein said
disabling means in a logic circuit for gating the clock signal to said
synchronous sequential logic blocks.
10. A programmable logic device as claimed in claim 7 wherein the clock
distribution is arranged in a hierarchical structure and an identifying
means and a disabling means is provided for each level of clock
hierarchy.
11. A programmable logic device as claimed in claim 10 wherein said
identifying means for a higher level of the clock hierarchy receives the
outputs from the disabling means at the next lower level of the clock
distribution hierarchy at its inputs.
12. A programmable logic device as claimed in claim 10 wherein said
disabling means for a particular level of the clock hierarchy receives the
output from the identifying means at the same level of the clock
hierarchy.
13. In a programmable gate array (PGA) containing one or more digital
synchronous sequential logic blocks at least one of which is either
selected or deselected during operation, an improved clock distribution
scheme that reduces power consumption, comprising:
identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.
14. A programmable gate array (PGA) as claimed in claim 13 wherein said
identifying means is a logic circuit that receives the select / deselect
signal for each synchronous sequential logic block as an input and
provides a defined logic signal when all its inputs are in the deselected
state.
15. A programmable gate array (PGA) as claimed in claim 13 wherein said
disabling means in a logic circuit for gating the clock signal to said
synchronous sequential logic blocks.
16. A programmable gate array (PGA) as claimed in claim 13 wherein the
clock distribution is arranged in a hierarchical structure and an identifying
means and a disabling means is provided for each level of clock
hierarchy.
17. A programmable gate array (PGA) as claimed in claim 16 wherein said
identifying means for a higher level of the clock hierarchy receives the
outputs from the disabling means at the next lower level of the clock
distribution hierarchy at its inputs.
18. A programmable gate array (PGA) as claimed in claim 16 wherein said
disabling means for a particular level of the clock hierarchy receives the
output from the identifying means at the same level of the clock
hierarchy.
19. A method for reducing power consumption in an electronic circuit
containing one or more digital synchronous sequential logic blocks at
least one or which is either selected or deselected during operation,
comprising the steps of:
identifying the select / deselect state of each deselectable logic
block, and
disabling the clock input to each deselected logic block.
20. A method as claimed in claim 19 wherein the select / deselect state of
each deselectable logic block is determined by monitoring its select /
deselect control signal.
21. A method as claimed in claim 19 wherein the clock input to each
deselected logic block is disabled by gating it with a control signal
22. A method as claimed in claim 19 applied to a hierarchical clock
distribution arrangement wherein the identification and disabling is
implemented for each level of the clock hierarchy.
23. A method as claimed in claim 22 wherein the disabling for a particular
level of the clock hierarchy is based on the monitoring of the disabling
signals for the lower levels of the clock hierarchy.
24. An electronic circuit substantially as herein described with reference to
and as illustrated in the accompanying drawings.
25. A programmable logic device substantially as herein described with
reference to and as illustrated in the accompanying drawings.
26. A programmable gate array (PGA) substantially as herein described with
reference to and as illustrated in the accompanying drawings.
27. A method for reducing power consumption in an electronic circuit
substantially as herein described with reference to and as illustrated in the
accompanying drawings.