Field of the Invention
The present invention relates in general to a Content Addressable Memory circuit and in particular to a low power Content Addressable Memory circuit.
Background of the Invention
A Content Addressable Memory (CAM) gets its name from the fact that a data word in CAM is selected or identified by its contents rather than by its physical address. CAM is a memory that can be instructed to compare a sequence of reference or comparand data with data stored in the CAM array. The entire CAM array is searched for indicating a match with the comparand data. CAMs are used in a variety of applications as sorting large databases, pattern-matching for image processing & voice recognition and in the cache memory systems of high speed computing systems. They are becoming increasingly popular in high-speed network routers and many other applications known in the art of computing.
The design of a standard CAM comprises an array of individual CAM cells configured into rows and columns. Typically, each CAM cell can store a single bit of data during a write operation and compare that stored bit with a comparand or reference bit during a search or comparison operation, which determines if the stored bit and the reference bit match. The CAM therefore comprises of a Data Storage circuit and a Comparison Circuit. In existing implementation of a CAM circuit each row represents a different word of n bits, wherein n being the number of columns in CAM array. During the comparison operation, if each of the reference bits of the data word matches with the corresponding bit of the stored word, a data match status is achieved. An indicator commonly known as Match Line (ML) is associated with each stored word for indicating data match or mismatch in the content addressable memory circuit which can be further detected by a sense amplifier or any other sensing means connected to each Match Line. The output of all the match line sense amplifiers is fed to a priority encoder. The priority encoder then prioritizes the matching locations (if more than one match was found) and
generates the corresponding address of the highest priority matching location, which can be used further to select data from rows of some additional memory.
It is known in the art that results of the comparison of multiple cells of a row in an CAM array are combined in several ways, each having different advantages and disadvantages.
In an existing implementation, a NAND configuration is used, wherein the match line driver devices (pass transistors) of all the cells belonging to a word are connected in series. This NAND configuration will consume less power but will inherently be slower than desirable especially in wide CAMs and in modern deep-sub micron processes where supply voltage is descending.
In another existing implementation, a NOR configuration is used for speed-oriented CAMs, wherein the match line driver devices (pass transistors) of all the cells corresponding to a specific data word are connected in parallel to pull down the initially precharged (at logical "High") Match Line during the search operation. With this NOR configuration, a match for a word occurs whenever no cell of the row is driving Match Line low. Thus, this NOR configuration is faster than the NAND configuration but consumes considerably large power.
The bit search operation of a CAM cell will now be described with reference to the Figures 1 and 2. Hereafter in the specification, logical "1" refers to logical "High" and a voltage VDD (Supply voltage), while logical "0" refers to a logical "Low" and a zero potential (Ground potential).
Figure 1 illustrates a prior art 9-transistor CAM cell 100 having a NOR configuration. The CAM cell 100 comprises a SRAM cell for data storage that includes a pair of cross-coupled inverters formed by transistors 111, 112, 113 and 114 and a pair of access transistors 115,116. The comparison circuitry of the CAM cell 100 comprises a pair of pass transistors 117,118. In particular the P-channel transistor 113 and N-channel transistor 111 are connected in series between a supply voltage (VDD) and ground
(GND) and have gates coupled to a node between transistors 114 and 112. P-channel transistor 114 and N-channel transistor 112 are connected in series between a supply voltage VDD and ground GND but have gates coupled to a node between transistors 113 and 111. N-channel pass transistors 115 and 116 connect the cross coupled inverters to the bit lines BLT and BLF and a word line WL couples to the gates of pass transistors 115 and 116. The N-channel transistors 117 and 118 are connected in scries between bit lines BLT and BLF and the common node is labeled as Bit-Match node. The gates of transistors 117 and 118 are coupled to nodes F and T, respectively. N-channel pass transistor 119 is coupled between Match Line ML and ground GND and its gate is connected to Bit-Match node of the CAM cell.
The Read and Write operations of this CAM cell 100 are exactly similar to those of a standard 6-transistor SRAM cell, wherein the precharge state of bit lines BLT & BLF is logical "High".
During the Search operation, bit lines BLT & BLF are initially precharged to logical "Low" and Match Line (ML) is precharged to logical "High". The comparand bit is then placed on BLT and its complementary bit is placed on BLF. Now if the comparand bit matches with the data bit stored in the CAM cell, then one of the N-channel pass transistors 117 or 118 drives the Bit-Match node to logical "0" and therefore ML remains at logical "High", indicating a match. On the other hand, if there is a mismatch between the applied comparand bit and the data bit stored in the CAM cell, then one of the N-channel pass transistors 117 or 118 drives the Bit-Match node to "VDD-Vtn", thereby switching on the N-channel pull-down transistor 119. Thus transistor 119 pulls down the Match Line thus indicating a mismatch.
The CAM cell 100 thus requires a precharge to logical "Low" operation for bit lines and precharge to logical "High" operation for ML when a Search operation is requested if the default standby state is for a READ or a WRITE operation. Conversely, if the CAM cell 100 is ready for a search operation in its default standby state, then the bit lines must be precharged to logical "High" and ML is thereby discharged when a READ or WRITE
operation is requested. The bit lines and Match Line impose a heavy capacitive load on their drivers and prechargers. The CAM cell 100 thus consumes more power and provides larger READ/WRITE/ SEARCH access times.
Figure 2 illustrates another prior art 9-transistor CAM cell 200 with NOR configuration. The difference between the CAM cell 200 and 100 is using a P-channel transistor 219 rather than N-channel discharge transistor 119. This configuration solves the problem of keeping the precharge low during search operation. The discharge through P-channel transistor is slow and it therefore increases the search access time. In addition the Match Line is discharged from VDD to Vtp, where Vtp is the threshold voltage of the P-channel discharging transistor 219. Further, the discharging of Match Line to the P-channel threshold consumes large power.
Thus, a requirement is felt for a CAM cell implementation, which overcomes the above stated limitations of conventional CAM design and offers a CAM circuit with high speed sensing of the bit match or mismatch condition and has low power consumption.
Object and Summary of the Invention
It is an object of the present invention to provide a low power consumption CAM circuit.
It is another object of the present invention to provide high-speed detection of the match line transition.
To achieve said objectives the present invention provides a low power content
addressable memory circuit comprising:
a storage means having a predetermined data stored is coupled to an input signal at its first input and to inverted response of said input signal at its second input for effectuating the comparison between the input signal and said predetermined data,
a comparison enabling means connected to the output of said storage means and receiving said input signal at its first input and its inverted response at its second input. - a searching means connected to a higher supply voltage at its first input and a control signal at its second input for initializing searching data from said storage means,
a match or mismatch detection means receiving response from said searching means at its first terminal, connected to the output of said comparison means at its second terminal and connected to a lower supply voltage at its third terminal;
a match line precharged to higher supply voltage is coupled to the common node of said searching means and match-mismatch detection means for providing bit match or mismatch signal at its output, and a sense amplifier is connected to said match line for detecting the signal transition at said match line to thereby detect bit match or mismatch condition, characterized in that,
said match or mismatch detection means being disconnected from the lower supply voltage.
a reference line precharged to zero potential is connected between said match-mismatch detection means and said sense amplifier for detecting transition of said match line and reference line, and
a controlled potential generation means connected to said control signal at its input, connected to a lower voltage supply at its first output and connected to the third terminal of said match or mismatch detection means at its second output for enabling charge sharing between the match line and said reference line to thereby provide high speed bit match or mismatch detection and to minimize power consumption.
Further, the present invention provides a method for minimizing power consumption in a content addressable memory, comprising steps of:
precharging the match line to higher supply voltage and the reference line
to zero potential,
initializing the bit search signal for providing controlled potential to the
match line and reference line,
maintaining the match line at higher supply voltage and reference line at
zero potential; and
enabling charge sharing between the match line and the reference line to
thereby enable high speed detection of a bit match or mismatch condition
and minimize power consumption.
Thus, the present invention provides a low power-CAM cell circuit and maintains high speed of bit match and mismatch operation by providing improved sensing of the match line and reference line transition.
Brief Description of the Accompanying Drawings
The present invention will now be described with reference to and as illustrated by the accompanying drawings.
Figure 1 illustrates a prior art CAM circuit.
Figure 2 illustrates another prior art CAM circuit.
Figure 3 illustrates the low power CAM circuit in accordance with the instant invention.
Figure 4 illustrates a conventional sense amplifier circuit for detecting the match-mismatch condition in the CAM circuit.
Figure 5 illustrates another conventional sense amplifier circuit used for detecting the match-mismatch condition in the CAM circuit.
Figure 6 illustrates the simulation results of the CAM circuit in accordance with the instant invention.
Figure 7 illustrates the Monte Carlo analysis of the CAM circuit in accordance with the instant invention.
Detailed Description of the Drawings
Figures 1 & 2 have been described under the heading Background of the Invention.
Figure 3 illustrates the low power CAM circuit in accordance with the instant invention. The low power CAM circuit comprises the search control circuit 350. In the precharge state SEARCH signal is kept low, thus, the MATCH LINE is precharged to the supply voltage and the REFERENCE LINE is discharged to the ground potential. When search operation is requested SEARCH goes high, thus transistors 320 and 322 are switched off and REFERENCE LINE and MATCH LINE start floating. In the case of a bit match transistor 319 remains off and the MATCH LINE and REFERENCE LINE remain at the supply voltage and ground potential respectively. In the case of mismatch, transistor 319 turns on, that results in charge sharing between the MATCH LINE and the REFERENCE LINE. As a result, the MATCH LINE starts discharging and REFERENCE LINE starts charging. A sense amplifier is used to detect the charging and discharging and produces results of bit match or mismatch at higher speed. Logic inverter 321 and transistor 322 provide a controlled potential to the MATCH LINE and REFERENCE LINE by adjusting the capacitance of these lines, for achieving desirable charge sharing for low power high speed CAM circuit.
Figure 4 shows a conventional sense amplifier, which can be used for detecting the transition of MATCH LINE and REFERENCE LINE of the low power CAM circuit. Transistor 413 is sized higher than the transistor 414. Transistors 411, 412, 415 and 416 are feedback transistors and transistor 417 is the enable transistor. Inverters 418, 419 and transistors 420 and 423 provide feedback and further improve the sensing. In the case of bit match condition, the MATCH LINE remains at power supply voltage and
REFERENCE LINE remains at ground voltage that causes a logic high on SENSE ENABLE. Transistor 414 discharges faster than the transistor 413, and output node OUT ~ of the sense transistor starts discharging. Similarly, transistor 424 is sized higher than the transistor 423 and the output of the sense amplifier OUT starts charging which enhances the operation of the sense amplifier. Performance of the sense amplifier is further improved by the feedback provided by the inverters 418 and 419 and p-channel transistors 420 and 421. In the case of mismatch, transistor 413 drives lower than the transistor 414 and transistor 424 drives lower than 423. Consequently logic level is passed at the output of the sense amplifier.
Figure 5 shows another conventional circuit of sense amplifier, which can be used for detecting the transition of MATCH LINE and REFERENCE LINE. The circuit operates in a similar manner as the above stated circuit and the constructional difference in the circuit is the series connection of transistor 524 in with 511 and series connection of transistor 523 with 512.
Figure 6 shows the simulation results of the circuit of the present invention using sense amplifier of figure 4. Curve 1 designates the match line and curve 2 designates the reference line. Curve 3 shows the latched data after detection by the sense amplifier and curve 4 shows the search enable signal. In case of bit mismatch, discharging of match line and charging of the ground line can be seen in the figure. It is observed that since the swing of these signals is small, a significant reduction in power dissipation is achieved in this case.
Figure 7 shows the Monte Carlo simulation results of the circuit of the present invention using the sense amplifier shown in Figure 5. Curve 1 shows discharging of the match line, Curve 2 shows the charging of the ground line and Curve 3 shows the latched data after detection from the sense amplifier. It is observed from the simulation results that the data is accurately latched by the sense amplifier.

We claim:
1. A low power content addressable memory circuit comprising:
a storage means having a predetermined data stored is coupled to an input signal at its first input and to inverted response of said input signal at its second input for effectuating the comparison between the input signal and said predetermined data,
a comparison enabling means connected to the output of said storage means and receiving said input signal at its first input and its inverted response at its second input,
a searching means connected to a higher supply voltage at its first input and a control signal at its second input for initializing searching data from said storage means,
a match or mismatch detection means receiving response from said searching means at its first terminal, connected to the output of said comparison means at its second terminal and connected to a lower supply voltage at its third terminal;
a match line precharged to higher supply voltage is coupled to the common node of said searching means and match-mismatch detection means for providing bit match or mismatch signal at its output, and a sense amplifier is connected to said match line for detecting the signal transition at said match line to thereby detect bit match or mismatch condition, characterized in that,
said match or mismatch detection means being disconnected from the lower supply voltage,
a reference line precharged to zero potential is connected between said match-mismatch detection means and said sense amplifier for detecting transition of said match line and reference line, and
a controlled potential generation means connected to said control signal at its input, connected to a lower voltage supply at its first output and connected to the third terminal of said match or mismatch detection means at its second
output for enabling charge sharing between the match line and said reference line to thereby provide high speed bit match or mismatch detection and to minimize power consumption.
2. A low power content addressable memory as claimed in claim 1, wherein said
storage means comprising at least two inversion means cross coupled to each
other and connected between a first transistor and a second transistor; said first
and second transistors connected to said input signal and its inverted response
respectively.
3. A low power content addressable memory as claimed in claim 1, wherein said comparison enabling means comprising at least two transistors connected between said input signal and the inverted response; said transistors connected to the output of said storage means at their control inputs.
4. A low power content addressable memory as claimed in claim 1, wherein said searching means is a transistor.
5. A low power content addressable memory as claimed in claim 1, wherein said match or mismatch detection means is a transistor.
6. A low power content addressable memory as claimed in claim 1, wherein said controlled potential generation means comprising:
a signal inversion means connected to said control signal at its input, and a charge sharing enabling means receiving the output of said signal inversion means is connected to a lower voltage supply at its first output and is connected to the third terminal of said match or mismatch detection means at its second output.
7. A low power content addressable memory as claimed in claim 1, wherein said
sense amplifier is a latch sense amplifier.
8. A low power content addressable memory circuit as claimed in claim 8. wherein
said latch sense amplifier comprising:
a plurality of cross coupled transistors connected between a higher voltage supply and a sense enable transistor for enabling precision latching of signals from match line and reference line,
a signal equalization transistor coupled to the gate input of said sense enable transistor for providing complimentary output signals to said plurality of cross coupled transistors,
said match line is connected at the input node of said plurality of cross coupled transistors for providing a first control signal to enable high speed match and mismatch detection,
a first device is connected to first output node of said sense amplifier and coupled to a lower supply voltage at its gate for providing a first controlled potential to said plurality of cross coupled transistors,
a second device is connected between said first device and higher supply voltage and a second logic inverter is connected to said first output node and gate input of said second device for providing feedback response to said first and second device.
a third device is connected to second output node of said plurality of transistors and receiving said reference line at its gate for enhancing high speed match and mismatch detection, and - a fourth device is connected between said first device and higher supply voltage and a first logic inverter is connected between said second output node and gate of said third device for providing feedback response to said third and fourth device.
9. A method for minimizing power consumption in a content addressable memory
circuit, comprising steps of:
precharging the match line to higher supply voltage and the reference line
to zero potential,
initializing the bit search signal for providing controlled potential to the
match line and reference line,
maintaining the match line at higher supply voltage and reference line at
zero potential; and
enabling charge sharing between the match line and the reference line to
thereby enable high speed detection of a bit match or mismatch condition
and minimize power consumption.
10. A low power content addressable memory circuit substantially as herein described with reference to and accompanying drawings.
11. A method for minimizing power consumption in content addressable memory substantially as herein described with reference to and as illustrated by accompanying drawings.