Field of the Invention
e invention relates to a memory with reduced bitline leakage current and the method for the same.
Background of the Invention
Precharge mechanism is commonly used in static memory architectures these days. For instance, in most high-speed Static Read Access Memory (SRAM) architecture, both the bitlines of the memory are initially precharged to the high voltage level. While reading a location in the memory, one of the wordlines correponding to the location is selected enabling the access transistor and connecting the bitline to a memory cell . Memory cell storing a low voltage dischrages the bitline producing current on the bitline in the process. Based on the current or voltage output of the memory cell, it is sensed by the sense amplifier as a low value stored in the memory.
Figure 1 shows circuitry for a bit in a conventional memory structure. The circuitry comprises bitlines BIT and BITBAR, memory cells with aceess transistors and wordlines associated with each memory cell. The two access transistors are coupled to each memory cell on one end and to the common bitlines BIT and BITBAR repectively on the other end. The gate node of access transistor is coupled to the associated wordline. While reading one wordline is selected and other wordlines are connected to ground through the wordline drivers. Bitline connected to low node discharges through the pull down of selected memory cell while bitline bar is held high. Problem with such setup may arise when memory cells other than the one selected in the column have opposite data value written in them. In this situation, bitline bar discharges through the leakage in the access transistors of these cells, worst case is when all other cell of column are having opposite data. This may result in erroneous detection of the stored data by the sense amplifier.
As the technology is shrinking, the leakage current in the access transistors has become a prime concern. The leakage current has become of same order as the current of the devices. The increased leakage current can be attributed to increase in the subthreshold current as technology has moved to deep-sub micron regime. At high temperature, problem is even more severe and
has become a bottleneck for fast and reliable operation of data sensing.The worst case is when one cell is read and opposite of this cell data is stored in all other cell in the column.
There are some solutions for reducing leakage current such as use of high threshold transistor, stack access for memory cell but all these either need modified process or reduce speed due to two access in series. These techniques also result in bigger chip area. Hence there is need for memory with reduced bitline leakage current. At the same time, there is also need for memories that provide reduced complexity and silicon area.There is also need for a memory architecture that do not result in reduced memory speed as a result of leakage current reduction.
Object and Summary of the Invention
To obviate the aforesaid drawbacks the object of the instant invention is to provide a memory with reduced bitline leakage.
Further object of the instant invention is to provide a method for reducing bitline leakage current in the memory cells.
Yet another object of the invention is to reduce bitline leakage current in th memory cell without significantly increasing the chip area.
Yet another object of the invention is to provide reduced cell and manufacturing complexity in memories with reduced bitline leakage current.
To meet the aforementioned objectives a memory with reduced bitline leakage current comprising:
a plurality of bitlines;
a plurality of wordlines;
a plurality of access transistors with each of said access transistors coupled to one of said
wordlines at its control terminal and connected to one of said bitlines at its output
terminal;
a plurality of memory cells with each output of said memory cells coupled to an input
terminal of one of said access transistors so that the acess transistors coupled to the
outputs from one of said memory cells share one of said wordlines and are coupled to
different said bitlines;
a wordline driver coupled to each said wordline with ability of generating variable
voltage at its output responsive to wordline driver control inputs and voltage at its ground
supply node;
a plurality of grouped voltage supply lines coupled to a group of said wordline drivers for
inducing a variable ground supply at said ground supply node; and
a voltage switching logic for switching voltage for said variable ground supply
responsive to a ground control input.
Further the invention provides a method for reducing bitline leakage current in a memory comprising the steps of:
storing data in memory cells of said memory;
coupling each output of said memory cells to an access transistor;
connecting outputs of said access transistors to a plurality of bitlines so that the access
transistors coupled to the outputs from one of said memory cells share a wordline at their
control terminals and are coupled to different said bitlines at their output;
generating a variable ground supply voltage using a plurality of voltage supply lines and
a voltage switching logic responsive to ground control input;
connecting said variable ground supply voltage to a wordline driver for generating a
variable output for each said wordline driver responsive to wordline driver control inputs;
and
reducing bitline leakage current for said memory cells by connecting said variable output
to the wordline of an access transistor.
To achieve the objective the present invention provides a memory with reduced leakage currents in memory cells. The invention further provides method of reducing bitline leakage in memory. The invention provides more split at sense amplifier node and hence more speed is given.A
negative voltage is generated and applied to the access transistors of unselected wordlines which reduces subthreshold leakage.
Brief Description of The Accompanying Drawings
The invention will now be described with reference to and as illustrated in the accompanying drawings.
Figure 1 illustrates the prior art SRAM architecture.
Figure 2 shows an embodiment of the memory in accordance with the instant invention.
Figure 3 shows the wordline driver in accordance with the instant invention.
Figure 4 shows another embodiment of the memory architecture in accordance with the instant invention.
Figure 5 shows the simulation results for the prior memory architecture.
Figure 6 shows the simulation results for the memory in accordance with the instant invention
Description of the Invention
The present invention proposes that while one memory Cell is read, the gate voltage at access transistors of other memory cells coupled to the same bitline is made negative. This is achieved by two independent means which are mutually exclusive but can be combined to have a cumulative advantage. These are:
i) Negative voltage generation due to channel Charge Injection, and ii) Generating negative voltage at the ground line of the wordline driver by coupling effect.
In above mentioned techniques wordline driver has separate ground supply from other circuitry and memory cell arrays. Further, a Capacitor can also be provided at the ground line of Wordline driver in a similar fashion as used in figure 1 with the pull down transistor of the wordline drivers.
The invention thus uses tristate wordline driver, a MOS connected as capacitor to increase negative voltage generation at the wordline in the circuit of tristate wordline driver. It includes a switch connected to ground for Wordline drivers and generates negative voltage by inducing coupling in the ground line of Wordline drivers when not selected. It utilizes minimum distance supply line to induce coupling and capacitor at switch ground line to increase the negative charge at ground line of driver and separate ground line for Wordline drivers.
Figure 3 illustrates the wordline driver which comprises PMOS transistors Mil, and NMOS transitors Ml 2 and Ml3. The source of Ml 1 is connected to supply Vdd, drain is connected to output terminal WL and the gate of Ml 1 is controlled by signal PEN. The source of M12 is connected to ground voltage supply, drain is connected to the output terminal WL and the gate is controlled by signal NEN. NMOS transistor Ml3 is connected as a capacitor between NEN and WL. Its drain and source are shorted and are connected to the output terminal WL. The substrate of transistor Ml 3 is also connected to WL while the gate is coupled to the NEN signal.
As soon as any memory cell is selected, the NEN of the associated wordline driver is made low. PEN of the wordline to be activated is also made low, activating the desired wordline to the high value. For all other drivers, output terminal WL is tristated and has some negative charge due to the channel charge injection. As soon as NEN is put low, channel charge of transistor M12 is distributed between ground line and unselected wordline. Since capacitance of wordline is very low as compared to that of the ground line most of the negative charge is distributed to the wordline. Capacitor connected NMOS M13 further boosts this effect by transferring all of its channel charge to the wordline only. The substrate of this capacitor is also connected to WL terminal to transfer all the charge to wordline.
Figure 2 comprises of Memory Cell Array 21, Wordline Drivers 22, NMOS transistor M23, supply line 24 .The source of M23 is connected to the ground supply, drain is connected to all the wordline drivers. The ground supply to all the wordline drivers is provided by NMOS switch, gate of NMOS M23 is controlled by GNDEN signal.Supply line 24 consist of three parallel lines laid out at minimum distance to have maximum coupling between the lines. Middle wire is ground line which is surrounded by two wires connected to vdd. When a memory cell is not selected, corresponding GNDEN signal is high providing proper ground to wordline driver of the memory cell. When a memory cell is selected GNDEN is made low, thereby tristating the ground line at the same time switching the surrounding lines from high to low. This switching of surrounding lines generates negative voltage at the ground line which in turn is passed to the unselected wordline.
To have maximum speed advantage with minimum area increase, negative voltage can be created seperatley for the ground line across the memory cells. The negative voltage can be fed on a group of memory cells where selected memory cell exists. On the other hand, the unselected memory cells can be provided with normal ground.
Figure 4 shows addition of NMOS M34 connected as a capacitor. Gate is connected to GNDEN, and drain, source, and bulk is connected to the ground line of wordline drivers. When GNDEN is made low negative charge will be generated at ground line due to capacitor M23.
To verify the architecture, an array of 512 Rows and 16 column is taken. Proper value of RC is added in the path of the wordline as well as ground line to driver. Worst case for leakage consideration if made by reading a high vlaue from one of the memory cells while other 511 cells in the column have a low value stored in them. In prior art, ground line of wordline drivers is not switched off during inactive cycles and while reading all other wordlines are at ground level. The architecture uses following:
Driver Size : Pull-up (PMOS) w= le-06 1=0.1 e-06
Pull-down (NMOS) w=0.5e-06 1=0.le-06 Supply Voltage 1.0v
Temperature 125 °C
Process 90NM (TSMC, Typical)
Ground Line : C= 131.12 fF R=181.184 0hm
Wordline :C=3.12fF R=4.32 Ohm
As shown in figure 5 bitline corresponding to high held node is severely affected by the currentleakage.
Figure 6 illustrates the results for present invention. Architecture uses the following:
Driver Size : Pull-up (PMOS) w= le-06 1=0.1 e-06
Pull-down (NMOS) w=0.5e-06 1=0.le-06
Capacitor (NMOS) w=0.4 e-06 1= 0.12 e-06
Supply Voltage l.Ov
Temperature 125 °C
Process 90NM (TSMC, Typical)
Ground Line :C= 131.12 fF R=181.184 0hm
Wordline :C=3.12fF R=4.32 Ohm
Two lines are laid out at minimum distance with ground line. As shown, the effect of leakage current is highly reduced. Negative charge is generated at wordline and ground of wordline driver.
It is believed that the present invention and many of its attendant advantages will be understood by the foregoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The fonn herein before described being merely an exemplary embodiment thereof, it is the intention of the following claims to encompass and include such changes.

We claim:
1. A memory with reduced bitline leakage current comprising:
- a plurality of bitlines;
a plurality of wordlines;
a plurality of access transistors with each of said access transistors coupled to one
of said wordlines at its control terminal and connected to one of said bitlines at its
output terminal;
a plurality of memory cells with each output of said memory cells coupled to an
input terminal of one of said access transistors so that the acess transistors
coupled to the outputs from one of said memory cells share one of said wordlines
and are coupled to different said bitlines;
a wordline driver coupled to each said wordline with ability of generating variable
voltage at its output responsive to wordline driver control inputs and voltage at its
ground supply node;
a plurality of grouped voltage supply lines coupled to a group of said wordline
drivers for inducing a variable ground supply at said ground supply node; and
- a voltage switching logic for switching voltage for said variable ground supply
responsive to a ground control input.
2. A memory with reduced bitline leakage current as claimed in claim 1 wherein said
wordline driver comprising:
a first N-type transitor having its first terminal coupled to the ground supply node,
its second terminal coupled to the output of said wordline driver and its control
terminal coupled to first of said wordline driver control inputs;
a first P-type transitor having its first terminal coupled to a high supply voltage,
its second terminal coupled to output of said wordline driver and its control
terminal coupled to second of said wordline driver control inputs: and
a first capacitor connected N-type transistor with its first and second terminals
coupled to the output of said wordline driver and its control terminal coupled to
first of said wordline driver control inputs.
A memory with reduced bitline leakage current as claimed in claim 1 wherein said grouped voltage supply lines comprises three parallel supply lines with outer of said supply lines coupled to the output of said voltage switching logic and middle one of said supply lines connecting to the ground supply node of said wordline drivers.
A memory with reduced bitline leakage current as claimed in claim 1 wherein said voltage switching logic comprising:
a second N-type transistor having its first terminal coupled to a ground voltage
supply, its second terminal connected to said ground supply node, and its control
terminal coupled to said ground control input; and
a set of series connected inverters for connecting said ground control input to
output of said voltage switching logic.
A memory with reduced bitline leakage current as claimed in claim 4 wherein said voltage switching logic comprising a second capacitor connected N-type transistor with its control terminal coupled to said ground control input and its first and second terminals coupled to said ground supply node.
A memory with reduced bitline leakage current as claimed in claim 1, wherein said bitlines coupled to said memory cells group of wordline drivers
A memory with reduced bitline leakage current as claimed in claim 3 wherein said supply lines in said grouped voltage supply lines are at a minimal distance to induce coupling effect between said supply lines.
A memory with reduced bitline leakage current as claimed in claim 1 wherein said access transistors are NMOS devices.
A memory with reduced bitline leakage current as preceeding claims wherein said transistors are MOS devices.
10. Method for reducing bitline leakage cunent in a memory comprising the steps of:
storing data in memory cells of said memory; coupling each output of said memory cells to an access transistor; - connecting outputs of said access transistors to a plurality of bitlines so that the access transistors coupled to the outputs from one of said memory cells share a wordline at their control terminals and are coupled to different said bitlines at their output;
generating a variable ground supply voltage using a plurality of voltage supply lines and a voltage switching logic responsive to ground control input: connecting said variable ground supply voltage to a wordline driver for generating a variable output for each said wordline driver responsive to wordline driver control inputs; and
reducing bitline leakage current for said memory cells by connecting said variable output to the wordline of an access transistor.
11. A memory with reduced bitline leakage current substantially as herein described with refernece to and as illustrated in the accompanygin drawings.
12. Method for reducing bitline leakage current in a memory substantially as herein described with refernece to and as illustrated in the accompanygin drawings.