Abstract: A method for feeding DC power to an amplifier module for a pulsed load (3), eg an antenna array, comprising the steps of - providing current pulses (6) from a DC power supply (1); - charging a capacitor configuration (4) in the amplifier module; - providing an output voltage (Uout) via a voltage regulated power supply; and - feeding current pulses (2) to said load from said capacitor configuration. The method is especially characterized by the further steps of - determining an output current (lout) pulse (2) configuration appearing during feeding the load from said configuration (4); - providing a pulsed input current (lin) from said DC power supply (1) based upon the determined output pulsed current; - limiting the maximum current level (61) of the input current pulses (6) to a predetermined level by, inter alia, a control and pulse shaping circuit (8) to be substantially lower compared to the peak current (2'} of said output current pulses (2). The present invention also relates to a device for feeding DC power. (Fig.1)
A METHOD AND A DEVICE FOR FEEDING DC POWER TO AN AMPLIFIER MODULE FOR A PULSED LOAD
BACKGROUND Technical field
The present invention relates to a method according to the introductory portion of the attached claim 1.
The invention also relates to a device according to the introductory part of the attached claim 9.
Prior art
Feeding of DC power to multiple amplifier modules in antenna arrays consisting of several elements is difficult especially when there are large variations in the current consumption, as is the case in a pulsed radar application.
A common implementation is feeding the voltage via a voltage regulated power supply to the pulsed load.
Previously known techniques of substantially the kind described, offers problems in the form of high levels of current ripple on the feeding power lines due to the pulsed current. Further, the pulsed current with extensive rise and fall during short time periods, causes EMI to other parts of the system. Still further, the power supply need to be designed to handle the peak current load.
OBJECT OF THE INVENTION
The object of the present invention is to provide a solution to the problems described above by providing, inter alia, a reduced EMI disturbance and reduced DC power supply current rating as far as peak currents are concerned.
SUMMARY OF THE INVENTION
This and other objects of the invention are obtained by means of a method and a device according to the attached claims 1 and 9, respectively.
Further advantages are obtained by means of what is stated in the respective dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention should be had based upon the following detailed description read in conjunction with the attached drawings, wherein
- Fig. 1 schematically shows a block diagram over a first embodiment of a current/
voltage regulator configuration according to the present invention; and
- Fig. 2 schematically shows a simulation of the input and output current, and out
put voltage in a regulation configuration according to Fig. 1.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
In Fig. 1 a DC power supply 1 is arranged for providing DC power for output current pulses 2 to a pulsed load 3. 4 designates a capacitor configuration or capacitor bank for energy storage, the capacitor configuration being arranged for feeding current pulses 2 to said load 3.
An output voltage Uout is provided via a current/voltage regulator configuration 5 between the DC power supply 1 and the load 3.
The energy of the output current pulses 2 fed to the load, ie required by the load, corresponds substantially to the energy of the input current pulses 6 provided from the DC power supply 1, a slight difference, however, appearing due to minor en-
ergy losses in the current/voltage regulator configuration 5. The energy of the output pulses is determined and, thus, known.
As discussed above the output current pulses 2 have an unfavourable maximum current level and shape, the rise and fall times being extremely short for many applications.
The current/voltage regulator configuration 5 is arranged to modify the input current pulses 6, the maximum current level 6' being limited to a pre-determined level and the rise and fall times of the current pulses preferably being controlled so that the rise and fall times are longer than irv the case of the output current pulses to the load, as will be further discussed in relation to Fig. 2.
The current/voltage regulator configuration 5 according to the present invention comprises a current sense arrangement 7, a control and pulse shaping circuit 8, a pass device 9, a voltage reference arrangement 10 and a voltage sense arrangement 11, the current/voltage regulator configuration being arranged to provide an output voltage Uout from the DC power supply for charging the capacitor configuration to provide energy for start-up and successive output current pulses 2 as required by the load. Preferably, the circuit has a slow voltage regulation loop so that a stable step response without over-shoot is obtained.
In Fig. 1 the capacitor configuration 4 has been shown as associated with the load
In more detail the current sense arrangement 7 comprises a modified current mirror arrangement cooperating with eg a power transistor of the pass device 9 and a differential amplifier arrangement of the control and pulse shaping circuit 8, the pass device being controlled to act as a variable resistance to limit the maximum current level 6' and the current mirror comprising a capacitor arrangement for controlling the rise and fall times of the input current pulses 6.
The voltage sense comprises means for regulation against a nominal output voltage by means of a feed-back reference voltage differential amplifier configuration.
Fig. 2 shows, as an example, plots from a simulation showing input and output current and output voltage behaviour vs time of the current/voltage regulator configuration during successive charging and discharging of the capacitor configuration and successive input current pulses from the power supply and successive output current pufses to the load from the capacitor configuration.
In the example the input voltage Ujn is + 41 V, the voltage reference +10 V, the nominal output voltage +36 V, the maximum current level 2' of the output current pulses 2 10 A and the maximum current level of the input current 2 A.
The upper plot in Fig. 2 shows the output voltage vs time with short-/high repetition rate pulses in the left part, and long-/low repetition rate pulses to the right.
The lower plot in Fig. 2 .show both the input- and output current vs time. In the left part 50 pulses of a high frequency pulse load current, short duration pulses with high repetition rate are shown, and in the right part 3 pulses of a lower frequency pulse load current, long pulses with low repetition rate are shown.
For the high repetition rate pulses in the left part, the chosen pulse length is short, and the duty cycle too low for limiting the input current. Therefore the circuit keeps regulating the output voltage, while the input current stays constant, until the high repetition rate pulses ends, and the input current drops to zero.
For the long pulses, to the right, the output voltage drops during each pulse and after a delay the input current limiter turns on to charge the output capacitor back to nominal output voltage.
Thus, energy for short 10 A output current pulses 2 discharged to the load is provided by input current pulses 6 from the power supply, the input pulses 6 being controlled and shaped by the current/voltage regulator configuration so that, in the example, the maximum current level 6' is about 2 A and the rise and fall times of the pulses 6 are much longer than those of the output current pulses 2.
The characteristics of the current/voltage regulator configuration may be controlled and amended with respect to eg output voltage, maximum current level and rise and fall times by means of choice of the discrete components, ie resistances, capacitors, transistors etc.
The method and the function of the device according to the present invention should to a considerable and sufficient extent have been made clear to a person skilled in the art from the detailed description given above.
The invention offers several advantages compared to prior art. Thus, the predetermined limited maximum, current level makes it possible to make the DC power supply 1 smaller since it does not have to be designed/dimensioned to handle the peak current pulses of the load/output current. In the given example, the reduction in load- to input current is about 5:1.
Further, the shaped input pulses with longer rise and fall times reduces EMI to other parts of the system or the corresponding.
The characteristics of the current/voltage regulator configuration may easily be amended by changing discrete components.
Above the present invention has been described in conjunction with examples and preferred embodiments;
However, further embodiments as well as minor additions and amendments may be imagined without departing from the basic inventive idea.
Thus, the invention is suitable for feeding DC power to multiple amplifier modules in antenna arrays comprising several elements, such as in pulsed radar applications. However, the invention is suitable also for other applications, especially applications characterized by extensive variations as far as pulsed current consumption is concerned.
When it comes to the detailed design of, primarily, the current/voltage regulation configuration there are a number of possible solutions, specific component characteristics etc.
Thus, the inventions should not be considered to be limited to the embodiments disclosed but can be varied within the scope of the attached claims.
CLAIMS
1. A method for feeding DC power to an amplifier module for a pulsed load, eg an
antenna array, comprising the steps of
- providing current pulses from a DC power supply;
- charging a capacitor configuration in the amplifier module;
- providing an output voltage via a voltage regulated power supply; and
- feeding current pulses to said load from said capacitor configuration,
characterized by the further steps of
- determining an output current (lout) pulse (2) configuration appearing during feed
ing the load from said configuration (4);
- providing a pulsed input current (lin) from said DC power supply (1) based upon
the determined output pulsed current;
- limiting the maximum current level (6') of the input current pulses (6) to a pre
determined level by, inter alia, a control and pulse shaping circuit (8) to be sub
stantially lower compared to the peak current (2') of said output current pulses (2).
2. A method according to claim 2, characterized by the further step of
- controlling the shape of the input current pulses (6) for extending the rise and fall
times of the input current pulses compared to the rise and fall times of the output
current pulses (2).
3. A method according to claim 1 or 2, characterized in that
the energy of the output current pulses substantially correspond to the energy of
the input current pulses from said DC power supply.
4. A method according to claim 1, 2 or 3, characterized by the step of sensing a
momentary voltage difference by a momentary voltage difference sensing configu
ration (7) during creation of the input current pulses for charging said capacitor
configuration.
5. A method according to claim 1, 2, 3 or 4, characterized by the step of
- regulating against a nominal output voltage (Uout) during capacitor configuration
charging by means of feed-back to a reference voltage amplifier configuration (8,
10,11).
6. A method according to anyone of claims 1-5, characterized by the steps of
providing a differential amplifier arrangement and a modified current mirror for
voltage regulation.
7. A method according to anyone of claims 1-6, characterized by the step of
- controlling a pass device (9) power transistor operation for limiting the maximum
input current (lin) level (6').
8. A method according to anyone of claims 2-7, characterized in the step of
- providing a capacitor arrangement in a current modified mirror for reducing rise
and fall times of the input current pulses (6).
9. A device for feeding DC power to an amplifier module for a pulsed load, eg an
antenna array, comprising a DC power supply for DC current pulse supply, a ca
pacitor configuration arranged in the module arranged to be charged, the capaci
tor configuration being arranged for feeding a pulsed current to a pulsed load, an
output voltage being provided via a voltage regulated power supply,
characterized in means (5) for providing a pulsed input current (lin) from said DC power supply (1) based upon a determined current (lout) pulse (2) configuration appearing during feeding the pulsed load (3) from said capacitor configuration (4) and in means (5) for limiting the maximum current level (6') of the input current (lin) pulses (6) to a pre-determined level (6') by, inter alia, a control and pulse shaping circuit (8) to be, preferably substantially, lower compared to a peak (2') current of said determined current pulse (2) configuration.
10. A device according to claim 9, characterized in that the control and pulse
shaping circuit (8) comprises means for controlling the shape of the input current
pulses (6) for extending the rise and fall times of the input current pulses com
pared to the rise and fall times of the output current pulses (2).
11. A device according to claim 9 or 10, characterized in that the energy of the
output current pulses.(2) substantially corresponds to the energy of the input
pulses (6) from said DC power supply.
12. A device according to claim 9,10 or 11, characterized in a momentary volt
age difference sensing configuration (7) for sensing a momentary voltage differ
ence during creation of the input current pulses for charging said capacitor con
figuration.
13. A device according to claim 9,10, 11 or 12, characterized in means (5) for
regulation against a nominal output voltage (Uout) during capacitor configuration
charging by means of a slow voltage regulator circuit.
14. A device according to claim 9, 10,11, 12 or 13, characterized in a differential
arrangement and a modified current mirror.
15. A device according to claim 9,10,11,12,13 or 14, characterized in an ar
rangement (5) comprising a power transistor and means for controlling the opera
tion of the same by limiting the maximum input current level (6').
16. A device according to anyone of claims 9-15, characterized in a capacitor arrangement in a modified current mirror for controlling the rise and fall times of the input current pulses.
| # | Name | Date |
|---|---|---|
| 1 | 373-DEL-2009-AbandonedLetter.pdf | 2019-10-14 |
| 1 | 373-DEL-2009-Form-3-(24-08-2009).pdf | 2009-08-24 |
| 2 | 373-DEL-2009-Certified Copy of Priority Document (MANDATORY) [03-09-2018(online)].pdf | 2018-09-03 |
| 2 | 373-DEL-2009-Correspondence-Others-(24-08-2009).pdf | 2009-08-24 |
| 3 | abstract.jpg | 2011-08-21 |
| 3 | 373-DEL-2009-FER.pdf | 2018-07-26 |
| 4 | 373-del-2009-form-5.pdf | 2011-08-21 |
| 4 | 373-del-2009-Correspondence Others-(07-11-2012).pdf | 2012-11-07 |
| 5 | 373-del-2009-form-3.pdf | 2011-08-21 |
| 5 | 373-del-2009-Form-3-(07-11-2012).pdf | 2012-11-07 |
| 6 | 373-del-2009-form-2.pdf | 2011-08-21 |
| 6 | 373-del-2009-Correspondence Others-(09-01-2012).pdf | 2012-01-09 |
| 7 | 373-del-2009-Form-18-(09-01-2012).pdf | 2012-01-09 |
| 7 | 373-del-2009-form-1.pdf | 2011-08-21 |
| 8 | 373-del-2009-drawings.pdf | 2011-08-21 |
| 8 | 373-del-2009-abstract.pdf | 2011-08-21 |
| 9 | 373-del-2009-claims.pdf | 2011-08-21 |
| 9 | 373-del-2009-description (complete).pdf | 2011-08-21 |
| 10 | 373-del-2009-correspondence-others.pdf | 2011-08-21 |
| 11 | 373-del-2009-claims.pdf | 2011-08-21 |
| 11 | 373-del-2009-description (complete).pdf | 2011-08-21 |
| 12 | 373-del-2009-abstract.pdf | 2011-08-21 |
| 12 | 373-del-2009-drawings.pdf | 2011-08-21 |
| 13 | 373-del-2009-form-1.pdf | 2011-08-21 |
| 13 | 373-del-2009-Form-18-(09-01-2012).pdf | 2012-01-09 |
| 14 | 373-del-2009-Correspondence Others-(09-01-2012).pdf | 2012-01-09 |
| 14 | 373-del-2009-form-2.pdf | 2011-08-21 |
| 15 | 373-del-2009-Form-3-(07-11-2012).pdf | 2012-11-07 |
| 15 | 373-del-2009-form-3.pdf | 2011-08-21 |
| 16 | 373-del-2009-Correspondence Others-(07-11-2012).pdf | 2012-11-07 |
| 16 | 373-del-2009-form-5.pdf | 2011-08-21 |
| 17 | 373-DEL-2009-FER.pdf | 2018-07-26 |
| 17 | abstract.jpg | 2011-08-21 |
| 18 | 373-DEL-2009-Certified Copy of Priority Document (MANDATORY) [03-09-2018(online)].pdf | 2018-09-03 |
| 18 | 373-DEL-2009-Correspondence-Others-(24-08-2009).pdf | 2009-08-24 |
| 19 | 373-DEL-2009-Form-3-(24-08-2009).pdf | 2009-08-24 |
| 19 | 373-DEL-2009-AbandonedLetter.pdf | 2019-10-14 |
| 1 | SearchStrategy373-DEL-2009_20-07-2018.pdf |