Claims:1. An apparatus for executing instruction matrices, comprising:
a memory to store a plurality of instruction matrices; and
a plurality of matrices of execution units to execute the plurality of instruction matrices, wherein each of the plurality of instruction matrices includes rows and columns, wherein instructions in a same row of an instruction matrix are to be executed in parallel and instructions that are dependent upon instructions in a row of an instruction matrix are in a subsequent row of the instruction matrix, wherein the plurality of matrices of execution units is configurable to operate in different execution modes including a first execution mode, a second execution mode, and a third execution mode,
wherein in the first execution mode, the plurality of matrices of execution units simultaneously executes a group of instruction matrices that form a super instruction matrix,
wherein in the second execution mode, the plurality of matrices of execution units simultaneously executes instructions matrices belonging to separate threads, and
wherein in the third execution mode, the plurality of matrices of execution units simultaneously executes non-dependent instruction matrices from a single thread.
, Description:A method of processing computer instructions, comprising: forming multiple instruction matrices, wherein each instruction matrix specifies parallel and dependent instructions; and executing the multiple instruction matrices simultaneously in multiple execution units within a fixed number of cycles, wherein each execution unit supports both parallel and serial instruction execution.