A) TECHNICAL FIELD

[0001] The present invention generally relates to a radio frequency link aggregation for metro Ethernet solution and particularly relates to a method and system for aggregating multiple speed data channels. The present invention more particularly relates to a method and system for aggregating radio frequency communication links and implementation in FPGA for utilizing the bandwidth to fullest extent possible with low delay variation.

B) BACKGROUND OF THE INVENTION

[0002] Ethernet is a technology which supports variable frame size [64 to 9616 in the current design] and can have multiple link speeds based on the auto-negotiation [10/100/1000 or 10G]. There are various technologies proposed such as 802.3ad and multilink PPP for aggregating the links for additional bandwidth, but each have their own drawbacks and issues. The 802.3ad may underutilize few links while expecting links to work at same speed, while multilink PPP has extra delay in processing, needing buffering of data at both ends and possible additional Packet delay Variation (PDV).

[0003] One of the existing prior arts provides an IEEE 802.3ad for implementing link aggregation. In this method a rule-set is used to decide a link to be used for next frame. Though the logic is simple, in most cases, the bandwidth gets unused in a few links while other links may get overloaded resulting in a frame loss.

[0004] Further, detection and changing of the partner links becomes very difficult and needs software intervention. So there is a huge frame loss in case of losing a link.

[0005] Another existing prior art provide a Multilink PPP implementation for link aggregation. This implementation needs a huge memory to buffer the incoming data to re-sequence, which may result in additional delay in a frame transmission. With most TCP connections resorting to a retransmit mode within couple of milliseconds, a network can potentially get filled with retransmitted frames in case of errors (link error and others). This issue will become more complex if the partner links are of different speeds.

[0006] Hence, there is a need to provide a method and system for aggregating the radio frequency communication links and implementing the same in FPGA. There is also need for a method and system for implementing the supports link aggregation over the multiple links of different speeds, with a maximum possible link utilization of up to 95% of aggregate bandwidth, for addressing a condition where the links may go down/up due to the environmental conditions, addressing partial link losses, low PDV and handling small buffering requirement. C) OBJECT OF THE INVENTION

[0007] The primary object of the present invention is to provide a method and system for aggregating the radio frequency communication links and implementing the same in FPGA.

[0008] Another object of the present invention is to provide a method and system for aggregating the data channels with multiple speeds.

[0009] Yet another object of the present invention is to provide a method and system for utilizing the bandwidth to the maximum extent possible with a low delay variation.

[0010] Yet another object of the present invention is to provide a system and method for detecting link state, link speeds and adjusting the data rate across with minimal loss and maximum bandwidth utilization.

[0011] Yet another object of the present invention is to provide a system and method for handling a support link loss and partial link failures with a minimal data loss.

[0012] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

D) SUMMARY OF THE INVENTION

[0013] The various embodiments of the present invention provide a method and system for aggregating the radio frequency communication links and implementing in FPGA. The method for aggregating radio frequency communication links and implementing in FPGA device comprises the steps of fragmenting a frame into a plurality of fragments before transmitting, adding a RFLAG header, adding a frame check sequence (FCS) for each fragmented frame, and the FCS is added at the end for matching Ethernet standards, scheduling a data to a RF link using a link rate of each partner, and a number of

fragments added in a high speed link is more than a number of fragments added to a low speed link, sending a pause frame from a downstream device to throttle a data rate, managing the credits to the link using a data rate matching logic, and the data rate matching logic manages the credits are managed based on a data rate, received pause frames and errors, receiving the fragmented frames at a receiving end, verifying the received fragmented frames to check whether the received fragmented frames are within a preset range or not, and wherein the received fragmented frames that are out of range and the received fragmented frames with error in Frame Check Sequence (FCS) are dropped, storing a data in the fragmented frames in an internal storage in FPGA using a sequence number, and the internal storage in FPGA is a BlockRAM, sharing the BlockRAM among a plurality of groups supporting variable link speeds, reading the fragmented frames one by one by a reading logic as soon as the received and stored fragmented frames are available for a reading operation and handling packet overflows and packet delays.

[0014] According to an embodiment of the present invention, an algorithm based computation is adopted to decide whether the next fragmented frame is to be read or not. The algorithm based computation is adopted to handle the packet overflows and packet delays.

[0015] According to an embodiment of the present invention, the RFLAG header comprises a sequence number, a plurality of flags and switchover related information. The RFLAG header is 4 byte RFLAG header. The plurality of flags comprises Sof/Eof flags and link information flags.

[0016] According to an embodiment of the present invention, the receive processing logic waits for a programmable pre-determined time interval or the threshold of the receive buffer when the next fragment is not available. The reading logic skips to a next available fragment after programmable pre¬determined time interval or the threshold of the receive buffer.

[0017] According to an embodiment of the present invention, the frames in which one or more fragments are skipped are marked as bad FCS to upper layers.

[0018] The various embodiments of the present invention provide a system for aggregating radio frequency communication links and implementing in FPGA. The system comprises a fragmentation block for fragmenting a frame into a plurality of fragments before transmitting, a data rate matching module comprising one or more data rate matching logics for managing credits to the link, and the credits are managed based on data rate, pauses frames and errors received, a link detection module comprising one or more link detection logics for detecting a partial link_down [one direction down] condition and a full linkdown [both direction down] condition, a partial fading detection module for detecting a partial fading on the link, a mis-configuration detection module for detecting a mis-configuration condition and generating a mis-configuration alarm, a frame validation checking module for checking a validation of a frame and a reassembly module comprising one or more logics for reassembling a plurality of fragments.

[0019] According to an embodiment of the present invention, the link detection module comprises a transmit block and a receive block. The transmit block sends a link detection frame with a preset size at a pre-defined time interval when no data is available for sending, and the pre-defined time interval is 1 millisecond, and the predetermined size is 64 bytes. The transmit block transmits a link detect related flags along with the frame header when a data is available for transmission, and wherein the frame header is RFLAG header, and wherein the transmit block stops a transmission of the data packets on the affected link on reception of Remote Defect Indication (RDI) or link_down condition.

[0020] According to an embodiment of the present invention, the link detection module comprises a receive logic. The receive logic detects a linkdown condition to send a remote defect indication (RDI) in the transmit direction, when the receive linkupdate fails for more than a preset time interval. The receive logic sends out remote defect indication (RDI) in the transmit direction until the link becomes correct, and the preset time is 3 milliseconds.

[0021] According to an embodiment of the present invention, the partial fading detection module comprises one or more logics for detecting severely error seconds [SES] with threshold and identifying continuous errors beyond a specified time period. The partial fading detection module comprises one or more logics for identifying a link_down period based on consecutive 5 SES (if 15 link frames are lost within 100 ms then that second is declared as SES) and declares as down. The logic declares link is UP when it receives link frames for more than 4 NON-SES intervals. The logic of the partial fading detection module does not transmit any data on the link with down status.

[0022] According to an embodiment of the present invention, the mis-configuration detection module comprises one or more logic for transmitting at-least 1 identifiers at every 1 second. Identifiers comprise a Group identifier and a Link identifier, each of 4 bytes in length.

[0023] According to an embodiment of the present invention, the values of the Group identifier and the Link identifier are compared and verified against the programmed values. The logic raises the mis-configuration alarm when there is a mismatch between the values of the received Group identifier and the Link identifier and the programmed values.

[0024] According to an embodiment of the present invention, the system for aggregating radio frequency communication links and implementing it in FPGA comprises fast reset logic and a second logic for rapid switchover. This is done to implement the switchover time within 50 msec. The fast reset logic resets the sequence window to start, and purges the buffer when all the links in the group are in a link down condition with Remote Defect Indication (RDI) with time to repair or react (TTR) state. The second logic for rapid switchover detects a change of card from a slave to master to latch to the next sequence number coming from the remote node to maintain sync between the nodes to get a quick recovery by reducing the fragment loss due to out of order reception. The second logic transmits a flag called 'S' Bit when the card in slave. The second logic transmits the flag 'S' Bit for only 50 milliseconds when the card is master. The second logic blanks a reception to avoid the confusion created by both in slave mode condition when the first'S' bit is received.

E) BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0026] FIG. 1 illustrates a system for aggregating radio frequency communication links and implementing the same in FPGA, according to an embodiment of the present invention.

[0027] FIG. 2 illustrates a flow chart explaining a method for aggregating radio frequency communication links and implementing the same in FPGA, according to an embodiment of the present invention.

[0028] Although the specific features of the present invention are shown in some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention.

F) DETAILED DESCRIPTION OF THE INVENTION

[0029] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that the logical, mechanical and other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.

[0030] FIG. 1 illustrates a system for aggregating radio frequency communication links and implementing the same in FPGA, according to an embodiment of the present invention. The system comprises a fragmentation block 102 for fragmenting a frame 101 into a plurality of fragments (101a, 101b, 101c and lOln) before transmitting over a plurality of links (104a, 104b, 104c and 104n). A data rate matching module 103 comprises one or more data rate matching logics for managing credits to the link, and the credits are managed based on data rate, pause frames and errors received. A link detection module 108 comprises one or more link detection logics for detecting a partial linkdown condition and a full linkdown condition. A partial fading detection module is provided for detecting a partial fading on the link. A mis-configuration detection module 109 is arranged for detecting a mis-configuration condition and generating a mis-configuration alarm. A frame validation checking module 106 is provided for checking a validation of a frame. A reassembly module 107 comprises one or more logics for reassembling a plurality of fragments (101a, 101b, 101c and lOln).

[0031] According to an embodiment of the present invention, the fragmentation block 102 fragments the frame 101 into the plurality of fragments (101a, 101b, 101c and lOln) of size 128 / 256 bytes. Further, the last fragment lOln is of size 128/256 + upto 60 bytes to avoid padding.

[0032] According to an embodiment of the present invention, a RFLAG header is added to each of the plurality of fragments. The RFLAG header is of 4 byte. The RFLAG header includes a sequence number (i.e. up to 16 bits), Sof/Eof flags, link information flags and switchover related information. The addition of RFLAG header provides maximum utilization of bandwidth. In 14xxN setup, it reaches 95% of the total aggregate bandwidth at all possible link speed combinations.

[0033] According to an embodiment of the present invention, a Frame Check Sequence (FCS) for each of the plurality of the fragments (101a, 101b, 101c and lOln) is added at the end to match Ethernet standard. Each partner link's rate is used for scheduling the data to the link. Faster link gets more fragments while slower link gets fewer fragments. The data in the fragment is stored in a small BlockRAM (FPGA internal storage) using the sequence number. The BlockRAM of the memory is shared among all the groups supported on the design platform. More links requires more memory, similarly less links requires less memory. On an average 32KB min or 128KB max memory per group is provided to support variable link speeds (data rate of link speed is in ratio 8:1).

[0034] According to an embodiment of the present invention, the link detection module 108 comprises a transmit block and a receive block. The transmit block sends a link detection frame with a preset size at a pre-defined time interval when no data is available for sending, and the pre-defined time interval is 1 millisecond, and the predetermined size is 64 bytes. The transmit block transmits a link detect related flags along with the frame header when a

data is available for transmission, and wherein the frame header is RFLAG header, and wherein the transmit block stops a transmission of data packets on the affected link on reception of RDI or link_down condition.

[0035] According to an embodiment of the present invention, the link detection module 108 comprises a receive logic. The receive logic detects a link_down condition to send a remote defect indication (RDI) in the transmit direction, when the receive linkupdate fails for more than a preset time interval. The receive logic sends out remote defect indication (RDI) in the transmit direction until the link becomes correct, and the preset time is 3 milliseconds.

[0036] According to an embodiment of the present invention, the partial fading detection module 109 comprises one or more logics for detecting severely error seconds [SES] with threshold and identifying continuous errors beyond a specified time period. The partial fading detection module 109 comprises one or more logics for identifying a link_down period based on consecutive 3 SES and declares as down. The logic declares "link is UP" when the link receives good link frames for more than 3 intervals. The logic of the partial fading detection module 109 does not transmit any data on the link with down status, but link detect frames are transmitted continuously.

[0037] According to an embodiment of the present invention, the mis-configuration detection module 105 comprises one or more logic for transmitting at-least one identifies at every 1 second. Identifies comprises a Group identifier and a Link identifier, and the Group identifier and the Link identifier are of 4 bytes in length.

[0038] According to an embodiment of the present invention, the values of the Group identifier and the Link identifier are compared and verified against the programmed values. The logic raises the mis- configuration alarm when there is a mismatch between the values of the Group identifier and the Link identifier and the programmed values.

[0039] According to an embodiment of the present invention, the system for aggregating the radio frequency communication links and implementing in FPGA comprises fast reset logic and a second logic for rapid switchover. The fast reset logic resets the sequence window to start and purges the buffer when all the links in the group are in RDI state or link down. The second logic for rapid switchover detects a change of card from a slave to master to latch to the next sequence number coming from the remote node to maintain sync between the nodes to get a quick recovery by reducing the fragment loss due to out of order reception. The second logic transmits a flag called 'S' Bit when the card in slave. The second logic transmits the flag 'S' Bit for only 50 milliseconds when the card is master. The second logic blanks a reception to avoid the confusion created by both in slave mode condition when the first'S' bit is received.

[0040] FIG. 2 illustrates a flow chart explaining a method for aggregating radio frequency communication links and implementing the same in FPGA, according to an embodiment of the present invention. The method for aggregating the radio frequency communication links and implementing in FPGA device comprises the steps of fragmenting a frame into a plurality of fragments before transmitting (Step 201). A RFLAG header is added to the fragmented frame (Step 202). A frame check sequence (FCS) is added for each fragmented frame (Step 203). The FCS is added at the end for matching the Ethernet standards and a data is scheduled to a RF link using a link rate of each partner (Step 204). When a number of fragments added in a high speed link is more than a number of fragments added to a low speed link, a pause frame is sent from a downstream device to throttle a data rate (Step 205). The credits to the link are managed or controlled or adjusted using a data rate matching logic (Step 206). The data rate matching logic manages the credits based on a data rate, received pause frames and errors. The fragmented frames are received at a receiving end (Step 207). The received fragmented frames are verified to check whether the received fragmented frames are within a preset range or not (Step 208). The received fragmented frames that are out of range and the received fragmented frames with error in FCS are dropped. The data in the fragmented frames are stored in an internal storage in FPGA using a sequence number. The internal storage in FPGA is a BlockRAM (Step 209). The BlockRAM is shared among a plurality of groups supporting variable link speeds (Step 210). The fragmented frames are read one by one by receive processing logic as soon as the received and stored fragmented frames are available for a reading operation (Step 211). In parallel a process of handling packet overflow condition and excess packet delays are performed using an algorithm (Step 212).

[0041] According to an embodiment of the present invention, an algorithm based computation is adopted to decide whether the next fragmented frame is to be read or not. The algorithm based computation is adopted to handle the packet overflows and packet delays.

[0042] According to an embodiment of the present invention, the RFLAG header comprises a sequence number, a plurality of flags and switchover related information. The RFLAG header is 4 byte RFLAG header. The plurality of flags comprises Sof/Eof flags and link information flags.

[0043] According to an embodiment of the present invention, the reading logic waits for a pre-determined time interval when the next fragment is not available. The reading logic skips to a next available fragment after pre¬determined time interval.

[0044] According to an embodiment of the present invention, the frames in which one or more fragments are skipped are marked as bad FCS to upper layers.

[0045] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.

G) ADVANTAGES OF THE INVENTION

[0046] The various embodiment of the present invention provide a system and method for aggregating the radio frequency communication links and implementing the same in FPGA. The method and system supports link aggregation over multiple links of different speeds.

[0047] The method and system utilizes maximum possible link i.e. up to 95% of aggregate bandwidth. The method and system further handles a condition when links goes down/up due to environmental conditions.

[0048] The method and system support link loss handling and partial link failures with minimal data loss (i.e. under 50 milliseconds). The method and system also handles Low Packet delay variation (PDV) and buffering requirement.

[0049] Although the embodiments herein are described with various specific embodiments, it will be obvious for a person skilled in the art to practice the disclosure with modifications. However, all such modifications are deemed to be within the scope of the claims.

[0050] It is also to be understood that the following claims are intended to cover all of the generic and specific features of the embodiments described herein and all the statements of the scope of the embodiments which as a matter of language might be said to fall there between.

CLAIMS

What is claimed is:

1. A method for aggregating radio frequency communication links and implementing in FPGA device, the method comprising:

fragmenting a frame into a plurality of fragments before transmitting;

adding a RFLAG header, and wherein the RFLAG header comprises a sequence number, a plurality of flags and a switchover related information, and wherein the RFLAG header is 4 byte RFLAG header, and wherein the plurality of flags comprises Sof/Eof flags and link information flags;

adding a frame check sequence (FCS) for each fragmented frame, and wherein the FCS is added at the end for matching Ethernet standards; scheduling a data to a RF link using a link rate of each partner, and wherein a number of fragments added in a high speed link is more than a number of fragments added to a low speed link;

sending a pause frame from a downstream device to throttle a data rate;

managing credits to the link using a data rate matching logic, and wherein the data rate matching logic manages the credits are managed based on a data rate, received pause frames and errors;

receiving the fragmented frames at a receiving end;

verifying the received fragmented frames to check whether the received fragmented frames are within a preset range or not, and wherein the received fragmented frames that are out of range and the received fragmented frames with error in FCS are dropped;

storing a data in the fragmented frames in an internal storage in FPGA using a sequence number, and wherein the internal storage in FPGA is a BlockRAM;

sharing the BlockRAM among a plurality of groups supporting variable link speeds;

reading the fragmented frames one by one by a reading logic as soon as the received and stored fragmented frames are available for a reading operation; and

handling packet overflows and packet delays; wherein an algorithm based computation is adopted to decide whether the next fragmented frame is in sequence or not, and wherein the algorithm based computation is adopted to handle the packet overflows and packet delays.

2. The method according to claim 1, wherein the reading logic waits for a pre-determined time interval when the next fragment is not available, and wherein the reading logic skips to a next available fragment after programmable pre-determined time interval.

3. The method according to claim 1, wherein the frame in which one or more fragments are skipped are marked as bad FCS to upper layers.

4. A system for aggregating radio frequency communication links and implementing in FPGA, the system comprising:

a fragmentation block for fragmenting a frame into a plurality of fragments before transmitting;

a data rate matching module comprising one or more data rate matching logics for managing credits to the link, and wherein, the credits are managed based on data rate, pauses frames and errors received;

a link detection module comprising one or more link detection logics for detecting a partial linkdown condition and a full linkdown condition;

a partial fading detection module for detecting a partial fading on the link;

a mis-configuration detection module for detecting a mis-configuration condition and generating a mis-configuration alarm;

a frame validation checking module for checking a validation of a frame; and

a reassembly module comprising one or more logics for reassembling a plurality of fragments.

5. The system according to claim 4, wherein the link detection module comprises a transmit block and a receive block, and wherein the transmit block sends a link detection frame with a preset size at a pre-defined time interval when no data is available for sending, and wherein the pre-defined time interval is 1 millisecond, and wherein the predetermined size is 64 bytes, and wherein the transmit block transmits a link detect related flags along with the frame header when a data is available for transmission, and wherein the frame header is RFLAG header, and wherein the transmit block stops a transmission of data packets on the affected link on a reception of remote defect indication (RDI) or linkdown condition.

6. The system according to claim 4, wherein the link detection module comprises a receive logic, and wherein the receive logic detects a linkdown condition to send a remote defect indication (RDI) in the transmit direction, when the receive linkupdate fails for more than a preset time interval, and wherein the receive logic sends out remote defect indication (RDI) in the transmit direction until the link becomes correct, and wherein, the preset time is 3 milliseconds unless reconfigured.

7. The system according to claim 4, wherein the partial fading detection module comprises one or more logics for detecting severely error seconds [SES] with threshold and identifying continuous errors beyond a specified time period, and wherein the partial fading detection module comprises one or more logics for identifying a linkdown period based on consecutive 3 SES and declares as down, and wherein the logic declare link is UP when the received 3 consecutive link frames, and wherein the logic of the partial fading detection module does not transmit any data on the link with down status, transmits only link frames.

8. The system according to claim 4, wherein the mis-configuration detection module comprises one or more logic for transmitting at-least one identifies at every 1 second, and wherein the identifies comprises a Group identifier and a Link identifier, and wherein the Group identifier and the Link identifier are of 4 bytes in length.

9. The system according to claim 8, wherein the values of the Group identifier and the Link identifier are compared and verified against the programmed values, and wherein the logics raises the mis-configuration alarm when there is a mismatch between the values of the Group identifier and the Link identifier and the programmed values.

10. The system according to claim 4 further comprises a fast reset logic and a second logic for rapid switchover, and wherein the fast reset logic resets a sequence window to start and purges the buffer when all the link in the group are in RDI(TTR) state of link down, and wherein the second logic for rapid switchover detects a change of card from a slave to master [1+1] to latch to the next sequence number coming from the remote node to maintain sync between the node to get a quick recovery by reducing the fragment loss due to out of order reception, and wherein the second logic transmits a flag called 'S' Bit when the card in slave, and wherein the second logic transmits the flag 'S' Bit for only 50 milliseconds when the card is master, and wherein the second logic blanks a reception to avoid the confusion created by both in slave mode condition when the first'S' bit is received.