Claims:We claim:
1. A method for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices (104 -110n) connected on I2C bus, the method comprising:
communicating, by a master (102), on a known address of the I2C slave devices (104 -110n);
enabling, by an RNG (Random number generator), the I2C slave devices (104 -110n) for updating their address;
assigning, by the master (102), new I2C addresses to the I2C slave devices (104 -110n);
maintaining, by the master (102), a table of all the slave addresses;
scanning, by the master (102), the I2C slave devices (104-110n) to remove a duplicate I2C slave address, and assigning a unique I2C slave address to the one having a duplicate slave address.
2. The method as claimed in claim 1, wherein the new assigned address is distinct from the previously known address.
3. A system for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on I2C Bus, the system comprising:
a master (102) configured to
communicate with the I2C slave devices (104 -110n) on their known address;
assign a new I2C address to the I2C slave devices (104 -110n);
maintain a table of all the slave addresses;
scan the I2C slave devices (104 -110n) to remove a duplicate I2C slave address, and assign a unique I2C slave address to the one having a duplicate slave address; and
an RNG (Random number generator) configured to enable the I2C slave devices (104 -110n) for updating their address.
4. The system as claimed in claim 3, wherein the plurality of the similar I2C slave devices (104 -110n) is connected with the master (102).
5. The system as claimed in claim 3, wherein the plurality of the I2C slave devices (104 -110n) have the same I2C slave address.
6. The system as claimed in claim 3, wherein the I2C slave devices (104 -110n) are connected on same I2C Bus.
7. The system as claimed in claim 3, wherein the table of all the slave addresses is maintained by the master (102) to communicate to the I2C slave devices (104 -110n).
8. The system as claimed in claim 3, wherein the I2C slave devices (104 -110n) are enabled and disabled by (Random number Generator) RNG, where the (Random number Generator) RNG is enabled and disabled by the master (102).
9. The system as claimed in claim 3, wherein the I2C slave devices (104 -110n) are independent of each other and have no physical interface to communicate with each other and the system comprises only one I2C bus interface between the master (102) and the I2C slave devices (104-110n).
10. The system as claimed in claim 3, wherein the unique physical address is assigned to the I2C slave devices (104 -110n) with same I2C slave address, even when standard I2C slaves are attached to the system.
11. The system as claimed in claim 3, wherein if the master (102) identifies that a common address of uninitialized I2C slave devices (104-110n) having the same I2C slave address is possessed by another physical device having hardcoded I2C slave address, then the master is configured to change the common address before starting initialization of the I2C slave devices (104-110n).

Dated this 31st day of March, 2022

Bharat Electronics Limited
(By their Agent)

(D. Manoj Kumar) (IN/PA 2110)
KRISHNA & SAURASTRI ASSOCIATES LLP
, Description:
FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

A METHOD AND SYSTEM FOR DYNAMICALLY ADDRESSING I2C SLAVE DEVICES

BHARAT ELECTRONICS LIMITED
HAVING ITS ADDRESS AT
OUTER RING ROAD, NAGAVARA,
BANGALORE,
KARNATAKA-560045

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
TECHNICAL FIELD
[0001] The present invention relates generally to a system and method for assigning an address to I2C slave devices on a same I2C bus.
BACKGROUND
[0002] I2C (Inter-Integrated Circuit) is a very popular bus protocol used for communication between a master (or multiple masters) and single or multiple slave devices. A number of slave devices can be connected to a master using only 2 wires SCL (clock) and SDA (data) which is one of the largest benefits that the I2C can give when compared to other interfaces.
[0003] The slave requires a unique 7-bit identifier or address to establish communication with I2C master. The problem arises when the master has to control slaves having the same I2C address. In conventional solutions, an extra physical signal is used to enable or disable the device to assign a unique address. But this creates a problem, the number of I2C slave devices having the same I2C address increases, which requires the I2C master to have more number of GPIOs to drive them.
[0004] A conventional technology EP3007387B1 describes a method for dynamic addressing of similar I2C peripherals. All similar I2C slave peripherals are connected with each other serially forming a chain. I2C peripherals are Enabled or disabled with an Independent Signal connected between master and slave. Each slave is having a shift registers which basically holds the slave address which is incremented if they detect a signal addressed to them. This is updated to all other slaves connected serially so every slave holds a unique address after initialization is over. The input of Ist peripheral and output of last peripheral are connected to master forming a chain.

[0005] In another conventional technology, US6629172B1 discloses a method of addressing similar I2C peripherals wherein an external signal is provided to enable or disable the peripherals. Each slave is communicated by enabling the signal addressed to them and masters provide them a unique address. This process continues till all the slaves are initialized with unique I2C address.
[0006] Against this background, it is an object of the present invention to overcome the aforementioned drawbacks and provide a system and method for assigning an address to I2C slave devices.
SUMMARY OF THE INVENTION
[0007] This summary is provided to disclose a method for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on the I2C Bus. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0008] For example, various embodiments herein may include one or more system and method for dynamically assigning address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on same I2C Bus.
[0009] In an embodiment, the present invention describes a system for dynamically assigning address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on I2C Bus. The system comprising a master configured to communicate with the I2C slave devices on their known address. The system further consists of a RNG (Random number generator). The RNG is configured to enable the I2C slave devices for updating their address. The master is further configured to assign new I2C addresses to the I2C slave devices. The master of the present system further maintains a table of all the slave addresses, scans the I2C slave devices to remove a duplicate I2C slave address, and assigns a unique I2C slave address to the one having a duplicate slave address.
[0010] In another embodiment, the present invention describes a method for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on the I2C Bus. The method comprising steps of communicating, by a master, on the known address of the I2C slave devices. The method further comprises the step of enabling, by a RNG (Random number generator), the I2C slave devices for updating their address. In the next step, assigning, by the master, new I2C addresses to the I2C slave devices is disclosed. The method further includes maintaining, by the master, a table of all the slave addresses. The method further includes scanning, by the master, the I2C slave devices to remove a duplicate I2C slave address, and assign a unique I2C slave address to the one having a duplicate slave address.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0011] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0012] Fig. 1 illustrates a block diagram depicting a system for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices, according to an embodiment of the present invention.
[0013] Fig. 2 illustrates a schematic diagram depicting a state machine, according to an embodiment of the present invention.
[0014] Fig. 3 illustrates a schematic diagram depicting initialization of multiple I2C slaves having same I2C address, according to an exemplary implementation of the present invention.
[0015] Fig. 4 illustrates a flow chart of the system for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices, according to an exemplary implementation of the present invention.
[0016] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes that may be substantially represented in a computer-readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0017] The various embodiments of the present invention describe a method for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on the I2C Bus for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on same I2C Bus.
[0018] In the following description, for purpose of explanation, specific details are outlined to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0019] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently disclosure and are meant to avoid obscuring the presently disclosure.
[0020] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0021] In an embodiment, a system for dynamically addressing many I2C Peripherals having the same slave address connected to master on the same I2C Bus is disclosed. The I2C is a two-wire interface used widely because of its simplicity. Many different peripherals use I2C for communication between master and slaves. The limitation of I2C comes when the user wants to address I2C slaves with the same physical addresses. The conventional scheme is using I2C dynamic addressing which calls for extra physical connection in between I2C master – slaves or among slaves. The scheme works fine if slaves connected to the I2C master are less in numbers. In an I2C application, where the number of slaves is comparatively more and unknown but similar, conventional scheming increases the complexity for implementation. A novel method for assigning a unique address to similar I2C slave devices, connected on the same I2C Bus to the I2C master is disclosed. This method implementation works on I2C with Master and Slave firmware/state machine without the requirement of an additional physical connection. This method includes programming of new slave address to each slave, determining the number of similar slaves connected on the bus, and keeping their records for further usage in application.
[0022] In another embodiment, a system for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices connected on an I2C Bus is disclosed. The system consists of a master configured to communicate with the I2C slave devices on their known address. The master further configured to assign new I2C addresses to the I2C slave devices. The master of the system is further configured to maintain a table of all the slave addresses, scan the I2C slave devices to remove a duplicate I2C slave, and assign a unique I2C slave address to the one having a duplicate slave address. The master of the system is further configured to an RNG (Random number generator) configured to enable the I2C slave devices for updating their address.
[0023] In another embodiment, dynamic addressing of I2C peripherals having the same I2C address is disclosed. No additional physical connection is required in the process of Dynamic Addressing. Slaves are independent of each other and have no interface (physical interface) to communicate with each other. Prior knowledge of number of I2C slave peripherals is not required.
[0024] In another embodiment, the method is disclosed where only one I2C bus interface between master and slaves is present. One I2C master is connected to many I2C slave peripherals having same I2C address. All these peripherals are having the same I2C address, to begin with and the address is known to the I2C master.
[0025] Each I2C slave is having a random number generator which enables the device at that particular instance for a duration required by the master for programming the device. Initially, I2C slaves come with a default RNG range. This RNG control is in master hands and can be updated (Enable, disable or change the range).
[0026] In another embodiment, an RNG (Random number generator) generation of the system is disclosed. These random number generates a random number in a range. The RNG gets reset once all the devices on duration has become more than Max duration (Max random number * Duration required to update the address of slave device) because Master does not know the number of I2C slave devices attached it has to wait for full duration.
[0027] In another embodiment Initialization of I2C peripherals having the same I2C address is disclosed. During Initiation Phase Master will scan for standard I2C devices attached to the system if any. This is done by scanning for full address range of I2C slave addresses ie 0 to 127. If found master makes a record that address cannot be assigned to uninitialized slaves.
[0028] In a further step, if the master founds/ identifies that the common address of uninitialized I2C slaves having same address is possessed by another physical device having a hardcoded I2C slave address, then the master changes the common address before starting the initialization.
[0029] In a further step, the master starts initialization by Enabling RNG logic in connected slaves having same I2C address.
[0030] In a further step, the master communicates to slaves with the known I2C slave address.
[0031] In a further step, each slave is enabled based on RNG (Random Number generator).
[0032] The I2C slaves are initialized by the master with an updated slave address and RNG (Random Number Generator) logic will be disabled, Master makes an entry of updated address in the address table maintained by the master.
[0033] Once Max duration (i.e Duration required to update the address of slave device * max random number) is over. Master switches to scan phase.
[0034] In a further step, I2C Master fetches the update slave address table. This table one address can be possessed by multiple slave I2C devices.
[0035] In a further step, the scanning process again starts. The scanning process is done to remove the duplicate I2C slave address present on the slave devices and assign a unique I2C slave address.
[0036] In a further step, the RNG logic is enabled for one of the slave addresses from the table.
[0037] In a further step, the I2C master checks for Acknowledgement for multiple iterations of random number generation on selected addresses from the table to ensure the duplicate I2C slave address are assigned unique I2C slave addresses.
[0038] If only one acknowledgment is coming for multiple iterations of random number generation, it is concluded that there is only one I2C slave device holding the slave address.
[0039] If there is more than one acknowledgment, the master assigns the updated slave address to the slave device and updates the address table.
[0040] In a futher step, the loop continues till all slave addresses from the table are scanned for duplicate slave address.
[0041] In another embodiment, the I2C, a two-wire interface used widely because of its simplicity is disclosed. Many different peripherals use I2C for communication between a master and slaves. The limitation of I2C comes when a user wants to address I2C slaves with a same physical addresses. The conventional scheme is using I2C dynamic addressing which calls for extra physical connection in between I2C master – slaves or among slaves. The scheme works fine if slaves connected to the I2C master are less in numbers. In an I2C application, where the number of slaves is comparatively more and unknown but similar, conventional scheming increases the complexity for implementation. A novel method for assigning a unique address to similar I2C slave devices, connected on the same I2C Bus to the I2C master is disclosed. This method implementation works on I2C with Master and Slave firmware/state machine without the requirement of an additional physical connection. This method includes programming of new slave address to each slave, determining the number of similar slaves connected on the bus and keeping their records for further usage in application.
[0042] In another exemplary implementation, the present invention discloses a method for dynamically assigning unique physical addresses to multiple I2C slave devices having same I2C address, connected on the same I2C Bus, The method comprises steps of:
Master communicating to the I2C slaves using known I2C address,
I2C slaves enabled by Random Number Generator
Master assigning new I2C address to I2C slaves different than previously known I2C address.
Master maintaining a table of slave addresses to communicate to the I2C slave device.
Scanning method to remove duplicate I2C slave address and assign unique I2C slave address.
[0043] In another embodiment, slave devices of the present invention are enabled and disabled by RNG (Random number Generator).
[0044] In another embodiment, the master device of the present invention assigns addresses to slave device. The assigned addresses are unique to the slave device.
[0045] In another embodiment, the master scans a slave address, to remove duplicates and assign a unique address to slave recursively is disclosed.
[0046] In another embodiment, assigning a unique physical address to I2C slaves with same slave address, even when standard I2C slaves are attached to the system is disclosed.
[0047] Fig. 1 illustrates a block diagram (100) depicting a system for dynamically assigning an address to a plurality of similar I2C (inter-integrated circuit) slave devices, according to an embodiment of the present invention.
[0048] The system of the present invention comprises a master (102) and slave devices (104-110n). The master (102) is configured to communicate with the I2C slave devices (104-110n) on their known address. The master (102) further assigns a new I2C addresses to the I2C slave devices (104-110n). The master (102) is further configured to maintain a table of all the slave addresses. The master (102) is further configured to scan to remove a duplicate I2C slave address present on the I2C slave devices (104-110n), and assign a unique I2C slave address to the one having a duplicate slave address. The system of the present invention also provides an dynamic addressing of I2C slave devices (104-110n) having same I2C address. No additional physical connection is required in the process of Dynamic Addressing. The slave devices (104-110n) are independent of each other and have no interface (physical interface) to communicate with each other.
[0049] Fig. 2 illustrates a flow diagram (200) depicting a state machine, according to an embodiment of the present invention.
[0050] Referring now to Fig. 2 which illustrates a flow diagram (200) for communicating master and I2C slave, according to an exemplary implementation of the present invention.
At I2C Master (102) side:
[0051] At step 202, start of address update of all the slave devices on a single bus by I2C master (102) is performed.
[0052] At step 204, the I2C master (102) scans for the standard I2C slave devices (104-110n) with hardcoded slave address, and makes a record of address.
[0053] At step 206, the I2C master (102) enables the RNG on the slave devices (104-110n).
[0054] At step 208, the master (102) sends a known slave address on the bus.
[0055] At step 210, the master (102) further writes an updated address to a slave register.
[0056] At step 212, the master (102) confirms the updated I2C slave address. After confirming, the master (102) makes an entry of the updated address in a table.
[0057] At step 214, the master (102) then disables RNG logic in the slave device.
[0058] At step 216, if the max duration is over then, yes, proceed to the next step.
[0059] At step 218, fetching of the address from the table is done to start to scan the process.
[0060] At step 220, if scanning of all the addresses is over, then stop. If No, then proceed to the next step.
[0061] At step 222, the master (102) enables RNG logic for one of the address from the table.
[0062] At step 224, the master (102) checks for ACK for multiple iterations of random number generation on the selected address from the table.
[0063] At step 226, if acknowledge is more than 1, yes, then assign new address to the slave device and update the table, and if No, then disable the RNG.
At I2C Slave device:
[0064] At step 228, power ON of the slave device is done.
[0065] At step, 230, RNG logic enabled by the master (102) in all the slave devices (104-110n) is done.
[0066] At step 232, the slave address updated in one of the slave devices (104-110n) is done. Each slave participates in address the update based on the RNG.
[0067] At step 234, the RNG logic is disabled in the slave devices (104-110n) whose address is updated.
[0068] At step 236, the RNG logic is enabled for the addresses from the table to remove duplicates.
[0069] At step 238, disable the RNG.
[0070] At step 236, the process stops.
[0071] Fig. 3 illustrates a schematic diagram depicting the initialization of multiple I2C slaves having same I2C address, according to an exemplary implementation of the present invention.
[0072] In the present invention, the system consists of only one I2C bus interface between the master (102) and the slave devices (104-110n). Thus one I2C master (102) is connected to many I2C slave devices (104-110n) having the same I2C address. All these slave devices (104-110n) are having same I2C address, to begin with, and the address is known to the I2C master (102).
[0073] Each I2C slave device is having a random number generator (not shown in fig) that enables the device at that particular instance for a duration required by the master for programming the device. Initially, I2C slave devices (104-110n) come with a default RNG range. This RNG control is in the master hands and can be updated (enable, disable or change the range). These random number generates a random number in a range.
[0074] The RNG generation will get reset once all the devices (104-110n) on duration has become more than Max duration (Max random number * Duration required to update the address of slave device) because master (102) does not know the number of I2C slave devices attached it has to wait for full duration.
[0075] Further, the system discloses initialization of the I2C slave devices having the same I2C address:
[0076] During the initiation phase, the master (102) scans for standard I2C devices attached to the system if any. This is done by scanning for full address range of I2C slave addresses ie 0 to 127. If found the master (102) makes a record that address cannot be assigned to uninitialized slaves.
[0077] Further, if the master (102) founds/ identifies that the common address of uninitialized I2C slave devices (104-110n) having the same address is possessed by another physical device having hardcoded I2C slave address, then the master changes the common address before starting the initialization.
[0078] Further, the master (102) starts initialization by Enabling RNG logic in connected slaves having the same I2C address.
[0079] Further, the master (102) communicates to the slave devices (104-110n) with the known I2C slave address. Each slave is enabled based on the RNG (Random Number generator). The I2C slave devices (104-110n) is initialized by the master (102) with the updated slave address and the RNG (Random Number Generator) logic is disabled. The master (102) makes entry of the updated address in the address table, i.e. these slave devices (104-110n) move out of the pool of, I2C slave devices to be initialized. Further, once Max duration (i.e Duration required to update the address of slave device * max random number) is over. The master (102) switches to the scan phase. The master (102) fetches the update slave address table. This table one address can be possessed by the multiple slave I2C devices.
[0080] Further, again scanning of the I2C slave devices is done to remove the duplicate I2C slave address and assigning the unique I2C slave address. The RNG logic is enabled for one of the slave address from the table. Further, the master (102) checks for Acknowledgement for multiple iterations of random number generation on selected address from the table to ensure the duplicate I2C slave address is assigned unique I2C slave address. In case, if only one acknowledgment is coming for multiple iterations of random number generation, it is concluded that there is only one I2C slave device holding the slave address. But, if there is more than one acknowledgment, the master (102) assigns the updated slave address to the slave device and updates the address table. Further, the loop continues till all the slave addresses from the table are scanned for the duplicate slave address.
[0081] This can be easily understood through the example given below. Let the random number range for the slave devices (104-110n) lies between 1 to 10. Slave device 1 (S1), Slave device 2 (S2), Slave device 3(S3), Slave device 4(S4), Slave device 5(S5). As shown in Fig. 3, the master (102) has to wait for full range since the master (102) does not know the number of the attached I2C slave devices in first iteration. Further, the master (102) disables the RNG logic once the I2C slave address is updated.
At the time of 1st iteration:
SLAVE I2C SLAVE ADDRESS
Slave 1 2A
Slave 2 2B
Slave 2 2C
Slave 4 2D
Scanning for duplicates:
SLAVE I2C SLAVE ADDRESS
Slave 1 2A
Slave 2 2B
Slave 2 2C
Slave 4 2D
Slave 5 2E
The previous allotment master (102) assigned 2A to both S1, S2.
So master (102) scans for duplicates in each address of the table and assign a unique address to the I2C slave device (one having the duplicate address) and update the table.
The I2C master (102) gest an idea on the number of I2C slave devices (104-110n) in the first iteration and can change the range of the RNG logic.
Further, the master (102) scans for the duplicate address. During the scanning process to find the duplicate address, select slave address 2A from the table. Further, enable the RNG logic generation. Further, the master (102) looks for the ACK for multiple instances of RNG generation. If it gets more than 1ACK, assign the unique address to them, populate the table and disable RNG. Further, the master (102) of the system checks for multiple iterations of the RNG generation, making sure only the slave device is in the selected slave address. Further, the master (102) continues till all the addresses in the table are scanned for duplicates.
[0082] Fig. 4 illustrates a flow chart of the system for dynamically assigning address to a plurality of similar I2C (inter-integrated circuit) slave devices (104-110n), according to an exemplary implementation of the present invention.
[0083] Referring now to Fig. 4 that illustrates a flowchart (400) for dynamically assigning address to a plurality of similar I2C (inter-integrated circuit) slave devices (104-110n), according to an exemplary implementation of the present invention. The flow chart (400) of Fig. 4 is explained below with reference to Fig.1 as described above.
[0084] At step 402, communicating, by a master (102), on the known address of the I2C slave devices (104-110n).
[0085] At step 404 enabling, by a RNG (Random number generator), the I2C slave devices (104-110n) for updating their address.
[0086] At step 406, assigning, by the master (102), new I2C addresses to the I2C slave devices (104-110n).
[0087] At step 408, maintaining, by the master (102), a table of all the slave addresses.
[0088] At step 410, scanning, by the master (102), the I2C slave devices (104-110n) to remove a duplicate I2C slave address, and assigning a unique I2C slave address to the one having a duplicate slave address.
[0089] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to a person skilled in the art, the invention should be construed to include everything within the scope of the invention.