FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
As amended by the Patents (Amendment) Act, 2005
&
The Patents Rules, 2003
As amended by the Patents (Amendment) Rules, 2006
COMPLETE SPECIFICATION
(See section 10 and rule 13)
TITLE OF THE INVENTION
A method and system for estimating DC bus voltages of h-bridge cells of a cascaded multilevel inverter
APPLICANTS
Crompton Greaves Limited, CG House, Dr Annie Besant Road, Worli, Mumbai 400 030, Maharashtra. India, an Indian Company
INVENTORS
Dr Simi Paul Valsan. Raja Saha, Hafiz Imtiaz Hassan, all of Crompton Greaves Limited, Electronics Design Center, CG Global R&D. Kanjurmarg(E). Mumbai 400042, Maharashtra, India, all Indian nationals
PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

FIELD OF THE INVENTION
The present invention relates to estimating DC bus voltages of h-bridge cells of a cascaded multilevel inverter. More specifically, the present invention relates to indirectly measuring DC bus voltages without using voltage measuring devices across DC bus capacitors of a cascaded multi-level inverter.
BACKGROUND OF THE INVENTION
A cascaded multi-level inverter includes a plurality of phase output lines, where a multi-level output is generated at a phase output line by connecting multiple h-bridge cells in series to the phase output line. The phase voltage at each output line is sum of output voltages of corresponding h-bridge cells. A typical h-bridge cell includes a plurality of bridge connected diodes, a DC bus capacitor and a plurality of power transistors such as IGBTs. In an h-bridge cell, an AC input power is converted to a DC voltage through bridge connected diodes, which is converted to a pulse width modulated output through switching of the power transistors. The switching of the power transistors is controlled using a modulated sine wave.
In order to monitor and control the performance of an h-bridge cell in different operating conditions, it is desirable to measure the effective DC bus voltage across DC bus capacitor of the h-bridge cell. Conventionally, multiple voltage sensors are used in a cascaded h-bridge multi-level inverter for direct measurements of the DC bus voltages, where one sensor is employed for measuring voltage across one DC bus capacitor.
However, as the number of cells increases in a cascaded multi-level inverter, the number of sensors also increases, making the cascaded multi-level inverter circuitry becomes complex and less reliable. Further, use of large number of sensors

places a significant burden on the control unit associated with the cascaded multi-level inverter.
In view of the above-mentioned problems, there is a need for estimating DC bus voltages of h-bridge cells of a cascaded multi-level inverter without using voltage sensors across corresponding DC bus capacitors.
OBJECTS OF THE INVENTION
It is an object of the invention to estimate DC bus voltages of h-bridge cells of a cascaded multi-level h-bridge inverter without using voltage sensors across corresponding DC bus capacitors.
DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION
According to the invention, there is provided a method of estimating DC bus voltages of series connected h-bridge cells of a multi-level cascaded inverter based on corresponding multi-level PWM output and a switching reference waveform. The method comprising comparing the switching reference waveform with a set of pre-defined constants to determine time periods of switching activity in each of the h-bridge cells, encoding output of the comparison to generate an output indicating non-zero voltage level number of the multi-level PWM output at various time instants, sampling the multi-level PWM output at a pre-defined sampling rate, checking whether a current sample value of the multi-level PWM output is greater than an estimated threshold voltage of a voltage level defined by current encoder output. incrementing a current sum by the current sample value and repeating step (d) for a next sample, if the current sample value is greater than the estimated threshold voltage, estimating a net dc voltage of said voltage level by dividing the current sum

by number of samples producing the current sum, if the current sample value is less than the estimated threshold voltage, estimating a dc bus voltage of an h-bridge cell corresponding to said voltage level by subtracting a net dc voltage of a previous voltage level from the net dc voltage of said voltage level and setting the current sum to zero and repeating step (d) for a next sample of the multi-level PWM output.
Preferably, the set of pre-defined constants is defined by kp, where p =1, 2,....m-l, kp = p*2/(m-l) and m is number of voltage levels of the multi-level PWM output.
Preferably, the encoder output is represented by an n-bit value, where 2" > (m-
1).
Preferably, the threshold voltage of a voltage level i defined by current
encoder output is estimated as Vthj(t)= Vdcni-1(t) + Vdcbi-i (t) * 0.1. where i=l,2..m-
1, Vthi is the threshold voltage corresponding to voltage level i, Vdcni-1 is a net dc
voltage of a previous voltage level and Vdcbi-1 is a dc bus voltage corresponding to
the previous voltage level.
Preferably, a DC bus voltage of an h-bridge cell is estimated by calculating average value of DC bus voltages of two voltage levels contributed by the h-bridge cell.
According to the invention, there is provided a system for estimating DC bus voltages of series connected h-bridge cells of a multi-level cascaded inverter based on corresponding multi-level PWM output and a switching reference waveform. The system comprising a plurality of comparators for comparing the switching reference waveform with a set of pre-defined constants to determine time periods of switching activity in each of the h-bridge cells; an encoder for encoding output of the comparison to generate an output indicating non-zero voltage level number of the

multi-level PWM output at various time instants; and a digital signal processing module for sampling the multi-level PWM output at a pre-defined sampling rate; comparing a current sample value of the multi-level PWM output with an estimated threshold voltage of a voltage level defined by current encoder output; incrementing a current sum by the current sample value and repeating step (ii) for a next sample, if the current sample value is greater than the estimated threshold voltage; estimating a net dc voltage of said voltage level by dividing the current sum by number of samples producing the current sum, if the current sample value is less than the estimated threshold voltage; estimating a dc bus voltage of an h-bridge cell corresponding to said voltage level by subtracting a net dc voltage of a previous voltage level from the net dc voltage of said voltage level; and setting the current sum to zero and repeating step (ii) for a next sample of the PWM output.
These and other aspects, features and advantages of the invention will be better understood with reference to the following detailed description, accompanying drawings and appended claims, in which,
Fig, 1 illustrates a system for measuring DC bus voltages of h-bridge cells of a cascaded multi-level inverter in accordance with an embodiment of the present invention;
Fig. 2 illustrates a cascaded seven-level inverter in accordance with an embodiment of the invention;
Fig. 3 illustrates an exploded view of series connected h-bridge cells of the seven- level cascaded inverter of the Fig.2;
Fig. 4 illustrates a switching reference waveform and a plurality of carrier waveforms for generating switching pulses for switching transistors of h-bridge cells of Fig.3;

Fig. 5 illustrates PWM output of each h-bridge cell of Fig.3 and the combined multi-level output in accordance with an embodiment of the invention;
Fig. 6 illustrates a switching reference waveform and waveforms of the predefined constants for estimating DC bus voltages of h-bridge cells of Fig.3;
Fig. 7 illustrates output of comparison of the switching reference waveform and the set of constants of Fig. 6;
Fig. 8 illustrates an encoder output obtained by encoding the output of Fig.7; and
Fig. 9 illustrates a processed multi-level PWM output of the h-bridge cells of Fig. 3; and
Fig. 10 is a flowchart illustrating a method of estimating DC bus voltages of h-bridge cells of a cascaded multi-level inverter.
Fig. 1 illustrates a system 100 for measuring DC bus voltages of series connected h-bridge cells of a cascaded multi-level inverter based on corresponding multi-level PWM output and switching reference waveform.
The system 100 comprises a multi-level cascaded inverter 1, a carrier waveform generator 2, a switching reference waveform generator 3. a switching reference waveform 4, a comparator 5. a multi-level PWM output 6, comparators 7, 8, and 9, a binary encoder 10, a signal conditioning circuit 11, a processed PWM output 12 and a digital signal processing module 13.

The multi-level cascaded inverter 1 include x phase output lines and generates n-level PWM output at each of the x phase output lines by connecting (m-l)/2 h-bridge cells in series to each phase output line.
The carrier waveform generator 2 generates carrier waveforms for generating switching pulses for switching transistors of h-bridge cells of the multi-level cascaded inverter 1. In an embodiment of the present invention, the carrier waveform generator 2 generates two carrier waveforms for one h-bridge cell. For example, for switching of (m-l)/2 h-bridge cells, total (m-1) level shifted carrier waveforms are generated. Examples of a carrier waveform include, but are not limited to triangle wave and a saw tooth wave.
The switching reference waveform generator 3 generates switching reference waveforms for the multi-level cascaded inverter 1. The switching reference waveforms are generated based on one or more feedback signals. Example of a switching reference waveform includes, but is not limited to a sine wave. One such waveform generated is switching reference waveform 4
The comparator 5 compares the switching reference waveform and carrier waveforms received from respective generators 2 and 3 to provide switching pulses to the inverter 1. On receiving the switching pulses, the multi-level inverter 1 generates a multi-level PWM output 6 at a phase output line.

The comparators 7, 8, and 9 receive the switching reference waveform 4 corresponding to the multi-level PWM output 6 and compare it with a set of predefined constants kp where
kp = p*2/(m-1),p=l,2,...m-1 (1)
For the sake of illustration and clarity, only three comparators are shown herein. however, the total number of comparators required for comparison of switching reference waveform is equal to the number of predefined constants k. i.e m-1.
It may be noted, that the set of constants kp essentially correspond to amplitudes of carrier waveforms used for switching of the h-bridge cells for generating the PWM output 6. The amplitudes of the carrier waveforms are significant in identifying the time periods of switching activity in the h-bridge cells. An h-bridge cell in which switching activity takes place can be referred to as an active cell. The voltage level to be contributed by an active h-bridge cell in the PWM output 6 is pre-defined. Therefore, the information regarding time periods of active h-bridge cells is indicative of voltage levels of the multi-level PWM output 6 at various time instants.
The binary encoder 10 encodes the output of the comparators 7, 8 and 9 to generate an output indicating a non-zero voltage level number of the.multi-level PWM output 6 at various time instants. The output of the binary encoder 10 is an n-bit value ranging from i = 1, 2.... m-1, where 2n>(m-l).

The signal conditioning circuit 11 receives the multi-level PWM output 6, reduces it magnitude and level-shifts it to 0-nV range to generate a processed multilevel PWM output 12 represented by Vinv(t).
The digital signal processing module 13 receives the encoder output from the encoder 10 and the processed PWM output 12 from the signal conditioning circuit 11. Based on the two, it estimates DC bus voltages across DC bus capacitors of corresponding (m-l)/2 h-bridge cells. At any time, the output of the encoder 10 is referred to as ENC(t) and the PWM output 12 as Vinv(t).
Referring to Fig.2. when the value of m is equal to seven, the multi-level inverter 1 is represented by a seven-level inverter 200. The seven-level inverter 200 comprises nine h-bridge cells 14-22, a load 23, a phase-shift transformer 24, an AC supply 25, and three phase output lines 26, 27 and 28.
The h-bridge cells 14-16 are connected in series to the line 26, h-bridge cells 17-19 are connected in series to the line 27, and h-bridge cells 20-22 are connected in series to the line 28. The phase voltage at each of the phase output lines 26. 27 and 28 is sum of the output voltages of respective three h-bridge cells. Further, the phase voltages at 26, 27 and 28 together provide a multi-phase multi-level PWM signal to the load 23. The phase-shift transformer 24 supplies input voltages to each of the h-bridge cells 14-22. As illustrated in the figure, the input voltages supplied by the transformer 24 to the h-bridge cells 14-22 are phase shifted by 20 degrees.

The exploded view of the h-bridge cells 14-16 connected in series to the phase output line 26 is illustrated in the Fig.3, The exploded views of the h-bridge cells 17-19 and 20-22 are identical to that of the h-bridge cells 14-16. However, for the sake of illustration and clarity, only the exploded view of the h-bridge cells 14-16 has been shown.
The h-bridge cell 14 includes a plurality of diodes, a DC bus capacitor 31 connected between 30 and 32, and switching transistors Sn, S21, S31 and S41- The h-bridge cell 15 includes a plurality of diodes, a DC bus capacitor 35 connected between 34 and 36, and switching transistors S12, S22, S32 and S42. The h-bridge cell 16 includes a plurality of diodes, a DC bus capacitor 39 connected between 38 and 40, and switching transistors S13. S23, S33 and S43, Example of switching transistors referred herein, includes; but is not limited to, Insulated Gate Bipolar Transistors (IGBTs).
Now referring to Figs. 1, 3, and 4, the switching reference waveform generator 3 generates switching reference waveform 42 and the carrier waveform generator- 2 generates carrier waveforms 43-48 for the seven-level inverter 200. The comparator 5 compares the switching waveform 42 with each of the waveforms 43-48 to generate switching pulses for twelve switching transistors S11- S43 of the h-bridge cells 14-16. Due to varying amplitudes, the carrier waveforms 43-48 intersect the switching reference waveform 42 at different time instants and generate switching pulses for activating switching in each of the h-bridge cells 14-16 at different time instants.

On receiving the switching pulses, the h-bridge cells 14-16 generate PWM output at 33, 37 and 41 respectively and a combined multi-level PWM output 50 at the phase output line 26.
Fig. 5 illustrates the PWM outputs of corresponding h-bridge cells 14-16 and the combined multi-level PWM output 50. Each of the PWM outputs ranges from -100 V to 100 V, whereas the multi-level PWM output 50 is a seven-level output ranging from -300 to +300 V. As apparent from the figure, in the seven-level PWM output 50, each voltage level is contributed by an h-bridge cell of the h-bridge cells 14-16.
Fig. 6 illustrates the switching reference waveform 42 and waveforms of the constants kp which are provided to the comparators 7, 8, and 9 for the purpose of estimating DC bus voltages across DC bus capacitors 31, 35 and 39. The values of constants kp represent amplitudes of carrier signals 43- 48 and are estimated as 1/3, 2/3, 1, 4/3, 5/3 and 2 using equation 1.
The comparators 7, 8 and 9 compare the switching reference waveform 42 and the k values to generate total six output waveforms as illustrated in Figs. 7(a)-7(f). The output waveforms provide information regarding time periods of switching activity in each of the h-bridge cells 14-16 in the PWM output 50. The voltage level to be contributed by an active h-bridge cell in the PWM output 50 is pre-defined. Therefore, the information regarding time periods of active h-bridge cells is indicative of voltage level numbers of the multi-level PWM output 50 at various time instants.

The binary encoder 10 receives the output of the comparators 7, 8 and 9 and generates an encoded output 80 as illustrated in Fig. 8. The output 80 of the binary encoder 10 indicates non-zero voltage level number of the multi-level PWM output 50 at various time instants and has values ranging from i = 1. 2... .6.
Fig. 9 illustrates a processed PWM output 90 obtained after processing of the PWM output 50 by the signal conditioning circuit 11. As apparent from the figure, the processed PWM output 90 ranges from 0-3V and has total number of six non-zero distinct voltage levels, represented by i, where i=l,2..6.
Referring to Figs. 1, 3,. 8 and 9, the processed PWM output 90 and the output 80 of the encoder 10 are fed to the digital signal processing module 13 for determining DC bus voltages across DC bus capacitors 31, 35 and 39 of the h-bridge cells 14-16 respectively. For the purpose of estimating the DC bus voltages, the digital signal processing module 13 samples the PWM output 90 at a predefined sampling rate.
For the three h-bridge cells 14-16, the DC bus voltages are represented by Vdc1(t), Vdc2(t) and Vdc3(t). Further, for a voltage level number i of the PWM output 50, a DC bus voltage is represented by Vdcbi (t), a net DC voltage of a voltage level is represented by Vdcni (t), and a threshold voltage is represented by Vthi(t), where i=l, 2..6.

Fig. 10 is a flowchart of a method of estimating DC bus voltages of h-bridge is of a cascaded multi-level inverter (1,200) based on the processed PWM output (12, 90) and output of the encoder 10.
At step 101, the Vdcbj (t), Vdcbi (t), Vthi(t). sumj(n), samplei(n) and n are set to zero for all the values of i, where x=l, 2,..(m-l)/2 and i~l,2...m-l.
At step 102, it is checked whether the inverter (1, 200) is turned on and is generating an output (12, 90).
If the inverter (1,200) is turned on and is generating an output (12, 90), then at step 103, the value of i is set equal to that of current encoder output ENC(t) and a threshold voltage of current voltage level i is estimated using the formula,
Vthi (t) = Vdcni.] (t) + Vdcbi-1 (t)
0.1 (2)
where Vdcni-1 is a net DC voltage of a previous voltage level and Vdcbj.] is a dc bus voltage of a previous voltage level.
After estimating Vthi(t) at step 103, at step 104, it is checked whether a current sample value of the PWM output (12, 90) is greater than the estimated threshold voltage Vthi(t). By executing this step, the high/low state of the current sample with respect to the current voltage level i is determined. If the current sample value is greater than corresponding threshold voltage Vthj(t), it implies that the current sample is either in high state or has made a transition from low to high state. If the current sample value is less than the estimated threshold voltage Vthj(t), it implies that either

the current sample is in low state or has made a transition from a high state to low state.
If the current sample value is greater than the estimated threshold voltage Vthi(t). then steps 105 and 106 are executed. At step 105, the number of current samples n is incremented by one. Further, at step 106. a current sum is incremented by the current sample value and a sample number is incremented by one. By executing the step 106, a cumulative sum of consecutive samples of a high state is estimated. After executing step 106, step 103 is repeated for a next sample.
If the current sample value is less than the estimated threshold voltage Vth,(t), then at step 107, a net dc voltage Vdcnj(t) of voltage level i is estimated by dividing the current sum by number of samples producing the current sum. When the current sample is in low state, a net dc voltage Vdcni(t) of voltage level i may be estimated as zero. Further, when the current sample has made a transition from high state to low state, then, a net dc voltage Vdcni(t) of voltage level i may be an average value of consecutive samples of a previous high state.
Based on the net dc voltage Vdcn;(f) of voltage level i , a dc bus voltage Vdcbj(t) of voltage level i is estimated using the formula:
Vdcbi(t) = Vdcni (t) - Vdcni-1 (t) (3)
where Vdcni-1 is a net dc voltage of current voltage level i and Vdcn1 is a net dc voltage of a previous voltage level. After estimating a dc bus voltage Vdcbi(t) of current voltage level i, the values of current sum, current number of samples, and sample number are set to zero and step 102 is repeated for a next sample.

It may be noted, that in one quarter cycle of operation, one h-bridge cell contributes two non-zero voltage levels of the PWM output (12, 90). Therefore, at any time, a DC bus voltage across a DC bus capacitor of an h-bridge cell is estimated by determining an average value of DC bus voltages of respective two voltage levels
Vdcx(t) = (Vdcbi(t) + Vdcbm-i(t))/2 (4)
Jt may be noted, that due to initialization of all the variables as zero, it may take at least one cycle of operation to obtain correct estimate of DC bus voltages across DC bus capacitors of the h-bridge cells of a cascaded multi-level inverter.
Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the scope of the invention as defined in the appended claims.

We claim:
1. A method of estimating DC bus voltages of series connected h-bridge cells of a multi-level cascaded inverter based on corresponding multi-level PWM output and a switching reference waveform, the method comprising:
a. comparing the switching reference waveform with a set of pre-defined constants to determine time periods of switching activity in each of the h-bridge cells; b. encoding output of the comparison to generate an output indicating non-zero voltage level number of the multi-level PWM output at various time instants;
c. sampling the multi-level PWM output at a pre-defined sampling rate;
d. checking whether a current sample value of the multi-level PWM output is
greater than an estimated threshold voltage of a voltage level defined by current
encoder output;
e. incrementing a current sum by the current sample value and repeating step
(d) for a next sample, if the current sample value is greater than the estimated
threshold voltage;
f. estimating a net dc voltage of said voltage level by dividing the current sum
by number of samples producing the current sum, if the current sample value is less
than the estimated threshold voltage;
h. estimating a dc bus voltage of an h-bridge cell corresponding to said voltage level by subtracting a net dc voltage of a previous voltage level from the net dc voltage of said voltage level; and
i, setting the current sum to zero and repeating step (d) for a next sample of the multi-level PWM output.

2. The method as claimed in claim 1, wherein the set of pre-defined constants is defined by kp, where p =1, 2,....m-l, kp = p*2/(m-l) and m is number of voltage levels of the multi-level PWM output.
3. The method as claimed in claim 2, wherein the encoder output is represented by an n-bit value, where 2" > (m-1).
4. The method as claimed in claim 3, wherein the threshold voltage of a voltage level i defined by current encoder output is estimated as Vthi(t)= Vdcni-l(t) + Vdcbi-l (t) * 0.1, where i= 1,2..m-1, Vthj is the threshold voltage corresponding to voltage level i, Vdcni-l is a net dc voltage of a previous voltage level and Vdcbi-l is a dc bus voltage corresponding to the previous voltage level.
5. The method as claimed in claim 1, which comprises estimating a DC bus voltage of an h-bridge cell by calculating average value of DC bus voltages of two voltage levels contributed by the h-bridge cell.
6. A system for estimating DC bus voltages of series connected h-bridge cells of a multi-level cascaded inverter based on corresponding multi-level PWM output and a switching reference waveform, the system comprising:
a. a plurality of comparators for comparing the switching reference waveform with a set of pre-defined constants to determine time periods of switching activity in each of the h-bridge cells;

b. an encoder for encoding output of the comparison to generate an output indicating non-zero voltage level number of the multi-level PWM output at various time instants; and
c. a digital signal processing module for
(i) sampling the multi-level PWM output at a pre-defined sampling rate;
(ii) comparing a current sample value of the multi-level PWM output with an estimated threshold voltage of a voltage level defined by current encoder output;
(iii) incrementing a current sum by the current sample value and repeating step (ii) for a next sample, if the current sample value is greater than the estimated threshold voltage;
(iv) estimating a net dc voltage of said voltage level by dividing the current sum by number of samples producing the current sum, if the current sample value is less than the estimated threshold voltage;
(v) estimating a dc bus voltage of an h-bridge cell corresponding to said voltage level by subtracting a net dc voltage of a previous voltage level from the net dc voltage of said voltage level; and
(vi) setting the current sum to zero and repeating step (ii) for a next sample of the PWM output.
7. The system as claimed in claim 6, wherein the set of pre-defined constants is defined by kp, where p =1, 2,....m-l, kp = p*2/(m-l) and m is number of voltage levels of the multi-level PWM output.
8. The system as claimed in claim 7, wherein the encoder output is represented by an n-bit value, where 2n > (m-1).

9. The system as claimed in claim 8, wherein the threshold voltage of a voltage level i defined by current encoder output is estimated as Vthi(t)= Vdcni-1(t) + Vdcbi-1 (t) * 0.1, where i=l,2..m-l, Vth, is the threshold voltage corresponding to voltage level i. Vdcni-1 is a net dc voltage of a previous voltage level and Vdcbi-1is a dc bus voltage corresponding to the previous voltage level.
10. The system as claimed in claim 6, wherein the digital signal processing module estimates a DC bus voltage across an h-bridge cell by calculating average value of DC bus voltages of two voltage levels contributed by the h-bridge cell.