Abstract: The present disclosure provides a method for overhead byte processing in SONET/SDH network element. In one embodiment, which is achieved by configuring a switch on a central controller card of the network element, configuring each port of the switch routed to each of the card slot in chassis, terminating some of the ports of the switch on the central controller card where management traffic to be locally terminated is connected to HDLC/LAPD controller device, allocating timeslots on each port of the switch and configuring line card hardware to place overhead bytes into appropriate timeslots, configuring the switch on the central card to either tunnel the overhead bytes or drop the bytes to the local HDLC controller and enabling the central controller card to generate a SYNC pulse to mark the start of timeslot sequence which is distributed to all cards which use it to reset the timeslot count.
Field of the Invention
This invention relates to network elements and more particularly to byte processing schemes in the network elements.
Background of the invention
The Synchronous Digital Hierarchy (SDH) and its North-American equivalent, the Synchronous Optical Network (SONET), are the compatible standards for data transmission in the public wide area network (WAN) domain.
SDH/SONET networks provide reliable, guaranteed available bandwidth, low jitter connections. These characteristics are generally required for voice quality networks.
However, SDH/SONET is bandwidth inefficient and has a higher overhead when compared to other network architectures such as Ethernet networks.
It is often required to process SONET/SDH overhead bytes for variety of features and applications. One of the major issues in processing the overhead bytes while adding new applications and features is the requirement of change of hardware/cards.
For instance, in traditional SONET/SDH network elements, TOH (Transport Overhead, RSOH ‘Regenerator Section Overhead’ + MSOH ‘Multiplexer Section Overhead) bytes are typically terminated and re-inserted in Line Terminating Equipment or Path Terminating Equipment (LTE/PTE equipment). Following are some of the applications of the existing architecture:
(1) Data Communication Channel ‘DCC’ bytes are used for in-band management of remote (Network Elements (NEs). Typically, High Level Data Link Control over Link Access Protocol for Data Channels (HDLC/LAPD) L2 and Internet Protocol over Connectionless Network Protocol (IP/CLNP) L3 protocols are used for forwarding/routing management packets within this network. This management information for NEs of different vendors almost invariably doesn’t interoperate. This problem requires DCC bytes to be transparently tunneled to be able to mix NEs of different vendors within the network. It is possible for a given NE to use DCC-M for management of same vendor (including the NE itself) equipment and tunnel DCC-R so that other vendor equipment can use DCC-R for remote management. This is just one example of being able to tunnel some set of TOH bytes. Following are some other applications one can think of.
(2) Tunneling E1/E2 order-wire bytes at least even if the NE itself does not support order-wire capability.
(3) Tunneling K1/K2 (and possibly entire MSOH) in case the node needs to be used like a regenerator, but it actually is not a true regenerator. This may be typically useful in case of MSSP (Managed Security Service Provider) Ring setup if the node does not add-drop any traffic (it only acts as pass-through node) on the given node. This is quite handy considering the MSSP Ring limitation of support for only 16 nodes in a ring.
However, the problem associated with above-mentioned applications is either product will not support tunneling OR there will be special serial lines which shall be routed to different slots and shall be connected in some central card through some FPGA/CPLD to ensure connectivity through software reconfiguration. Typically several serial lines (one for each application) may be carried from each traffic slot to central overhead processing card requiring large amount of connectivity from line cards to central processing card requiring higher connectivity. This scheme is also not flexible enough to support future applications.
Hence, a novel system and a method for configuring service ports are required.
Summary of the Invention
It is an object of the present invention to propose for future-proof overhead byte processing in SDH/SONET Network Element.
Accordingly, the present invention provides a method for overhead byte processing in SONET/SDH network element. The method comprises the steps of configuring a switch on a central controller card of the network element, configuring each port of the switch routed to each of the card slot in chassis, terminating some of the ports of the switch on the central controller card where management traffic to be locally terminated is connected to HDLC/LAPD controller device, allocating timeslots on each port of the switch and configuring line card hardware to place overhead bytes into appropriate timeslots, configuring the switch on the central card to either tunnel the overhead bytes or drop the bytes to the local HDLC controller; and enabling the central controller card to generate a SYNC pulse to mark the start of timeslot sequence which is distributed to all cards which use it to reset the timeslot count.
In an embodiment the method includes configuring a shared high-speed TDM bus running on the backplane where the shared TDM bus is clocked by the system clock from a central controller card. Each line card extracts a timeslot from the shared TDM bus and also for inserting data at an appropriate rate. The central controller card is configured to generate a SYNC pulse to mark the start of TDM bus timeslot sequence which is distributed to all cards for the enablement of resetting the timeslot count.
Brief Description of Drawings
Figure 1 illustrates future-proof overhead byte processing scheme as per an embodiment herein.
Figure 2 illustrates future-proof overhead byte processing solution based on a shared high-speed TDM bus running on the backplane as per an embodiment herein.
Description of the Invention
Various embodiments of the present invention provide a method for overhead byte processing in SONET/SDH network element.
References will be now made to Figure 1 and Figure 2 that illustrate the future-proof overhead byte processing in SDH/SONET Network Element as per the embodiments described herein.
Figure 1 illustrates an architectural framework 100 of a central DS0 switch 110 based, flexible future-proof solution for overhead byte processing as per an embodiment herein.
The architectural framework 100 uses TDM (Time Division Multiplexing) bus 120 based transport of SONET/SDH overhead byte processing. The framework 100 also uses centralized DS0 switch 110 based tunneling (cross connect) of SONET/SDH overhead bytes. The framework enables the use of centralized shared TDM bus for SONET/SDH overhead bytes processing, the use of “centralized DS0 switch based “and “shared TDM bus based” architectures for applications based on SONET/SDH overhead bytes.
The applications based on SONET/SDH overhead bytes include E1/VC12 based remote node management, overhead byte (specifically remote management bytes like DCC-R, DCC-M, F1) tunneling for enabling management of other vendor nodes through tunneled bytes, tunneling of K1/K2 and TOH bytes to enable accommodation of more nodes in a MSSPRing based deployment when node does not drop any traffic, tunneling of E1/E2 bytes to enable other nodes to use order-wire and F1 (or any other byte) based UDC (user data channel) on a craft connector.
The tunneling of k1/k2 and TOH bytes is a regenerator like functionality.
The solution provided through the above-described architecture framework 100 provides a flexible framework, which can be scaled to provide capability to use overhead bytes to manage the node OR tunnel any overhead bytes across ports.
As per this solution, a DS0 switch 110 on the central controller card or cross connect fabric card may be provided. Each port of the switch 110 may be routed to each of the card slot in the chassis. Some of the port of the DS0 switch 110 may be terminated on the central card where management traffic to be locally terminated may be connected to the HDLC/LAPD controller device 130. Timeslots may be allocated on each of the port of DS0 switch 110 and configures line card hardware to place overhead bytes into appropriate timeslots.
In an embodiment the switch is a (64 kbps timeslot) switch.
In an embodiment each port of the switch is carries a 32 or more 64 kbps timeslots to the central controller card and also in the other direction.
In an embodiment, the DS0 switch 110 is configured on the central card to either tunnel the overhead bytes or configure the switch to drop the bytes to the local HDLC controller 130. Central card may generate a SYNC pulse to mark the start of TDM bus timeslot sequence, which is distributed to all cards which use it to reset the timeslot count.
Figure 2 illustrates future-proof overhead byte processing solution based on a shared high-speed TDM bus running on the backplane as per an embodiment herein.
The byte processing solution based on a shared high-speed TDM bus running on the backplane includes a shared TDM bus running on the backplane clocked by the system clock from a central card.
In an embodiment, the central controller card is a cross connect, system timing controller card.
In the solution based on a shared high-speed TDM bus running on the backplane, each line card is configured to extract a DS0 timeslot from this bus and also insert data at NxDS0 rate.
In an embodiment, the line card tri-states all the timeslots it does not use.
In the solution based on a shared high-speed TDM bus running on the backplane, the central card generates a SYNC pulse to mark the start of TDM bus timeslot sequence, which is distributed to all cards, which use it to reset the timeslot count.
While the present invention has been described with respect to certain embodiments, it will be apparent to those skilled in the art that various changes and modification may be made without departing from the scope of the invention as defined in the following claims.
We Claim:
1. A method for overhead byte processing in SONET/SDH network element, the method comprising the steps of:
configuring a switch on a central controller card of the network element;
configuring each port of the switch routed to each of the card slot in chassis;
terminating some of the ports of the switch on the central controller card where management traffic to be locally terminated is connected to HDLC/LAPD controller device;
allocating timeslots on each port of the switch and configuring line card hardware to place overhead bytes into appropriate timeslots;
configuring the switch on the central card to either tunnel the overhead bytes or drop the bytes to the local HDLC controller; and
enabling the central controller card to generate a SYNC pulse to mark the start of timeslot sequence which is distributed to all cards which use it to reset the timeslot count.
2. The method as in claim 1, wherein the switch is a (64 kbps timeslot) switch.
3. The method as in claim 1, wherein each port of the switch carries 32 or more 64 kbps timeslots to the central controller card and also in the other direction.
4. A method for overhead byte processing in SONET/SDH network element, the method comprising the steps of:
configuring a shared high-speed TDM bus running on the backplane;
the shared TDM bus being clocked by the system clock from a central controller card;
enabling each line card for extracting a timeslot from the shared TDM bus and also for inserting data at an appropriate rate;
configuring the central controller card to generate a SYNC pulse to mark the start of TDM bus timeslot sequence which is distributed to all cards for the enablement of resetting the timeslot count.
5. The method as in claim 4, wherein the central controller card is a cross connect, system timing controller card.
6. The method as in claim 4, wherein the line card tri-states all the time slots it does not use.
| # | Name | Date |
|---|---|---|
| 1 | 1285-CHE-2012-EVIDENCE FOR REGISTRATION UNDER SSI [31-03-2022(online)].pdf | 2022-03-31 |
| 1 | Form-5.pdf | 2012-04-09 |
| 2 | Form-3.pdf | 2012-04-09 |
| 2 | 1285-CHE-2012-FORM FOR SMALL ENTITY [31-03-2022(online)].pdf | 2022-03-31 |
| 3 | Form-1.pdf | 2012-04-09 |
| 3 | 1285-CHE-2012-Abstract_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 4 | Drawings.pdf | 2012-04-09 |
| 4 | 1285-CHE-2012-Claims_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 5 | Drawings as Filed.pdf | 2013-03-28 |
| 5 | 1285-CHE-2012-Description_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 6 | As Filed Complete Specification- Devendra.pdf | 2013-03-28 |
| 6 | 1285-CHE-2012-Drawings_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 7 | abstract1285-CHE-2012.jpg | 2014-01-03 |
| 7 | 1285-CHE-2012-IntimationOfGrant23-10-2020.pdf | 2020-10-23 |
| 8 | 1285-CHE-2012-Marked up Claims_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 8 | 1285-CHE-2012-FER.pdf | 2019-07-12 |
| 9 | 1285-CHE-2012-PatentCertificate23-10-2020.pdf | 2020-10-23 |
| 9 | 1285-CHE-2012-OTHERS [10-01-2020(online)].pdf | 2020-01-10 |
| 10 | 1285-CHE-2012-ABSTRACT [10-01-2020(online)].pdf | 2020-01-10 |
| 10 | 1285-CHE-2012-FER_SER_REPLY [10-01-2020(online)].pdf | 2020-01-10 |
| 11 | 1285-CHE-2012-CLAIMS [10-01-2020(online)].pdf | 2020-01-10 |
| 11 | 1285-CHE-2012-DRAWING [10-01-2020(online)].pdf | 2020-01-10 |
| 12 | 1285-CHE-2012-COMPLETE SPECIFICATION [10-01-2020(online)].pdf | 2020-01-10 |
| 13 | 1285-CHE-2012-CLAIMS [10-01-2020(online)].pdf | 2020-01-10 |
| 13 | 1285-CHE-2012-DRAWING [10-01-2020(online)].pdf | 2020-01-10 |
| 14 | 1285-CHE-2012-ABSTRACT [10-01-2020(online)].pdf | 2020-01-10 |
| 14 | 1285-CHE-2012-FER_SER_REPLY [10-01-2020(online)].pdf | 2020-01-10 |
| 15 | 1285-CHE-2012-OTHERS [10-01-2020(online)].pdf | 2020-01-10 |
| 15 | 1285-CHE-2012-PatentCertificate23-10-2020.pdf | 2020-10-23 |
| 16 | 1285-CHE-2012-FER.pdf | 2019-07-12 |
| 16 | 1285-CHE-2012-Marked up Claims_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 17 | 1285-CHE-2012-IntimationOfGrant23-10-2020.pdf | 2020-10-23 |
| 17 | abstract1285-CHE-2012.jpg | 2014-01-03 |
| 18 | 1285-CHE-2012-Drawings_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 18 | As Filed Complete Specification- Devendra.pdf | 2013-03-28 |
| 19 | 1285-CHE-2012-Description_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 19 | Drawings as Filed.pdf | 2013-03-28 |
| 20 | Drawings.pdf | 2012-04-09 |
| 20 | 1285-CHE-2012-Claims_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 21 | Form-1.pdf | 2012-04-09 |
| 21 | 1285-CHE-2012-Abstract_Granted 349999_23-10-2020.pdf | 2020-10-23 |
| 22 | Form-3.pdf | 2012-04-09 |
| 22 | 1285-CHE-2012-FORM FOR SMALL ENTITY [31-03-2022(online)].pdf | 2022-03-31 |
| 23 | Form-5.pdf | 2012-04-09 |
| 23 | 1285-CHE-2012-EVIDENCE FOR REGISTRATION UNDER SSI [31-03-2022(online)].pdf | 2022-03-31 |
| 1 | Searchstrategy_03-07-2019.pdf |