TECHNICAL FIELD

The present disclosure relates to differential delay compensation design. In particular  the present invention relates to receiving data streams over Synchronous Digital Hierarchy (SDH) network or Synchronous Optical Network (SONET) by implementing Virtual Concatenation (VCAT) receiver.

BACKGROUND

SONET /SDH were created as the standard fiber optic transmission system for long-distance telephone and data communications. First  the SONET hierarchy consists of a number of levels  organized according to data transmission speed. Each level has an optical carrier (OC) and an electrical level transmission frame structure  termed the synchronous transport signal (STS).

The basic unit of SONET transmission capacity (51.84 Mb/s) is designated as an STS-1 frame  with each byte in this frame representing a timeslot. The capacity of a SONET optical link is increased by byte-interleaving or multiplexing several basic STS-1 frames. However  each individual STS-1 frame remains separate from the others within this multiplexing structure and is managed as a separate unit carrying a different information stream from all others.

However  in many situations it may be necessary to transport data information of larger capacity between two end-points as a single stream. To achieve this  SONET networks employ a method called contiguous concatenation  wherein the number of basic frames permitted to be so linked are certain fixed multiples of 3 (3  12  48  192  768) and the linked frames are required to have a fixed relationship in time to each other when transported over a SONET network.

While the restrictions placed upon contiguously concatenated frames greatly simplify the implementation of equipment  it unfortunately also unduly constrains the flexibility afforded to a user in creating and configuring a SONET network  and also impacts the efficiency of the data transfer process.

A standard for transmission of information over SONET/SDH networks calls for the use of virtual concatenation (VCAT) to solve this problem. Virtual concatenation attempts to link together multiple STS-1 sub-frames in the same manner as contiguous concatenation  but eliminates all of the restrictions on the number of basic STS-1 sub-frames thus linked as well as the relative placement of these STS-1 sub-frames within the complete SONET frame structure.

VCAT facilitates the efficient transfer of data of arbitrary bandwidth over an SONET/SDH network. Further enhancements to vary the bandwidth without any loss of data were enabled by the Link Capacity Adjustment Scheme (LCAS). These are standardized by the International Telecommunication Union (ITU) in its standards G.707  G.7041 and G.7042. SDH is a byte-oriented interface where the basic units of transmission are 8bits (a byte). As the speed of the SDH interfaces increases performing all the operations at a byte-level requires very high-speed operations.

In conventional designs  the buffering of all the traffic for a tributary unit was done with different metrics. For lower order containers  the bytes in a frame was treated as a unit  while for higher order containers  the data in a row was the unit of operation. This greatly increased the amount of storage required and scaling the design for greater capacity becomes difficult. Moreover  few conventional methods were capable of STM16 and above operation when implemented in FPGA type technologies where the clock-speeds are less than ASICs.

U.S. Pat. No. 6 160 819  issued to Partridge et. al.  discloses a form of inverse multiplexing of variable-length packet data over multiple low-speed SONET links that bears some general resemblance to the virtual concatenation technique  but presupposes the existence of a Byte-By-Byte (BBB) “striping unit” that performs the actual splitting and recombining of the data stream  without giving details about its construction. A co-pending U.S. patent application Ser. No. 10/176 230 filed Jun. 3  2002  entitled “Efficient Variably-Channelized SONET Multiplexer and Payload Mapper” describes a variably-channelized SONET mapper arrangement that is substantially more efficient at processing contiguously concatenated streams than the prior art at high speeds  but this is also inapplicable to the task of processing virtual concatenated frames due to its multiplexing and demultiplexing in powers of 2 rather than arbitrary combinations.

Therefore  the present disclosure overcomes the above-mentioned problems by providing a method for receiving data streams by implementing Virtual Concatenation (VCAT) receiver. The present invention defines a fixed block-size for the basic operation and uses double buffered receive-page memory to scale the VCAT receiver to support heterogeneous data streams at higher rates.

SUMMARY OF THE DISCLOSURE

The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method and a system as described in the description.

The present invention uses a new design to scale the rates while retaining the FPGA as the implementation platform (keeping the clock speed low which helps reduce power). In one embodiment  the design scales according to the number of tributary units. In another embodiment  the design is dependent on the number of streams.

Accordingly  the present disclosure relates to a method for implementing Virtual Concatenation (VCAT) receiver over SDH/SONET network for receiving data streams. The method comprising steps of extracting control information from SDH stream for each Tributary Unit (TU) and assembling data bytes of that TU using the extracted control information into fixed size pages with well-defined starting position by writing the data bytes into an active page of double buffered receive-page memory. Then  a signal is generated to write the completed page to external memory  upon completion of writing of fixed size bytes into the active page for each TU  and simultaneously the active page is swapped for this TU of the receive-page memory for assembly of subsequent data bytes. The completed page for each TU is written into an external memory  common to all TU’s  in an order such that writing for each TU is completed prior to the assembly of the next page for that TU. Upon completion of writing of all TU’s that have the same offset from the well-defined starting position and belonging to the VCG  a signal is generated to read one fixed-size page from the external memory for all the TU’s for a Virtual Concatenation Group (VCG). Then  the fixed-size pages are read for all TU’s of a VCG from the external memory and stored in an internal double-buffered transmit-page memory and a signal is generated to interleave the stored pages once all TU’s of a VCG have been read from the external memory. Finally  the data stream is constructed for each VCG by interleaving the bytes held in the stored fixed-size pages in the transmit-page memory based on the control information for each TU of the VCG. Simultaneously  the next fixed-size page is read from external memory into other page of the double-buffered transmit-page memory.

Accordingly  the present disclosure relates to a VCAT receiver for receiving data streams over SDH network. The receiver comprises a Telecom Logic block to generate control information and a Control History block that stores the VCAT and LCAS information received from the telecom logic block and communicates this to the Transmit Control to effect the proper recovery of the data stream. Further  the receiver comprises a write logic block to write the received data bytes into a double buffered receive-page memory and to generate a write signal for writing the page into external memory and to generate read signal to initiate reading of data bytes from the external memory. The Transmit Control block for each VCG is configured to read fixed-size pages from the external memory upon receiving read signal and interleaving the data bytes based on the sequence numbers and member’s data carrying status.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects  embodiments  and features described above  further aspects  embodiments  and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present disclosure are set forth with particularity in the appended claims. The disclosure itself  together with further features and attended advantages  will become apparent from consideration of the following detailed description  taken in conjunction with the accompanying drawings. One or more embodiments of the present disclosure are now described  by way of example only  with reference to the accompanied drawings wherein like reference numerals represent like elements and in which:

Figure 1 shows the structure of a Lower Order Tributary Unit (TU11) in an AU3 structure.

Figure 2 illustrates the structure of a Higher Order Tributary Unit (VC3) in an AU3 Structure.

Figure 3 illustrates the concept of several Virtual Concatenation Groups (VCGs) being carried in an SDH link.

Figure 4 illustrates a functional block diagram of VCAT receiver in accordance with an embodiment of the present disclosure.

Figure 5 illustrates a block diagram for the write process in accordance with an embodiment of the present disclosure.

Figure 6 illustrates page and frame alignment in accordance with an embodiment of the present disclosure.

Figure 7 illustrates the update logic that tracks the most-delayed frame per VCG in accordance with an embodiment of the present disclosure.

The figures depict embodiments of the disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

DETAILED DESCRIPTION

The foregoing has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure  both as to its organization and method of operation  together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood  however  that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

Accordingly  the present disclosure relates to a method for implementing Virtual Concatenation (VCAT) receiver over SDH network for receiving data streams. In one embodiment  SDH network includes SDH network and SONET network. The method comprising steps of extracting control information from SDH stream for each Tributary Unit (TU) and assembling data bytes of that TU using the extracted control information into fixed size pages with well-defined starting position by writing the data bytes into an active page of double buffered receive-page memory. Then  a signal is generated to write the completed page to external memory  upon completion of writing of fixed size bytes into the active page for each TU  and simultaneously the active page is swapped for this TU of the receive-page memory for assembly of subsequent data bytes. The completed page for each TU is written into an external memory  common to all TU’s  in an order such that writing for each TU is completed prior to the assembly of the next page for that TU. Upon completion of writing of all TU’s that have the same offset from the well-defined starting position and belonging to the VCG  a signal is generated to read one fixed-size page from the external memory for all the TU’s for a Virtual Concatenation Group (VCG). Then  the fixed-size pages are read for all TU’s of a VCG from the external memory and stored in an internal double-buffered transmit-page memory and a signal is generated to interleave the stored pages once all TU’s of a VCG have been read from the external memory. Finally  the data stream is constructed for each VCG by interleaving the bytes held in the stored fixed-size pages in the transmit-page memory based on the control information for each TU of the VCG. Simultaneously  the next fixed-size page is read from external memory into other page of the double-buffered transmit-page memory.

In one embodiment of the present disclosure  each SDH frame of a Tributary Unit (TU) is tagged with frame number and a sequence number indicating its position in the interleaving of the members of the virtually concatenated group (VCG).

In another embodiment of the present disclosure  the control information comprises Tributary Unit (TU) addresses  interrupts for various changes in the alarms of the network  link capacity adjustment scheme (LCAS) information and wherein said LCAS information comprises sequence number  control word and group identifier bit of SDH frames.

In yet another embodiment of the present disclosure  each page of the double buffered page memory consists of predetermined number of bytes and each TU consists of an active page and a backup page  wherein the active page is swapped when the signal for writing the page to external memory is generated.

In still another embodiment of the present disclosure  the address of a fixed-size page in external memory is determined in a manner that the storage allocated to different TU’s do not overlap  said address is computed on the basis of the control information in the TU  the TU identifier bits  and the offset from the well-defined starting position.

In another embodiment of the present disclosure  the signals to write the completed pages to external memory are acted upon in strict priority of the bandwidth capacity of the TU they represent to avoid stalling higher bandwidth requests by large number of lower bandwidth requests. The above method is implemented by having multiple First In First Out (FIFO) queues  one for each unique bandwidth granularity of the TU’s  and storing the signals to write the completed pages to external memory into the corresponding bandwidth FIFO  and serving the requests in a FIFO only if there are no requests in FIFOs of higher bandwidth.

In yet another embodiment of the present disclosure  the first frame number update in most delayed computation interval is updated as smallest frame in the memory and further updates within the interval are compared to determine the smallest frame number  if further updated frame number is smaller than the stored smallest frame number in the memory then the memory is updated with the new smallest frame number  and thereafter the read side is updated with stored smallest frame number at the end of the most-delayed computation interval for triggering the read of bytes from external memory for the VCG till the updated frame number.

In still another embodiment of the present disclosure  the fixed-size page read from the external memory is stored into the transmit-page memory for that VCG at an address corresponding to the sequence number of that TU in the VCG  and the data bytes are stored with an additional valid bit for each byte and said valid bit indicates that the TU’s data should be interleaved into the VCG data stream.

In another embodiment of the present disclosure  interleaving the pages read from the external memory has to be completed before pages are read into the same location in the transmit-page memory.

Accordingly  the present disclosure relates to a VCAT receiver for receiving data streams over SDH network. The receiver comprises a Telecom Logic block to generate control information and a Control History block that stores the VCAT and LCAS information received form the telecom logic block and communicates this to the Transmit Control to effect the proper recovery of the data stream. Further  the receiver comprises a write logic block to write the received data bytes into a double buffered receive page memory and to generate a write signal for writing the page into external memory and to generate read signal to initiate reading of data bytes from the external memory. The Transmit Control block for each VCG is configured to read fixed-size pages from the external memory upon receiving read signal and interleaving the data bytes based on the sequence numbers and member’s data carrying status.

In another embodiment of the present disclosure  the telecom logic comprises payload interface for carrying telecom data  pointer-interpreter  path overhead processing  LCAS control interface to provide LCAS information to the Transmit Control block.

In yet another embodiment of the present disclosure  the transmit control block comprises a Common Transmit Controller block that provides to each Transmit Control block the frame number up to which data from external memory should be read  and at least one External Memory Access sequencer to ensure that the memory requests are placed in prerequisite order; and to control and coordinate external memory read operation with per VCG Transmit Control logic.

In still another embodiment of the present disclosure  the interleaving logic reads one or more bytes from the transmit-page memory for each of the members in a sequence and packs the bytes into a word depending on the valid bit associated with each byte.

In another embodiment of the present disclosure  the interleaving logic for a High Speed port uses the write/read port along with read-only port to increase the read bandwidth.

In yet another embodiment of the present disclosure  interleaving logic is shared among several low-speed ports and the ports are being interleaved based on the availability of data to be interleaved.

Embodiments of the instant disclosure relates to a design of the Transmit side of the Virtual Concatenation (VCAT) processor. It explains in detail about an understanding of the concepts of SDH Multiplexing and Virtual Concatenation as described in ITU G.707 and an understanding of LCAS described in ITU G.7042.

Figure 1 shows the structure of a Lower Order Tributary Unit (TU11) in an Administrative unit (AU3) structure. It is a SONET frame which is a block of 810 bytes put out every 125 µsec. It consists of 90 columns and 9 rows. This figure shows a Lower order (LO) VCG where the first three columns indicate Section Overhead (SOH) 101 and payload 102. Figure 1 shows path overhead (POH) bytes 103 in the payload 102.

Figure 2 shows the structure of a Higher Order Tributary Unit (VC3) in an AU3 Structure. It is a SONET frame which is a block of 810 bytes put out every 125 µsec. It consists of 90 columns and 9 rows. This figure shows a Higher Order (HO) VCG where first three columns indicate section overhead (SOH) 201 and the 4th column comprises path overhead (POH) byte 203 in the payload 202.

The different types of containers are explained herein is to show that since the bytes available for the payload differ depending on the mode and size of the Tributary Units  it is important that the VCAT design be able to handle an arbitrary multiplexing structure. Thus  some Container can contain TU11 tributaries and some other TU12 tributaries and other can even be higher-order tributaries. Of course  as defined in the G.707 standard  Virtual Concatenation makes a Virtual Concatenation Group (VCG) by using member Tributary Units that are of the same granularity.

Figure 3 shows an STM channel. This channel is occupied by multiple VCG’s (302  304  303 and 305). For example let us say that VCG 302 is occupied by 4 TU12  VCG 304 is occupied by two VC4 and VCG 303 is occupied by three VC3. This helps in utilizing the entire bandwidth more efficiently.

It is customary to represent each member in an SDH stream by specifying the index it occupies at each level of the multiplexing structure. This is commonly called the A-k-l-m number where the “A” is the STM-1 number  the “k” the AU3/AU4 number  the “l” the TU2 number and the “m” the TU11 or TU12 in the TU2.

Figure 4 illustrates a functional block diagram of VCAT Receiver in accordance with an embodiment of the present disclosure.

The functional blocks of VCAT receiver comprises telecom logic block (402)  control history block (404)  write logic block (406)  and transmit control block (408).

The telecom logic block is configured to handle traffic on Synchronous Transport Module (STM-4). In one embodiment  STM-x operates at a predefined frequency and byte-wide data path to perform functions including but not limited to pointer-interpreter  path-overhead processing (extraction and alarm generation) as well as the virtual concatenation (VCAT) and link capacity adjustment scheme (LCAS) related processing. The telecom logic block is responsible for generating interrupts for various changes in alarms and other events that require a response from the method. The operation of this block is controlled on a per Tributary Unit (TU) basis.

The telecom logic is implemented on a time division multiplexing scheme (TDM) scheme. A central block in the telecom logic is responsible for generating the sequence of Tributary Unit addresses. The addresses are referred to as Aklm numbers and the sequence of the numbers is dependent on the multiplexing structure associated with STM-1.

In terms of Differential Delay compensation  the telecom block comprises of two interfaces namely payload interface and LCAS control interface. The payload interface carries the telecom data. The payload interface is the interface between the telecom logic and write logic. The LCAS control interface is used by the read side logic to determine the LCAS related information for each tributary unit.

Figure 5 illustrates a block diagram showing write process in accordance with an embodiment of the present disclosure.

The structure of the write logic consists of a TDM scheme running at 77 MHz that writes the bytes into a double-buffered transmit-page memory. Each page consists of 16 bytes and for each tributary unit  there is an active page and a backup page. Whenever  16 bytes are received for a tributary unit  a request is generated to write the page into external memory and at the same time the active page for this TU is swapped.

The write to external memory must be completed before another page is written to that memory. The rate of write requests varies depending on the “mode” of the tributary unit. However  the sequence of requests is arbitrary depending on the configuration of virtual concatenation groups. The writes to external memory happen periodically. Therefore  the write logic is configured such that the lower-order requests do not stall a higher-order request. This is accomplished by separating the requests into First-in First-Out (FIFO’s) based on the TU granularity and servicing the ones that request with highest priority. This is done in order to avoid page buffer from overflowing.

The state machine of write logic works on the basis of incoming frame number. It detects the start of a 2 ms boundary based on a transition of the frame number.

The addressing of pages in external memory is accomplished using the following method. The accesses to external RLDRAM occur in fixed size bursts of 16 bytes while the number of bytes in a frame for all the modes is not a multiple of 16 bytes. This results in pages not being aligned to a frame start on successive frames. Hence  the frame number cannot be used as part of the address. However  the higher order (HO) VCAT frame is 16-frames and it is guaranteed to have good alignment at every 2milli-second boundary. The address is therefore a combination of the 2 milli-second count and the running page number in that frame. The end-of a frame is therefore signaled when the last page that ends in that frame is completed. Figure 6 shows the page and frame alignment with the shaded boxes representing the “last_page” in the frame.

On completion of 16 bytes of writing  a request is generated to transfer the written page to external memory (502). The request is a vector of information that can be used to construct the external address. The request consists of vcg  aklm  page_cnt  active_page  tu_mode  and frame_number. An asynchronous FIFO is used to transfer the request to the mtc_clk domain (504).

The time taken to accumulate 16 bytes of data for each tributary unit is widely different. Also  the order in which the page requests are generated is arbitrary  being a function of the multiplexing structure and the configuration. Having a single FIFO for the write requests will not be sufficient since many requests for lower-order VCs may be present between two requests for a higher capacity tributary unit. This will exceed the time-critical service of higher-order  and would require a design that stores multiple pages for a TU  increasing the memory required. To ensure that each tributary unit has storage of only 2 pages  it is essential that the requests be serviced at a rate that is inversely proportional to the time difference between successive requests.

In an embodiment of the present disclosure  there are separate request FIFOs for each VC type request and these are serviced in strict-priority  with VC4 having the highest priority. The present disclosure comprises of three sets of FIFO’s (506)  one for VC4 requests  one for VC3 requests  and the third for the lower capacity requests  TU11 and TU12. As requests are generated  they are dispatched to the appropriate FIFO and the three FIFO’s are serviced in strict priority (508).

A request service logic (510) is triggered whenever one of the request FIFO’s has a valid entry. The highest priority FIFO is read and the address is given to the controller of the memory. Simultaneously a read to the page memory using the page address is triggered.

The state information for each tributary unit consists of various parameters. In one embodiment  one output of the state machine is the local address to the page memory consisting of the aklm  the active-page  and the byte number. The addressing of the page-memory is done in k-a-l-m order to reduce the memory required. In one embodiment  k has a range of 0  1  2 and so we can save address space if it is in the MSB location of the address.

Table 1 illustrates external memory addressing scheme in accordance with an embodiment of the present invention.
Mode Page range 18- 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VC4 0-2339 ms2_cnt A page_cnt[11:0]
VC3 0-755 ms2_cnt A K page_cnt[9:0]
TU2 0-105 ms2_cnt A K L page_cnt[6:0]
TU12 0-31 ms2_cnt A K L M page_cnt[4:0]
TU12 32-33 ms2_cnt A K L 1 1 M page_cnt[2:0]
TU11 0-24 ms2_cnt A K L N page_cnt[4:0]

Table 1

The external address used for the data is determined by mode  page count  2 milli-second count and the TU number. The request FIFO stores the external address as well as the local page address from the page-memory where the data will be read from. There are three request FIFOs  one for VC4 requests  one for VC43 requests and the third for lower order (LO) requests (TU2  TU11 and TU12). The appropriate request FIFO is written depending on the mode of the request.

The table describes how the bits in the external address of a page are determined. To track the different frames of data the 2 milli-second count is the MSB of the addresses. Then  the memory is segregated as per the TU numbering using only as many bits as required for that mode. Further  the 34 pages of TU12 are mapped. Since M is in the range 0-2  the remaining space (where those bits evaluate to 3) is used to store the 2 remaining pages (3 bits actually could store 8 pages – total of 40 but there are only 2 more pages once the first 32 is stored as per the first TU12 row).

Table 2 illustrates addressing scheme for control history block in accordance with an embodiment of the present disclosure.

TU Mode Address Bits of the LCAS history
10 9 8 7 6 5 4 3 2 1 0
Higher Order A K 0 0 ms2_cnt[4:0]
Lower Order A K L M or N ms2_cnt[4:3]

Table 2

The control history block (404) is an integral part of the differential delay compensation since it stores the LCAS information associated with a frame number. The LCAS information changes only at 2 ms boundaries for higher order and 16 ms boundaries for lower order. With 64 ms of differential delay compensation supported on TR03  upto 16 LCAS frames of control information should be stored for each Higher-order TU  and 4 LCAS frames should be stored for lower order TU’s. The addressing of the RAM is therefore mode dependent with the addressing scheme as illustrated in Figure 6.

In the transmit control block  the read side reads from external memory  the pages for the various members belonging to a VCG and interleaves the bytes based on the sequence number and whether the member is carrying traffic. The reads are for a frame number less than the most-delayed frame number update. When the data for a frame is read out and a new update is not yet signaled by the write side  the reading is to be stalled.
The functionality of transmit control block is divided into three modules comprising top level logic  per STM4 logic  and per VCG logic.

Per STM 4 Logic: The reads from external memory use a port on the rldram_mtc block that provides an STM4 rate bandwidth guarantee. There are many VCG’s that have members in each STM4 and the logic in per STM4 logic block is responsible for ensuring that the memory requests are placed in a fair and efficient manner. The requests are made in round-robin manner for the ports that have pending reads. The reads for a VCG are done in cycles and the read-machine in each STM4 is triggered by the per-VCG controller. This logic also is responsible for stopping the reads and starting them in co-ordination with the frame number communicated by the write-logic. The STM4 logic also communicates to the per-VCG logic indicating the end of a 2ms boundary based on the number of pages read.

Per VCG Logic : Each VCG has its own controller that handles the double-buffering of the read pages. The per VCG logic module performs hand-shaking with the multiple STM4 read logic blocks to ensure that a cycle of requests for all the members has been issued before the swapping of the active buffer for the writing is carried out. At the end of a 2ms boundary  the VCG logic clears the page-memory so that there is no old valid flags in the page memory. There VCG logic also interleaves the pages for the different members into a per-VCG stream. These streams are interleaved at the top level.

The updates of the completion of the most-delayed frame for each VCG are received by the update logic of the top level logic. Since a VCG can map across multiple STM4’s  the most-delayed member across all the STM4’s is found by a TDM state machine to share the logic required for the comparison of the frame numbers. The updates are sequential with no simultaneous updates from the multiple STM4’s. Once a certain number of updates have been received for a given VCG  the read state machine for a VCG is triggered at the start of a LCAS frame boundary (2 ms boundary for HO and 16ms boundary for LO).

The end-of-frame updates received from the write side from the multiple STM4’s  i.e. from multiple TU’s after the most-delayed computation is moved to FPGA  is compared to determine till where it is safe for the read side to read. The read process is performed until the most delayed member has the least frame number. Subsequent reads are stalled until an update is received informing that more data has been received and reading can be performed.

Figure 7 illustrates the update logic that tracks the most-delayed frame per VCG. In one embodiment  a 125 µsec signal called “frm_time” is received from the telecom logic block (402)  derived from the frame pulse that toggles every 125 µsec. For the first update  the updated frame number is loaded in RAM  and on every subsequent update in the same frame time  if the frame number being signaled is smaller  the cur_frm is replaced. Thus  at the end of the frm_time  the most-delayed update is received in that 125 µsec. At the first update of the next value of frm_time  this is written to another RAM and is used as the value for the next 125 µsec to determine till where the read can progress to.

The read side of the most-delayed RAM (MD_RAM) is the read_state address. This is the port which is granted a read request or being polled during the time when there is no grant. One of the outputs of this logic is a “rd_initiated” vector which tells us that for which VCGs updates has been received and crossed LCAS boundary that enables the triggering of the read control for that VCG.

The present disclosure is not to be limited in terms of the particular embodiments described in this application  which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its spirit and scope  as will be apparent to those skilled in the art. Functionally equivalent methods and devices within the scope of the disclosure  in addition to those enumerated herein  will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims  along with the full scope of equivalents to which such claims are entitled. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only  and is not intended to be limiting.

While various aspects and embodiments have been disclosed herein  other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting  with the true scope and spirit being indicated by the following claims.

We claim:

1. A method for implementing Virtual Concatenation (VCAT) receiver over SDH network for receiving data streams  said method comprising steps of:
extracting control information from SDH stream for each Tributary Unit (TU) and assembling data bytes of that TU using the extracted control information into fixed size pages with well-defined starting position by writing the data bytes into an active page of double buffered receive-page memory 
generating a signal to write the completed page to external memory  upon completion of writing of fixed size bytes into the active page for each TU; and simultaneously swapping the active page for this TU of the receive-page memory for assembly of subsequent data bytes 
writing the completed page for each TU into an external memory  common to all TU’s  in an order such that writing for each TU is completed prior to the assembly of the next page for that TU;
generating a signal to read one fixed-size page from the external memory for all the TU’s for a Virtual Concatenation Group (VCG)  upon completion of writing of all TU’s that have the same offset from the well-defined starting position and belonging to the VCG;
reading the fixed-size pages for all TU’s of a VCG from the external memory and storing them in an internal double-buffered transmit-page memory and generating a signal to interleave the stored pages once all TU’s of a VCG have been read from the external memory; and
constructing the data stream for each VCG by interleaving the bytes held in the stored fixed-size pages in the transmit-page memory based on the control information for each TU of the VCG  while simultaneously reading the next fixed-size page from external memory into other page of the double-buffered transmit-page memory.

2. The method as claimed in claim 1  wherein each SDH frame of a Tributary Unit (TU) is tagged with frame number and a sequence number indicating its position in the interleaving of the members of the virtually concatenated group (VCG).

3. The method as claimed in claim 1  wherein the control information comprises Tributary Unit (TU) addresses  interrupts for various changes in the alarms of the network  link capacity adjustment scheme (LCAS) information and wherein said LCAS information comprises sequence number  control word and group identifier bit of SDH frames.

4. The method as claimed in claim 1  wherein each page of the double buffered page memory consists of predetermined number of bytes and each TU consists of an active page and a backup page  wherein the active page is swapped when the signal for writing the page to external memory is generated.

5. The method as claimed in claim 1  wherein the address of a fixed-size page in external memory is determined in a manner that the storage allocated to different TU’s do not overlap  said address is computed on the basis of the control information in the TU  the TU identifier bits  and the offset from the well-defined starting position.

6. The method as claimed in claim 1  wherein the signals to write the completed pages to external memory are acted upon in strict priority of the bandwidth capacity of the TU they represent to avoid stalling higher bandwidth requests by large number of lower bandwidth requests.

7. The method as claimed in claim 6 is implemented by having multiple First In First Out (FIFO) queues  one for each unique bandwidth granularity of the TU’s  and storing the signals to write the completed pages to external memory into the corresponding bandwidth FIFO  and serving the requests in a FIFO only if there are no requests in FIFOs of higher bandwidth.

8. The method as claimed in claim 2  wherein the first frame number update in most delayed computation interval is updated as smallest frame in the memory and further updates within the interval are compared to determine the smallest frame number  if further updated frame number is smaller than the stored smallest frame number in the memory then the memory is updated with the new smallest frame number  and thereafter the read side is updated with stored smallest frame number at the end of the most-delayed computation interval for triggering the read of bytes from external memory for the VCG till the updated frame number.

9. The method as claimed in claim 1  wherein the fixed-size page read from the external memory is stored into the transmit-page memory for that VCG at an address corresponding to the sequence number of that TU in the VCG  and the data bytes are stored with an additional valid bit for each byte and said valid bit indicates that the TU’s data should be interleaved into the VCG data stream.

10. The method as claimed in claim 1  wherein interleaving the pages read from the external memory has to be completed before pages are read into the same location in the transmit-page memory.

11. A VCAT receiver for receiving data streams over SDH network  comprising:
a. Telecom Logic block to generate control information 
b. Control History block stores the VCAT and LCAS information received form the telecom logic block and communicates this to the Transmit Control to effect the proper recovery of the data stream 
c. write logic block to write the received data bytes into a double buffered receive page memory and to generate a write signal for writing the page into external memory and to generate read signal to initiate reading of data bytes from the external memory 
d. Transmit Control block for each VCG  to read fixed-size pages from the external memory upon receiving read signal and interleaving the data bytes based on the sequence numbers and member’s data carrying status.

12. The VCAT receiver as claimed in claim 11  wherein the telecom logic comprises payload interface for carrying telecom data  pointer-interpreter  path overhead processing  LCAS control interface to provide LCAS information to the Transmit Control block.

13. The VCAT receiver as claimed in claim 11  wherein the Transmit block comprises
a. Common Transmit Controller block that provides to each Transmit Control block the frame number up to which data from external memory should be read 
b. at least one External Memory Access sequencer to ensure that the memory requests are placed in prerequisite order; and to control and coordinate external memory read operation with per VCG Transmit Control logic.

14. The VCAT receiver as claimed in claim 11  wherein the interleaving logic reads byte(s) from the transmit-page memory for each of the members in a sequence and packs the bytes into a word depending on the valid bit associated with each byte.

15. The VCAT receiver as claimed in claim 11  wherein the interleaving Logic for a High Speed port uses the write/read port along with read-only port to increase the read bandwidth.

16. The VCAT receiver as claimed in claim 11  wherein interleaving logic is shared among several low-speed ports and the ports are being interleaved based on the availability of data to be interleaved.