TECHNICAL FIELD:

The present disclosure is related to semiconductor processing. Specifically the disclosure
relates to semiconductor-metal interfaces as embodied by Schottky contacts in diodes,
field effect transistors and Schottky source/drain MOSFETs for passivation and
modifying interface/contact properties.

BACKGROUND:

The scaling of the Metal – Oxide semiconductor Field effect Transistor (MOSFET) to
ever smaller dimensions is central to the Information Technology revolution. This has
however resulted in several problems which limit the performance of such transistors
especially at very small length scales. Nanometer scale Metal Oxide Semiconductor Field
Effect Transistors (MOSFETs) suffer from significant drive current reduction due to
mobility degradation, parasitic source/drain (S/D) resistance and a host of other issues
collectively known as Short Channel Effects (SCE). While Silicon has traditionally been
used as the substrate for realizing MOSFETs, Germanium has emerged in recent times as
an alternative channel material to address mobility degradation. The oxides (GeOx) of
Germanium are inherently unstable and hence deposited dielectrics need to be used. The
resulting interface however has a large number of traps degrading mobility. Sulfur
passivation treatment has been explored to reduce the density of oxide – semiconductor
interface states and good MOS capacitors have been demonstrated using this approach.
Sulfur passivation has also been explored in compound semiconductor devices to reduce
the midgap state density at the interface.
Parasitic resistance and SCE however continue to pose problems for scaling of the
MOSFET and is a topic of contemporary research. At present, state of the art transistors
are realized using the traditional method of implanting pentavalent impurities
(Phosphorus, Arsenic, Antimony) to realize n-type regions or trivalent impurities (Boron,
Aluminum, Gallium or Indium) to realize p-type regions, followed by relatively high
temperature (> 600°C) anneals to form the source/drain regions. But due to solid
solubility limits of the dopants in Germanium, there is a lower limit on the resistance that
can be achieved which is detrimental to the performance of very small transistors. There
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is also a lower limit on the depth of the source/drain junctions that can be achieved by
this approach, resulting in poor protection against SCE. To address the problem of
parasitic resistance the Schottky source/drain MOSFET is a promising solution. Here the
traditional doped source/drain regions are replaced with metals which are carefully
chosen to provide the required electrical properties such as barrier height. This approach
however is limited to only the p-channel transistor, due to the Fermi-level Pinning
problem. Fermi-level pinning is a phenomenon where band alignment between the
semiconductor and the electrically active material, specifically metals in case of Schottky
contacts, occurs very close to the Valence band edge of Germanium. The result is a large
electron barrier height which is independent of the work function of the metal in contact.
For this reason metals with larger work functions are preferred and only p-channel
devices have been realized. Nickel and Platinum Germanides/Silicides have traditionally
been used as the materials for realizing the p-type Schottky source drain regions. Recent
efforts have also focused on engineering the barrier height of the Silicide/Germanide
source/drain regions through dopant segregation techniques or implant to silicide process
whereby low resistance contacts may be achieved. This approach however does not yield
complementary behavior required for realizing Schottky source/drain transistors. The
other limitations of the existing technologies include-
1. Parasitic resistance of traditional source/drain region does not scale because of the
solid solubility limit of dopants in Germanium. Hence the dopant segregation technique
does not yield good results when used on Germanium.
2. The problem of Fermi-level Pinning results in rectifying contacts to n-type substrates
and ohmic contacts to p-type substrates, independent of the metal used. Thus Schottky
S/D junction MOSFETs are at present, limited to p-channel devices due to Fermi level
pinning.
3. High performance n-channel transistors have not been realized on Germanium.
4. Implant- to - silicide process results in low resistivity ohmic contacts to both n & ptype
substrates and cannot be used to realize Schottky source/drain regions.
Complementary behavior cannot be achieved. Sulfur is implanted in high doses which
introduces a high density of defects in the single crystal substrate.
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5. Sulfur passivation of Germanium has been explored for reducing the density of trap
states at the Germanium High-k dielectric interface. This however is reported only for
one type of substrate, namely, n-type Germanium. No studies have been done on the
effect of passivation at semiconductor-metal interfaces.
Thus there exists the need to come up with a method whereby it is possible to realize
good rectifying contacts to p-type Germanium substrates which simultaneously show
good ohmic contact to n-type substrates. Such a technique creates the possibility of
realizing n-channel Schottky source/drain transistors and thereby Germanium Nano
CMOS circuits with Schottky junctions. This may also be useful for other semiconductor
devices/structures on a variety of other substrates including Silicon, where such contacts
are employed.

STATEMENT OF DISCLOSURE:

The present disclosure provides a method for passivating semiconductor-metal interface
with sulfur, comprising acts of treating the semiconductor with an acid mixture; cleaning
the acid treated semiconductor with water; coating the cleaned semiconductor with the
sulfur; washing the sulfur coated semiconductor with water; and depositing the metal on
the washed sulfur coated semiconductor to obtain passivated semiconductor-metal
interface with sulfur; a passivated semiconductor-metal interface with sulfur obtained
using the method of present disclosure; a semiconductor device comprising passivated
semiconductor-metal interface with sulfur and a method of using a semiconductor device
comprising passivated semiconductor- metal interface with sulfur, said method
comprising act of conjugating said device in a gadget in need thereof for its working.
BRIEF DESCRIPTION OF FIGURES:
The disclosure itself, however, as well as a preferred mode of use, further objectives and
advantages thereof, will best be understood by reference to the following detailed
description of an illustrative embodiment when read in conjunction with the
accompanying figures. One or more embodiments are now described, by way of example
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only, with reference to the accompanying drawings wherein like reference numerals
represent like elements and in which:
Figure 1: shows cross-sectional view of Schottky diode with interface modified using the
process outlined.
Figure 2a: shows Current – Voltage measurements for Schottky diodes realized on both
untreated and surface modified n-type Germanium substrates.
Figure 2b: shows Current – Voltage measurements for Schottky diodes realized on both
untreated and surface modified p-type Germanium substrates.
Figure 3: shows the pictorial depiction of the transistor with modified semiconductormetal
interface, wherein 1 and 2, represents metal source/drain regions, 3 represents gate
stack, 4 represents interfacial layer introduced using passivation treatment and 5
represents semiconductor substrate.
Figure 4: shows barrier heights for Schottky contacts with and without passivation,
plotted against the ideal metal work functions. The best slope has a value of 0.95, as
shown by the dotted line.
The figures depict embodiments of the disclosure for purposes of illustration only. One
skilled in the art will readily recognize from the following description that alternative
embodiments of the structures and methods illustrated herein may be employed without
departing from the principles of the disclosure described herein.

DETAILED DESCRIPTION OF DISCLOSURE:

The present disclosure is in relation to a method for passivating semiconductor-metal
interface with sulfur, comprising acts of
a) treating the semiconductor with an acid;
b) cleaning the acid treated semiconductor with water;
c) coating the cleaned semiconductor with the sulfur;
d) washing the sulfur coated semiconductor with water; and
e) depositing the metal on the washed sulfur coated semiconductor to obtain
passivated semiconductor-metal interface with sulfur.
6
In another embodiment of the present disclosure, the semiconductor is selected from a
group comprising p-type and n-type semiconductors.
In still another embodiment of the present disclosure, the semiconductor is in a form of
single crystal wafer.
In yet another embodiment of the present disclosure, the metal is selected from a group
comprising Aluminum, Zirconium, Tungsten, Tantalum, Nickel, Platinum and a metal
with low work function.
In yet another embodiment of the present disclosure, the acid is selected from a group
comprising Hydrochloric acid, Hydrobromic acid, Hydrofluoric acid and mixture thereof.
In yet another embodiment of the present disclosure, the mixture comprises acids
Hydrochloric acid and Hydrobromic acid in ratio ranging from about, 0.1:0.1 to about
1:1, preferably in the ration of about 1:1.
In yet another embodiment of the present disclosure, the water is in deionized form.
In yet another embodiment of the present disclosure, the sulfur is coated using solution
selected from a group comprising Ammonium sulphide solution and Ammonium
polysulfide solution.
In yet another embodiment of the present disclosure, the Ammonium sulphide solution
and Ammonium polysulfide solution are the solutions diluted with deionized water.
In yet another embodiment of the present disclosure, the coating is carried out at a
temperature ranging from about 40°C to about 100°C, preferably about 50°C.
In yet another embodiment of the present disclosure, the coating is carried out for a
period ranging from about 3 min to about 10 min, preferably about 5 min.
In yet another embodiment of the present disclosure, the metal is deposited by a process
selected from a group comprising sputtering, thermal evaporation, electron beam
evaporation, Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE),
Atomic Layer Deposition (ALD) and Gas Injection System (GIS).
The present disclosure is also in relation to a passivated semiconductor-metal interface
with sulfur.
The present disclosure is also in relation to a semiconductor device comprising passivated
semiconductor-metal interface with sulfur.
7
In yet another embodiment of the present disclosure, said device is selected from a group
comprising diodes, transistors, resistors, inductors and capacitors.
The present disclosure is also in relation to a method of using a semiconductor device
comprising passivated semiconductor- metal interface with sulfur, said method
comprising act of conjugating said device in a gadget in need thereof for its working.
In yet another embodiment of the present disclosure, the gadget is selected from a group
comprising electric, electronic and optoelectronic devices.
The present disclosure is a method directed at modifying the interface between a
semiconductor and an electrically active material by introducing an interfacial layer
containing sulfur. This interfacial layer results in improvement in the properties of the
interface such as enhanced carrier mobility, complete/partial passivation of interface/trap
states which otherwise cause degradation in electrical performance.
Specifically discussed herein is a desirable modification in the interface between
Germanium and metals, resulting from the method. The method discussed herein is
applicable to any semiconductor material. The disclosure also does not restrict to any
particular crystal orientations. It may be applied to <100>, <111>, <110> or any other
orientation as the case may be. The method discussed is also independent of substrate
doping type or concentration. It is also applicable in general to any semiconductor
structure including regions within integrated circuits or optoelectronic devices (e.g. Solar
cells, Light Emitting Diodes) where interface between metal and semiconductor may be
present.
The term "interface" as used herein refers to the region (1, 2 or 3-dimensional as the case
may be) of contact between two or more materials. In general this region may be located
anywhere within the physical boundaries of the overall structure and is not restricted to
just the surface of any individual material in contact.
8
The method is illustrated using the example of Germanium Schottky diodes. The
semiconductor structure is constructed as shown in Fig. 1. In the figure-1, 1 represents
metal deposited to make contact with the interface layer, 2 represents interfacial layer
formed after the treatment and 3 represents the germanium substrate.
The advantage of the present disclosure includes modification in the interface to achieve
contact behavior in accordance to theoretical prediction for ideal semiconductor-metal
contacts according to the Schottky – Mott theory. The figure 4 clearly shows that the
technique restores the barrier heights to values close to the ideal line predicted by
Schottky – Mott theory (depicted by the line with slope = 1). In the figure 4, the open
circles show the barrier height which is ordinarily obtained for a metal semiconductor
contacts fabricated on Germanium without passivation. The stars indicate the new
modified barrier height obtained through the passivation technique of present disclosure.
Providing an interfacial layer containing sulfur at the contact region between two
materials can also have other beneficial properties such as protection from detrimental
effects of exposure to atmosphere. The presence of oxides of Germanium at the interface
is undesirable as such oxides are unstable, both chemically and thermally, and can result
in degradation of the device over time leading to reliability problems. The inclusion of a
layer incorporating sulfur can prevent the adsorption of oxygen and the formation of
Germanium oxides, even if the surface is left exposed to an oxygen containing
atmosphere.
Modern MOSFETs typically contain a layer of High-k dielectric at the interface to form
the Gate, which is the control terminal of the device. High-k dielectrics are always
deposited using techniques such as Atomic Layer Deposition (ALD) or other Chemical or
Physical Vapor Deposition (CVD/PVD) methods. Deposited dielectrics typically have
poor interfaces with the semiconductor and tend to accumulate a large concentration of
traps and dangling bonds which are detrimental to the flow of charge carriers in a device
such as the MOSFET. The inclusion of an interfacial layer realized using the described
method can alleviate such problems.
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Finally the results discussed herein point to the possibility of realizing a Schottky
source/drain n-channel MOSFET. Here the interface between a low work function metal
used for source/drain contact and the semiconductor is passivated by the above method
resulting in a suitably low barrier height to the inverted channel while retaining its
rectifying characteristic to the substrate.
The resultant modification in the semiconductor-metal contact at the source/drain regions
will yield a device with superior performance than existing solutions.
Although the current disclosure of Fermi level de-pinning in Germanium schottky
contacts is illustrated with sulfur passivation, the other chalcogenide family elements
namely selenium and tellurium may also be used in place of sulfur.
The technology of the instant Application is elaborated in detail with the help of
following examples. However, the examples should not be construed to limit the scope of
the disclosure.
Example-1: The process flow for realizing Sulfur passivated diodes is detailed below:
A Germanium substrate is first treated with a mixture of Hydrochloric and Hydrobromic
acids and subsequently immersed in a solution of Ammonium Sulfide at a temperature of
50°C for 5 minutes to yield a layer containing sulfur on the surface of Germanium. This
is followed by the deposition of a metal layer on top by sputtering, opposite the
semiconductor as depicted in Fig. 1.
The semiconductor devices, diode thus realized are characterized by measuring the
current as a function of the voltage, as depicted in Fig. 2a and 2b. Each figure shows two
pairs of current – voltage curves corresponding to contacts realized on bare Germanium
and sulfur passivated Germanium surface respectively.
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The figures correspond to two different substrate types, viz., n-type and p-type
Germanium. It is shown that Aluminum and Zirconium metal contacts to n-type
Germanium (Fig. 2a) show reversal of behavior from Rectifying to Ohmic and vice-versa
on p-type Germanium (Fig. 2b) after the Germanium substrate is subjected to the
passivation treatment described.
Example 2: The step wise process flow for realizing Sulfur passivated Schottky
Source/Drain transistors is detailed below:
Step 1: The substrate, Single crystal 100 oriented Germanium, is cleaned using a 1:1
mixture of HBr and HCl acids followed by a rinse in De-ionized water. The substrate is
then dried by blowing Nitrogen.
Step 2: The substrate is then treated in Ammonium sulfide solution (concentration of
40% by wt.) at 50°C followed by rinse in De- ionized water and Nitrogen blow dry.
Step 3: The passivated Germanium substrate is then loaded into an Atomic layer
deposition system for depositing a suitable thickness of dielectric (Hafnium oxide in a
typical embodiment).
Atomic Layer Deposition (ALD) is the preferred method of deposition for dielectrics as it
provides high quality dielectrics and has a lower thermal budget. But other methods such
as thermal oxidation, sputtering or evaporation may also be used to realize a good
dielectric for the gate.
The passivation provided in step 2 serves to reduce the interface trap density at the
dielectric – semiconductor interface to provide good gate control for the Metal-insulatorsemiconductor
field effect transistor (MISFET).
Step 4: This is then followed by deposition of a metal layer on the dielectric and
patterning through lithography and etching through dry/wet etch or a combination of
both, to realize the gate conductor layer. In special cases heavily doped Polysilicon is
used instead of metal to realize the gate conductor.
Step 5: Later a thin layer of insulator through a Chemical Vapor deposition (CVD)
process to provide a conformal deposition on the gate metal/conductor is deposited.
Variants of this process such as Plasma Assisted/Enhanced CVD are preferable as the
process can be carried out at lower temperatures. Although the particular process outlined
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here is CVD any other process which will provide a conformal coating of insulator on the
gate conductor can be used.
Step 6: This is then followed by patterning through lithography to define windows in the
dielectric followed by a dry/wet etch or a combination as the case may be to realize the
“Gate Stack”. The gate stack will consist of the gate dielectric, gate conductor and the
insulator layer deposited in step 5 which serves as a “Spacer” to provide insulation
between the gate and source/drain metals.
Step 7: Subsequently the Germanium substrates with the Gate Stack realized as detailed
above are treated again in Ammonium Sulfide solution as described in step 2 to passivate
the source/drain regions opened in steps 3 to 5. This repetition is helpful as the sulfur
passivation provided through step 2 is likely to degrade due to subsequent processing in
steps 3 to 5.
Step 8: This is then followed by the deposition of the required metal; say Aluminum or
Zirconium, to realize the Schottky Source/Drain regions. The thickness of the deposited
metal is a critical parameter that needs to be monitored carefully. It has to be thinner than
the gate stack to prevent the bridging (shorting) of the gate and source/drain metals, at the
same time should be thick enough to prevent the degradation of the contact with time. For
this reason it is preferable that the gate metal/conductor deposited and patterned in step 4
is sufficiently thick.
Steps 1 to 8 only serve to exemplify a typical process flow to realize Sulfur Passivated
Schottky source/drain transistors. Variations and additions to the above process flow will
be apparent to anyone skilled in the art. The process can also be easily extended to other
semiconductors such as Silicon or Gallium Arsenide to name a few. The process listed
above is not specific to the metals listed here for the Schottky source/drain (Aluminum
and Zirconium) and it can be easily extended or modified to accommodate any other
metal as desired.
Figure 3, provides the pictorial depiction of the transistor with modified semiconductormetal
interface, wherein 1 and 2, represents metal source/drain regions, 3 represents gate
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stack, 4 represents interfacial layer of sulfur introduced using passivation treatment
outlined in the present disclosure and 5 represents semiconductor substrate.
While various aspects and embodiments have been disclosed herein, other aspects and
embodiments will be apparent to those skilled in the art. The various aspects and
embodiments disclosed herein are for purposes of illustration and are not intended to be
limiting, with the true scope and spirit being indicated by the following claims.
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WE CLAIM:

1. A method for passivating semiconductor-metal interface with sulfur, comprising
acts of
a) treating the semiconductor with an acid;
b) cleaning the acid treated semiconductor with water;
c) coating the cleaned semiconductor with the sulfur;
d) washing the sulfur coated semiconductor with water; and
e) depositing the metal on the washed sulfur coated semiconductor to obtain
passivated semiconductor-metal interface with sulfur.
2. The method as claimed in claim 1, wherein the semiconductor is selected from a
group comprising p-type and n-type semiconductors.
3. The method as claimed in claim 1, wherein the semiconductor is in form of single
crystal wafer.
4. The method as claimed in claim 1, wherein the metal is selected from a group
comprising Aluminum, Zirconium, Tungsten, Tantalum, Nickel, Platinum and a
metal with low work function.
5. The method as claimed in claim 1, wherein the acid is selected from a group
comprising Hydrochloric acid, Hydrobromic acid, Hydrofluoric acid and mixture
thereof.
6. The method as claimed in claim 5, wherein mixture comprises acids Hydrochloric
acid and Hydrobromic acid in ratio ranging from about, 0.1:0.1 to about 1:1,
preferably in the ratio of about 1:1.
7. The method as claimed in claim 1, wherein the water is in deionized form.
8. The method as claimed in claim 1, wherein the sulfur is coated using solution
selected from a group comprising Ammonium sulphide solution and Ammonium
polysulfide solution.
9. The method as claimed in claim 8, wherein the Ammonium sulphide solution and
Ammonium polysulfide solution are the solutions diluted with deionized water.
14
10. The method as claimed in claim 1, wherein the coating is carried out at a
temperature ranging from about 40°C to about 100°C, preferably about 50°C.
11. The method as claimed in claim 1, wherein the coating is carried out for a period
ranging from about 3 min to about 10 min, preferably about 5 min.
12. The method as claimed in claim 1, wherein the metal is deposited by a process
selected from a group comprising sputtering, thermal evaporation, electron beam
evaporation, Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy
(MBE), Atomic Layer Deposition (ALD) and Gas Injection System (GIS).
13. A passivated semiconductor-metal interface with sulfur obtained using the
method as claimed in claim 1.
14. A semiconductor device comprising passivated semiconductor-metal interface
with sulfur.
15. The semiconductor device as claimed in claim 14, wherein said device is selected
from a group comprising diodes, transistors, resistors, inductors and capacitors.
16. A method of using a semiconductor device comprising passivated semiconductormetal
interface with sulfur, said method comprising act of conjugating said device
in a gadget in need thereof for its working.
17. The method as claimed in claim 16, wherein the gadget is selected from a group
comprising electric, electronic and optoelectronic gadgets.

Dated this 20th day of August, 2010

Signature:
Name: K. Rama
Of K & S Partners
Agent for the Applicant

To
The Controller of Patent
The Patent Office, at Chennai