DESC:TECHNICAL FIELD OF THE INVENTION
[0001] The present disclosure/invention relates in general to Wireless communication and more particularly to a method and system to support wideband frequency hopping systems using RF sampling ADC and DAC.
BACKGROUND OF THE INVENTION
[0002] Generally, a frequency hopping (FH) is a spread spectrum technology mainly used for secure tactical communication. It provides effective anti-jamming capability. Traditionally, analog mixers are used for frequency hopping. Recently, the polyphase channelizer approach has become the choice of efficient implementation of FH in the digital domain.
[0003] The anti-jamming performance of FH depends on hopping bandwidth and hops rate. More the hopping bandwidth, better is the FH performance. As frequencies vary over a wider band, it is difficult to jam. Digital implementation of FH over a wideband is difficult because of higher sampling rates. As hopping bandwidth increases, sampling rates of direct RF ADC/DAC will also increase, requiring faster processing in digital domain.
[0004] Radio frequency (RF) sampling Analog-to-Digital Converter (ADC)/ Digital-to-Analog Converter (DAC) uses JESD interface for transferring the samples. JESD provides multiple samples in a single clock at a reduced clock rate. If only one sample out of multiple samples is considered due to high processing rate, then the signal aliases generating multiple signals at the transmit side. The same is applicable to the receive side also.
[0005] One of the prior art describes a method of frequency hopping supported by a base station having a broadband transceiver for GSM application. The method maps baseband output signals from a digital channelizer which represent physical channels to ones of digital signal processors representing logical channels and baseband input signals of a digital combiner to ones of logical outputs of digital signal processors according to a mapping signal. But this architecture differs widely from the current proposed one.
[0006] Therefore, there is a need in the art with a method and system to support wideband frequency hopping systems using Radio frequency (RF) sampling Analog-to-Digital Converter (ADC)/ Digital-to-Analog Converter (DAC) and to solve the above-mentioned limitations.
SUMMARY OF THE INVENTION
[0007] An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.
[0008] Accordingly, in one aspect of the present disclosure a method for processing wideband radio frequency (RF) signals is disclosed. The method includes receiving radio frequency (RF) signals in form of analog signals by an analog-to-digital converter (ADC) of a multistage polyphase channelizer. The method includes converting the received RF signals to digital signals by the ADC based on performing radio frequency sampling on the received radio frequency signals. Further, the method includes transmitting the digital signals from the ADC to a receiver path of the multistage polyphase channelizer. Furthermore, transmitting the digital signals to the receiver path includes routing the digital signals to at least a first stage and a second stage associated with a programmable logic device of the multistage polyphase channelizer. The digital signals are subjected to at least parallel processing and serial processing in the first stage and the second stage based at least on a first hop index and a second hop index for optimizing speed and number of resources, respectively.
[0009] Accordingly, in one aspect of the present disclosure a method for processing wideband radio frequency (RF) signals is disclosed. The method includes receiving digital signals by a baseband modulator of a multistage polyphase combiner. The method includes processing the digital signals by the baseband modulator to obtain a third output. Further, the method includes transmitting the third output from the baseband modulator to a transmitter path of the multistage polyphase combiner. Furthermore, transmitting the third output to the transmitter path includes routing the third output to at least a first stage and a second stage associated with a programmable logic device of the multistage polyphase combiner. The third output signals are subjected to at least serial processing and parallel processing in the first stage and the second stage based at least on a third hop index and a fourth hop index for optimizing number of resources and speed, respectively.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0010] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0011] Figure 1 shows a block diagram of half duplex system according to an exemplary implementation of the present disclosure/ invention.
[0012] Figure 2a shows a block diagram of Transmit Chain of the system and figure 2b shows a block diagram of Receive Chain of the system according to an exemplary implementation of the present disclosure/invention.
[0013] Figure 3 shows a block diagram of conventional N- channel Polyphase transmitter and receiver.
[0014] Figure 4 shows a block diagram of Conventional multistage polyphase channelizer.
[0015] Figure 5 shows a block diagram of proposed Multistage Polyphase Channelizer for Frequency Hopping (FH) application according to an exemplary implementation of the present disclosure/invention.
[0016] Figure 6 shows a block diagram of proposed Multistage Polyphase Combiner for Frequency Hopping (FH) application according to an exemplary implementation of the present disclosure/invention.
[0017] Figure 7 shows an overview of proposed Frequency Hopping (FH) scheme according to an exemplary implementation of the present disclosure/invention.
[0018] Figure 8 is a flow diagram depicting a method performed by the multistage polyphase channelizer for processing wideband radio frequency (RF) transceiver signals.
[0019] Figure 9 is a flow diagram depicting a method performed by the multistage polyphase combiner for processing wideband radio frequency (RF) transceiver signals.
[0020] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0021] The various embodiments of the present disclosure/invention describe about a method and system to support wideband frequency hopping systems using RF sampling ADC and DAC.
[0022] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0023] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently disclosure and are meant to avoid obscuring of the presently disclosure.
[0024] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0025] Frequency Hopping (FH) is a spread spectrum technology mainly used for secure communication. It provides effective anti-jamming capability. The anti-jamming performance of FH depends on hopping bandwidth and hops rate. More the hopping bandwidth, better the FH performance, as frequencies vary over a wider band, it is difficult to jam. Digital implementation of FH over a wideband is difficult because of higher sampling rates. As hopping bandwidth increases, sampling rates of direct RF ADC/DAC will also increase requiring faster processing in digital domain.
[0026] In order to effectively overcome the above-mentioned limitations, a parallel approach is taken instead of processing at a high sampling rate. This approach led to the novel invention of digital FH transmitter and receiver using multistage polyphase channelizer at the receive side and multistage polyphase combiner at the transmit side.
[0027] In order to handle the above issue, an architecture is proposed for a programmable device that can run at a lower rate compared to the ADC/DAC sampling rates using parallel processing. At the first stage of the multistage polyphase channelizer which has to run at the ADC sampling rate, is parallelized by the number of channels at that stage, in order to reduce the processing clock frequency in FPGA. Similarly, at the transmit side. Multistage implementation of polyphase channelizer/combiner also gives the advantage of better prototype low pass filter realization at each stage, improved selectivity and image rejection.
[0028] In the present invention architecture, a direct RF samples are considered without any pre filtration. The present invention architecture is very efficient for very high sampling rates of the order of few hundreds of Mega samples per second to Giga samples per second. Also, the present invention architecture has multiple stages of channelization and parallelism.
[0029] In the present invention architecture, the device can run at a lower rate compared to the ADC/DAC sampling rates using parallel processing at the first stage of multistage polyphase channelizer. Similarly, at the transmit side. So, the first/last stage of the multistage polyphase channelizer/combiner which has to run at the ADC/DAC sampling rate, is parallelized by the number of channels at that stage, in order to reduce the processing rate.
[0030] In one embodiment, the present invention provides a Multistage implementation of polyphase channelizer and combiner for frequency hopping over a wide RF band.
[0031] In one embodiment, the present invention provides parallel implementation of the first/last stage of channelizer/combiner to effectively reduce the processing clock rate in programmable devices.
[0032] In one embodiment, the present invention provides computation of only the required channel outputs at each stage of channelizer based on the hop frequency information thereby reducing the resources required.
[0033] In one embodiment, the present invention provides multistage implementation of polyphase channelizer also gives the advantage of better filter realization at each stage, improved selectivity and image rejection.
[0034] In another embodiment, the present invention relates to a method for processing of wideband RF transceiver signals using multistage polyphase channelizer and combiner.
[0035] In another embodiment, the present invention provides an efficient low power method of processing wideband RF transceiver signals using multistage polyphase channelizer and combiner.
[0036] In another embodiment, the present invention is used for Frequency hopping application over a wide RF band.
[0037] In another embodiment, the present invention provides efficient realization of prototype low pass filters at each stage, improved selectivity and image rejection.
[0038] In another embodiment, the present invention wherein in the receive path, the architecture is optimized for speed in the first stage and resource in the next stages and in the transmit path, the architecture is optimized for resources in the first and next stages and speed in the last stage.
[0039] Figure 1 shows a block diagram of half duplex system according to an exemplary implementation of the present disclosure/ invention.
[0040] The figure shows the block diagram of half duplex system. UI 101 is the user interface of the system through which data is interfaced to the system. 102 is the processing unit where Network and Media Access Control Address (MAC) layer protocols are run. The present invention applies for Time Division Multiple Access (TDMA) based MAC layer protocols where 1PPS synchronization 103 is required across different nodes in the network. The Time Division Multiple Access (TDMA) based hop index is provided by the MAC layer running in processing unit 102. The hop index is then mapped to channel index in Programmable logic device 104. The present invention of frequency hopping method for both transmitter and receiver run in Programmable Logic Device. The digital samples generated in the programmable logic device are then transferred to RF DAC 105 via JESD 204B interface. RF DAC 105 converts digital signal to RF analog signal. Power Amplifier (PA) 106 boosts the RF signal and transmitted to the free space through antenna 108 via TR switch 107. TR switch is required for half duplex communication. In the receive path the received RF signal from antenna is fed to Low Noise Amplifier (LNA) 109 followed by RF ADC 110. RF ADC 110 block converts analog RF signal to digital signal. The digital samples are sent to Programmable logic device 104 using JESD 204B interface. Received digital samples are processed in programmable logic device (PLD) and decoded data is sent to Processing unit and then to UI.
[0041] Figure 2a shows a block diagram of Transmit Chain of the system and figure 2b shows a block diagram of Receive Chain of the system according to an exemplary implementation of the present disclosure/invention.
[0042] The figure 2a shows the Transmitter chain and figure 2b shows the Receiver chain. The digital data 201 is given to Baseband modulator 202. The baseband modulator maps the digital data to baseband I, Q samples. The Input framer 203 forms the input to the combiner 1, 204, the combined output is fed to the combiner 2, 205. The final combined signal is converted to analog signal by RF DAC 206 followed by PA and antenna.
[0043] Received RF signal is converted to digital signal by RF ADC 207. These samples are fed to channelizer 1, 208 and the output of channelizer 1 is fed to channelizer 2, 209. Channel output selection 210 selects the required channel output which is demodulated back to digital data 212 by the baseband demodulator 211.
[0044] Polyphase channelizer has become the choice of efficient implementation of FH in the digital domain.
[0045] Figure 3 shows a block diagram of conventional N- channel Polyphase transmitter and receiver.
[0046] The figure shows the basic N channel polyphase transmitter and receiver. In the transmit path the baseband samples 301 are given to Inverse discrete Fourier transform 302, then polyphase N-path filter 303 and output commutator 304. The commutator output is given to RF DAC 305 for transmission. In the receive path the incoming ADC samples 306 are given to the input commutator 307 followed by polyphase N-path filter 308 and discrete Fourier transform 309.
[0047] Figure 4 shows a block diagram of Conventional multistage polyphase channelizer.
[0048] The figure shows conventional two stage polyphase channelizer, where 401, 404, 405, 406 are input commutator, 402, 407, 408, 409 are polyphase filter banks, 403, 410, 411, 412 are FFT blocks, 413, 414, 415 are the outputs of the second stage channelizer. Similarly, a two-stage polyphase combiner is the reverse of the channelizer.
[0049] Figure 5 shows a block diagram of proposed Multistage Polyphase Channelizer 500 for Frequency Hopping (FH) application according to an exemplary implementation of the present disclosure/invention.
[0050] The multistage polyphase channelizer 500 includes an analog to digital converter (ADC) 501. The radio frequency (RF) signals in form of analog signals are received at the ADC 501. The frequency of the RF signals received at the ADC 501 may be ‘fs’. The ADC 501 converts the received RF signals to digital signals based on performing radio frequency sampling on the received RF signals. Further, the digital signals are transmitted from the ADC to a receiver path of the multistage polyphase channelizer 500. In particular, the digital signals are transmitted to a programmable logic device 512 of the multistage polyphase channelizer 500. The programmable logic device 512 includes at least a first stage and a second stage.
[0051] The first stage of the programmable logic device 512 includes a series to parallel conversion block 502, a first channel polyphase filter bank 503, and a first fast fourier transform (FFT) block 504. The block 502 is configured to perform conversion of the digital signals (or ADC samples) from series to parallel. The first channel filter bank 503 run in parallel to handle or manage high sampling rate of the digital signals. Further, the first channel of the filter bank 503 may be referred to as ‘N1’. The first FFT block 504 is configured to select a channel among multiple channels (i.e., N1 channels) associated with the first channel polyphase filter bank 503 based at least on a first hop index. Thereafter, the first FFT block 504 computes a first output of required frequency for the selected channel. In other words, the first FFT block 504 outputs only required channel among multiple N1 channels based on the first hop index. The first output from the first FFT block 504 is ‘fs/N1’.
[0052] Further, the first output is transmitted to the second stage. Specifically, the first output is transmitted to a second channel polyphase filter bank 506 of the second stage from the FFT block 504 via an input commutator 505 of the second stage. The first output is subjected to serial processing in the second stage. The second channel of the second channel polyphase filter bank 506 may be referred to as ‘N2’. The second stage of the programmable logic device 512 further includes a second fast fourier transform (FFT) block 507. The second FFT block 507 selects a channel among multiple channels (i.e., N2 channels) associated with the second channel polyphase filter bank 506 based at least on a second hop index. Thereafter, the second FFT block 507 computes a second output of required frequency associated with the selected channel. The first output from the second FFT block 507 is ‘fs/(N1 x N2)’. The second FFT block 507 further transmits the second output to a baseband demodulator.
[0053] It is to be noted that the first hop index and the second hop index are provided by a MAC layer 511. The MAC layer 511 includes at least a pulse per second (PPS) block 508 and a hop index calculator 509. The combined operation of the PPS block 508 and the hop index calculator 509 outputs the first hop index and the second hop index. The pulse per second (PPS) 508 block and the hop index calculator 509 may be based on time division multiple access (TDMA). To that effect, the first hop index and the second hop index correspond to a TDMA based hop index. Further, the MAC layer 511 includes a block 510 for performing hop index to channel index mapping based on the first hop index and the second hop index. This enables the selection of the channel among multiple channels (i.e., N1 and N2 channels) associated with the first channel polyphase filter bank 502 and the second channel polyphase filter bank 506 by the corresponding first and second FFT blocks 504 and 507.
[0054] Thus, routing the digital signals routed to at least the first stage and the second stage associated with the programmable logic device 512 of the multistage polyphase channelizer 500 conforms to a two-stage implementation of the channelizer 500. In two-stage implementation of the channelizer 500, the digital signals are subjected to at least parallel processing and serial processing in the first stage and the second stage based at least on the first hop index and the second hop index for optimizing speed and number of resources, respectively. Without loss of generality, the proposed invention can be extended to multiple stages based on the requirement.
[0055] Figure 6 shows a block diagram of proposed Multistage Polyphase Combiner 600 for Frequency Hopping (FH) application according to an exemplary implementation of the present disclosure/invention.
[0056] The multistage polyphase combiner 600 includes a baseband modulator 601. The baseband modulator 601 receives the digital signals and then processes the digital signals to obtain a third output. The third output is ‘fs/(N2 x N1)’. Further, the third output is transmitted from the baseband modulator 601 to a transmitter path of the multistage polyphase combiner 600. In particular, the digital signals are transmitted to a programmable logic device 613 of the multistage polyphase channelizer 600. The programmable logic device 613 includes at least a first stage and a second stage.
[0057] The first stage of the programmable logic device 613 includes a first inverse fast fourier transform (IFFT) block 602, a first channel polyphase filter block 603. The first inverse fast fourier transform (IFFT) block 602 receives the third output from the baseband modulator 601. The first IFFT block 602 selects a channel among multiple channels associated with the first channel polyphase filter bank 603. Further, the first channel of the filter bank 603 may be referred to as ‘N1’. The channel among the multiple channels (i.e., N1 channels) is selected based at least on a third hop index. Further, the IFFT block 602 computes a fourth output of required frequency associated with the channel. Specifically, the output (i.e., the fourth output) of the IFFT block 602 is given by keeping all other channels inputs to zeros and excluding the channel being selected based on the third hop index. Thereafter, the fourth output is transmitted from the first IFFT block 602 to an output commutator 604 of the second stage via the first channel polyphase filter bank 603. The fourth output from the first stage is ‘fs/N2’.
[0058] The fourth output is received at a second inverse fast fourier transform (FFT) block 605 of the programmable logic device 613 from the output commutator 604. The fourth output is subjected to parallel processing in the second stage. The second IFFT block 605 performs similar operations to that of the first IFFT block 602. In particular, the second IIFT block 605 selects a channel among multiple channels associated with the second stage. The second channel associated with the second stage may be referred to as ‘N2’. The channel among the multiple channels (i.e., N2 channels) is selected based at least on a fourth hop index.
[0059] Thereafter, the second IFFT block 605 computes a fifth output of required frequency associated with the channel. In particular, the output (i.e., the fifth output) of the second IFFT block 605 is given by keeping all other channels inputs to zeros and excluding the channel being selected based on the fourth hop index. Further, a second channel polyphase filter bank 606 is operated in parallel for managing high sampling rate of the digital signals of the fifth output. In other words, To implement the second channel polyphase filter block 606, multiple filter blocks are used so that N2 outputs are calculated parallelly. Further, the fifth output is transmitted to a radio frequency (RF) digital to analog converter (DAC) 608 upon converting the fifth output from parallel to series. The fifth output is converted by a parallel to series conversion block 607 associated with the second stage of the multistage polyphase combiner 600. The fifth output referred to as ‘fs’ exhibits high sampling rate which further processed.
[0060] It is to be noted that the third hop index and the fourth hop index are provided by a MAC layer 612. The MAC layer 612 includes at least a pulse per second (PPS) block 609 and a hop index calculator 610. The combined operation of the PPS block 609 and the hop index calculator 610 outputs the third hop index and the fourth hop index. The pulse per second (PPS) block 609 and the hop index calculator 610 may be based on time division multiple access (TDMA). To that effect, the third hop index and the fourth hop index correspond to a TDMA based hop index. Further, the MAC layer 612 includes a block 611 for performing hop index to channel index mapping based on the third hop index and the fourth hop index. This enables the selection of the channel among multiple channels (i.e., N1 and N2 channels) associated with the first channel polyphase filter bank 603 and the second channel polyphase filter bank 606 by the corresponding first and second FFT blocks 602 and 605.
[0061] Thus, routing the third output routed to at least the first stage and the second stage associated with the programmable logic device 613 of the multistage polyphase combiner 600 conforms to a two-stage implementation of the combiner. In two-stage implementation of the combiner 600, the third output is subjected to at least serial processing and parallel processing in the first stage and the second stage based at least on the third hop index and the fourth hop index for optimizing number of resources, and speed respectively. Without loss of generality, the proposed invention can be extended to multiple stages based on the requirement.
[0062] Figure 7 shows an overview of proposed Frequency Hopping (FH) scheme according to an exemplary implementation of the present disclosure/invention.
[0063] The figure shows the overview of the proposed FH scheme in multiple stages. A first stage has two channels, and an input signal to the first stage is represented as 701. The input signal 701 falls into a first channel of the first stage. A second stage has four channels and the input signal 701 after down conversion using the first stage is represented as 702. In the second stage the input signal 702 falls into a third channel which is given to a third stage as input. The third stage has eight channels and the input signal falls into the third channel and this output is given to baseband demodulator.
[0064] The wideband ADC/DAC uses JESD interface to transfer the samples to and from the FPGA. This architecture is applied to the frequency hopping application and can be extended to similar applications thereof. At the receiver these samples are supplied in a parallel fashion to the first stage of multistage polyphase filter bank retaining the commutator properties as show in Figure 5. These samples are filtered parallelly through the polyphase filters (i.e., the first channel polyphase filter bank 503) and given to the FFT module (i.e., the FFT block 504). In frequency hopping application the hop index is known from the PPS aligned hopping method. As explained above, the hop index is mapped to the channel number of the polyphase filter. So only the output of that particular channel is computed and considered for further processing and the rest of the channels are discarded. So, this method of implementation reduces number of resources required to a greater extent.
[0065] The selected channel output is passed on to the next stage. N1 being the number of channels in the first stage of multistage polyphase channelizer 500. The choice of N1 is based on the RF ADC sampling rate. If N1 is very high then the resources required for parallel implementation increases, on the other hand if N1 is very less the operating frequency has to be increased. So, a trade off between these two parameters has to be considered.
[0066] From the second stage of the multi-stage polyphase channelizer 500, conventional polyphase channelizer architecture is followed with the computation of only the required channel output based on the hop index and rest of the channels are discarded. Similarly, the same procedure applies to multistage polyphase combiner 600 but in the reverse fashion as explained with reference to Figure 6, therefore it is not reiterated herein again for the sake of brevity.
[0067] An overview of the proposed FH scheme is shown in Figure 7. The hop is index obtained from the PPS (pulse per second) aligned hop index calculator. This hop index is then mapped to the channel indexes at each stage and correspondingly the signal is transmitted on the required frequency. This proposed hopping scheme is implemented for TDMA based access scheme and can be extended for other access schemes thereof.
[0068] Conventional implementation of a N-pt FFT needs (2*N*logN) real multipliers and (3*N logN) real adders are required. In the proposed implementation only the required channel output is calculated. So, the number of multipliers and adders required are only to calculate that particular channel output. For a known hopping index i.e., channel, this can be accomplished using a single complex multiply accumulate unit there by reducing number of Multipliers and adders required to a greater extent. The proposed architecture can be applied to 2 powers or non 2 powers of channels without increasing the complexity.
[0069] Figure 8 is a flow diagram depicting a method 800 performed by the multistage polyphase channelizer 500 for processing wideband radio frequency (RF) transceiver signals, in accordance with an embodiment of the present disclosure. The various steps and/or operations of the flow diagram, and combinations of steps/operations in the flow diagram, may be implemented by, for example, hardware, firmware, a processor, circuitry and/or by the multistage polyphase channelizer 500. The method 800 starts at 802.
[0070] At 802, the method 800 includes receiving radio frequency (RF) signals in form of analog signals by an analog-to-digital converter (ADC) of a multistage polyphase channelizer.
[0071] At 804, the method 800 includes converting the received RF signals to digital signals by the ADC based on performing radio frequency sampling on the received radio frequency signals.
[0072] At 806, the method 800 includes transmitting the digital signals from the ADC to a receiver path of the multistage polyphase channelizer. Further, transmitting the digital signals to the receiver path includes routing the digital signals to at least a first stage and a second stage associated with a programmable logic device of the multistage polyphase channelizer (see, 806a). The digital signals are subjected to at least parallel processing and serial processing in the first stage and the second stage based at least on a first hop index and a second hop index for optimizing speed and number of resources, respectively (see, 806a). Further, the one or more operations performed by the multistage polyphase channelizer 500 for processing wideband radio frequency (RF) transceiver signals are explained with references to Figures 5 and 7, therefore they are not reiterated herein for the sake of brevity.
[0073] Figure 9 is a flow diagram depicting a method 800 performed by the multistage polyphase combiner 600 for processing wideband radio frequency (RF) transceiver signals, in accordance with an embodiment of the present disclosure. The various steps and/or operations of the flow diagram, and combinations of steps/operations in the flow diagram, may be implemented by, for example, hardware, firmware, a processor, circuitry and/or by the multistage polyphase combiner 600. The method 900 starts at 902.
[0074] At 902, the method 900 includes receiving digital signals by a baseband modulator of a multistage polyphase combiner 600.
[0075] At 904, the method 900 includes processing the digital signals by the baseband modulator to obtain a third output.
[0076] At 906, the method 900 includes transmitting the third output from the baseband modulator to a transmitter path of the multistage polyphase combiner. Further, transmitting the third output to the transmitter path includes routing the third output to at least a first stage and a second stage associated with a programmable logic device of the multistage polyphase combiner (see, 906a). The third output signals are subjected to at least serial processing and parallel processing in the first stage and the second stage based at least on a third hop index and a fourth hop index for optimizing number of resources and speed, respectively (see, 906a). Further, the one or more operations performed by the multistage polyphase combiner 600 for processing wideband radio frequency (RF) transceiver signals are explained with references to Figures 6 and 7, therefore they are not reiterated herein for the sake of brevity.
[0077] Further, multistage implementation gives an added advantage of better Low pass filter (LPF) realization. Since, multistage approach is taken instead of single stage de-hopping, the LPF can be easily realized because the cut off frequency to sampling rate ratio will be more compared to the single stage approach. Also, the multistage approach gives better rejection compared to the single stage approach.
[0078] Thus, taking into account of all the added advantages, efficient multistage polyphase channelizer and combiner architecture is proposed. The number of channels at each stage has to be determined based on ADC/DAC sampling rates, possible processing rate, resources available and baseband signal bandwidth. The proposed FH architecture can be adopted to different RF bands by changing only the NCO tuned frequency correspondingly.
[0079] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.

,CLAIMS:
1. A method (800) for processing wideband radio frequency (RF) signals, the method (800) comprising:
receiving (802) radio frequency (RF) signals in form of analog signals by an analog-to-digital converter (ADC) (501) of a multistage polyphase channelizer (500);
converting (804) the received RF signals to digital signals by the ADC based on performing radio frequency sampling on the received radio frequency signals; and
transmitting (806) the digital signals from the ADC to a receiver path of the multistage polyphase channelizer, wherein transmitting the digital signals to the receiver path comprises:
routing (806a) the digital signals to at least a first stage and a second stage associated with a programmable logic device (512) of the multistage polyphase channelizer, wherein the digital signals are subjected to at least parallel processing and serial processing in the first stage and the second stage based at least on a first hop index and a second hop index for optimizing speed and number of resources, respectively.

2. The method (800) as claimed in claim 1, further comprising:
performing conversion of the digital signals from series to parallel by a series to parallel conversion block (502) of the programmable logic device, upon receipt of the RF signals from the ADC;
operating parallelly, a first channel polyphase filter bank (503) of the programmable logic device, for maintaining a high sampling rate of the digital signals;
selecting by a first fast fourier transform (FFT) block (504) of the programmable logic device, a channel among multiple channels associated with the first channel polyphase filter bank based at least on the first hop index; and
computing by the first fast fourier transform (FFT) block, a first output of required frequency associated with the channel.

3. The method (800) as claimed in claims 1 or 2, further comprising:
receiving the first output by a second channel polyphase filter bank (506) of the second stage from the first fast fourier transform (FFT) block via an input commutator (505) of the second stage, wherein the first output is subjected to serial processing in the second stage;
selecting by a second fast fourier transform (FFT) block (507) of the programmable logic device, a channel among multiple channels associated with the second channel polyphase filter bank based at least on the second hop index;
computing by the second fast fourier transform (FFT) block, a second output of required frequency associated with the channel; and
transmitting by the second fast fourier transform (FFT) block, the second output to a baseband demodulator.

4. The method (800) as claimed in claim 1, further comprising:
computing the first hop index and the second hop index by combined operation of a pulse per second (PPS) block (508) and a hop index calculator (509), the first hop index and the second hop index correspond to a time division multiple access (TDMA) based hop index; and
performing hop index to channel index mapping based on the first hop index and the second hop index, for selecting a channel among multiple channels associated with a first channel polyphase filter bank (503) and a second channel polyphase filter bank (506).

5. The method (800) as claimed in claim 1, wherein subjecting the input RF signals to at least parallel processing and serial processing in the multistage polyphase channelizer reduces at least a processing rate.
6. A method (900) for processing wideband radio frequency (RF) signals, the method (900) comprising:
receiving (902) digital signals at a baseband modulator (601) of a multistage polyphase combiner (600);
processing (904) the digital signals by the baseband modulator to obtain a third output; and
transmitting (906) the third output from the baseband modulator to a transmitter path of the multistage polyphase combiner, wherein transmitting the third output to the transmitter path comprises:
routing (906a) the third output to at least a first stage and a second stage associated with a programmable logic device (613) of the multistage polyphase combiner, wherein the third output signals are subjected to at least serial processing and parallel processing in the first stage and the second stage based at least on a third hop index and a fourth hop index for optimizing number of resources and speed, respectively.

7. The method (900) as claimed in claim 6, further comprising:
receiving the third output at a first inverse fast fourier transform (IFFT) block (602) of the programmable logic device;
selecting by the first IFFT block a channel among multiple channels associated with a first channel polyphase filter bank (603) in the first stage of the multistage polyphase combiner, wherein the channel among the multiple channels is selected based at least on the third hop index;
computing by the first IFFT block, a fourth output of required frequency associated with the channel; and
transmitting the fourth output from the first IFFT block to an output commutator (604) of the second stage via the first channel polyphase filter bank of the multistage polyphase combiner.

8. The method (900) as claimed in claim 6 or 7, further comprising:
receiving the fourth output at a second inverse fast fourier transform (IFFT) block (605) of the programmable logic device from the output commutator;
selecting by the second IFFT block a channel among multiple channels associated with the second stage of the multistage polyphase combiner, wherein the channel among the multiple channels is selected based at least on the fourth hop index;
computing by the second IFFT block, a fifth output of required frequency associated with the channel;
operating parallelly, a second channel polyphase filter bank (606) of the programmable logic device for maintaining high sampling rate of the digital signals of the fifth output; and
transmitting the fifth output to a radio frequency (RF) digital to analog converter (DAC) upon converting the fifth output from parallel to series.

9. The method (900) as claimed in claim 6, further comprising:
computing the third hop index and the fourth hop index by combined operation of a pulse per second (PPS) block (609) and a hop index calculator (610), the third hop index and the fourth hop index correspond to a time division multiple access (TDMA) based hop index; and
performing hop index to channel index mapping based on the third hop index and the fourth hop index, for selecting a channel among multiple channels associated with a first channel polyphase filter bank (603) and a second channel polyphase filter bank (606).

10. The method (900) as claimed in claim 6, wherein subjecting the third output to at least serial processing and parallel processing in the multistage polyphase combiner reduces at least a processing rate.