DESC:TECHNICAL FIELD
1. The present disclosure generally relates to high precision oscillators. More particularly, the present disclosure relates to a method of clock disciplining and holdover with respect to an oscillator such that the oscillator continuously performs to act as an accurate clock source.

BACKGROUND
2. Background description includes information that can be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
3. Global Navigation Satellite system (GNSS) is a space-based satellite navigation system that provides location and timing information. The constellations in GNSS include GPS, GLONASS, Galileo, IRNSS (Indian Regional Navigation Satellite System), Beidou, QZSS etc.
4. Although GNSS signals "rains" from the sky, they are quite faint, have poor penetration and are easily obscured. They are not available (or reliable) indoors or in noisy RF environments. So being able to hold the last known frequency and timing (phase) during a GNSS outage becomes a necessary requirement in critical timing solutions. This is why GNSS receivers are paired with high-quality oscillators, to create clock sources with holdover characteristics that can bridge temporary RF outages.
5. In the current art, disclosures provided attempts at addressing various needs associated with radar devices and applications. In one conventional method of generating disciplined clock, the methodology relies on a GPS receiver generating a reference pulse, a digital to analog converter (DAC) for supplying control voltage and an oscillator locked to reference pulse and controlled via the control voltage from DAC to generate a reference clock. Here the stability of the clock mainly depends on the resolution of the DAC. To precisely control the clock, the narrow tuning of oscillator is required which in turn depends on how good is the resolution of DAC used.
6. In another conventional method disclosed in US 2016.0223677A1. The method comprises of receiving a GPS time signal representing GPS time data, providing local time data with local clock. Here local clock is initiated with GPS time. The difference between current GPS time and local time is calculated thereby measuring an error. If the error exceeds certain threshold value, then GPS time signal is used for time stamping and if the error doesn’t exceed the threshold, local time is used for time stamping. In case of a GPS denied environment main clock source will be the inaccurate local clock as it is not disciplined.
7. This invariably leaves open a pursuit for a need in the art to provide a reliable and efficient a method of clock disciplining and holdover with respect to an oscillator such that the oscillator continuously performs to give accurate clock source even in the case of GNSS outage.
8. All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
9. In some embodiments, the numbers expressing quantities or dimensions of items, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
10. As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
11. Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.

OBJECTS OF THE PRESENT DISCLOSURE
12. Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
13. It is an object of the present disclosure to provide a method for clock disciplining and holdover.
14. It is another object of the present disclosure to provide a simple and effective method for clock disciplining and holdover.
15. It is another object of the present disclosure to provide a reliable and efficient method for clock disciplining and holdover.
16. It is another object of the present disclosure to provide a robust method for clock disciplining and holdover.

SUMMARY
17. The present disclosure relates to high precision oscillators. More particularly, the present disclosure relates to a method of clock disciplining and holdover with respect to an oscillator such that the oscillator continuously performs to give accurate clock source even in the case of GNSS outage.
18. This summary is provided to introduce simplified concepts of a system for time bound availability check of an entity, which are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended for use in determining/limiting the scope of the claimed subject matter.
19. An aspect of the present disclosure pertains to a circuitry for achieving accurate clock sourcing. The circuitry includes a global navigation satellite system (GNSS) receiver configured to generate a reference pulse; an oscillator configured to lock to the reference pulse from a GNSS module associated with the GNSS receiver; a field programmable gate array (FPGA) configured to compare clocks from the GNSS receiver and the oscillator, derive a clock error of the oscillator with respect to the clock associated with the GNSS receiver, and compute correction values for disciplining the oscillator for better holdover performances; and an advanced RISC (reduced instruction set computer) machine (ARM) processing side.
20. In an aspect, the oscillator is tuned and disciplined by means of a methodology implemented on a System on Chip (SoC).
21. In an aspect, the circuitry is a GNSS based disciplined reference clock circuitry.
22. In an aspect, the methodology includes logical blocks tasked to analyse two accurate time sources and compute error therebetween without using any external hardware circuits including conventional Phased lock loop (PLL) or Analog to Digital Convertor (ADC).
23. In an aspect, the methodology has a sign based identification to determine the oscillator’s speed or phase.
24. In an aspect, the methodology includes a comparison module to determine a difference between the actual number of pulses from oscillator and the expected number of pulses over a specified duration, being computed by means of the FPGA or the SoC.
25. In an aspect, the methodology including a ARM side computing module to wherein the ARM side of SoC receives the error or difference values then computes the correction values and sends the correction values to the oscillator for disciplining.
26. In an aspect, the methodology is configured to derive both the course value and fine value from the phase error.
27. In an aspect, the methodology is capable of averaging out the phase error values by adaptive moving average principle.
28. In an aspect, the methodology is configured to allow a holdover when the GNSS clock is not available.
29. In an aspect, the methodology is configured to allow a deliberate holdover even when the GNSS clock is present to protect from any kind of timing interferences.
30. In an aspect, the methodology proposed is oscillator independent.
31. In an aspect, the methodology is capable of being utilized with different kinds of oscillators.
32. Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
33. The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
34. FIG. 1 shows a system level block diagram with regards to a method of clock disciplining and holdover, in accordance with an embodiment of the present disclosure.
35. FIG. 2 shows a block diagram for the design implemented in the FPGA portion, in accordance with an embodiment of the present disclosure.
36. FIG. 3 shows a flow chart for calculating the phase error by taking 1pps input and calculating the phase error with respect to the GNSS clock, in accordance with an embodiment of the present disclosure.
37. FIG. 4 shows a block diagram for edge detection circuitry and the holdover request feature embodied within, in accordance with an embodiment of the present disclosure.
38. FIG. 5 shows the flow chart of the disciplining methodology in the ARM side which receives the phase error and sends the corresponding correction value to the rubidium oscillator, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
39. The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
40. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
41. Embodiments of the present invention include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and/or by human operators.
42. Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present invention with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present invention may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the invention could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
43. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
44. As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
45. Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
46. Thus, for example, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named element.
47. Embodiments of the present invention may be provided as a computer program product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process. The term “machine-readable storage medium” or “computer-readable storage medium” includes, but is not limited to, fixed (hard) drives, magnetic tape, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, magnetic or optical cards, or other type of media/machine-readable medium suitable for storing electronic instructions (e.g., computer programming code, such as software or firmware).A machine-readable medium may include a non-transitory medium in which data may be stored and that does not include carrier waves and/or transitory electronic signals propagating wirelessly or over wired connections. Examples of a non-transitory medium may include, but are not limited to, a magnetic disk or tape, optical storage media such as compact disk (CD) or digital versatile disk (DVD), flash memory, memory or memory devices. A computer-program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
48. Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks (e.g., a computer-program product) may be stored in a machine-readable medium. A processor(s) may perform the necessary tasks.
49. Systems depicted in some of the figures may be provided in various configurations. In some embodiments, the systems may be configured as a distributed system where one or more components of the system are distributed across one or more networks in a cloud computing system.
50. Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases, it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
51. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
52. Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
53. The present disclosure generally relates to high precision oscillators. More particularly, the present disclosure relates to a method of clock disciplining and holdover with respect to an oscillator such that the oscillator continuously performs to give accurate clock source even in the case of GNSS outage.
54. FIG. 1 shows a system level block diagram with regards to a method of clock disciplining and holdover, in accordance with an embodiment of the present disclosure. As shown in FIG. 1, the FPGA design has an oscillator input, GNSS clock input, Phase Error Calculation FSM, Disciplined 1PPS out generation, PLLs and a reporting function that will send phase error & sign to the ARM every 400sec.
55. FIG. 2 shows a block diagram for the design implemented in the FPGA portion, in accordance with an embodiment of the present disclosure. FIG. 2 illustrates the Phase Error Calculation (PEC) FMS which is driven by the GNSS clock. The FPGA is receiving 10MHz clock output from local oscillator and 1PPS output from GNSS. For e.g. if the local oscillator is Rubidium, then its resolution will be 10-11. To accurately synchronize the oscillator with the GNSS clock the resolution of synchronization should be 10-11 i.e., the error calculated should be in the order of 10-11. But with 10MHz output of the local oscillator, maximum error that can be measured is 10-7.
56. To achieve the resolution of Rubidium, the following methodology has been followed: 10MHz clock has been converted into a 250MHz clock using PLL’s inside FPGA. By doing this the resolution now reached 1/250 MHz = 4 X 10-9.The maximum clock that PLL’s can generate and output is 250MHz.But the resolution to be achieved is 10-11. Hence instead of calculating error for each 1PPS output, the error is calculated for 400 pulses of 1PPS thereby achieving the resolution of 10-11.
57. The above methodology can be used for deriving resolutions of various oscillators with different resolutions.
58. The following methodology is used to calculate the phase error value: It is assumed that if clock frequency of GNSS Satellite is exactly matched with local oscillator then exactly 250M pulses can be seen synced with 1PPS of GNSS. I.e.in 400 continuous pulses of 1PPS of GNSS, 400*250M pulses of local oscillator should be present.
59. If the local oscillator’s pulse count is more than the expected pulse count in 250MHz, then the oscillator is running faster and the phase error sign is represented by a positive value and if the oscillator’s pulse count is less than the expected pulse count in 250MHz, then the oscillator is running slower and the phase error sign is represented by a negative value.
60. In summary, this FSM compares and calculates the number of 250MHz pulses in 400 continuous 1PPS pulses, and calculate the difference every 400 consecutive seconds and then sends the error and sign to ARM using the reporting function.
61. FIG. 3 shows a flow chart for calculating the phase error by taking 1pps input and calculating the phase error with respect to the GNSS clock, in accordance with an embodiment of the present disclosure.
62. FIG. 4 shows a block diagram for edge detection circuitry and the holdover request feature embodied within, in accordance with an embodiment of the present disclosure. Fig 4 illustrates the flow chart of the methodology implemented in the ARM side. The methodology includes capturing the phase error and phase sign computed by the Phase Error Calculation FMS every 400 seconds. The PEC FSM will send an interrupt to the ARM notifying it to capture the phase error and phase sign.
63. When the interrupt is high, the methodology includes capturing the error value and the sign. From the phase error value the course correction and fine correction which is to be written into the rubidium clock is calculated by using lookup tables.
64. There are lookup tables for positive adjustments and negative adjustments. Which lookup table to refer to is dependent on the phase sign. I.e. if the local oscillator is running faster, then the phase sign is represented by a positive value, so the clock needs to be slowed down. In such cases negative adjustments are to be done and for calculating the course and fine corrections negative adjustment lookup table is referred to and vice versa for positive adjustments.
65. After calculating the course correction and fine correction, the correction values are then sent to the local oscillator for it to adjust/correct its frequency and phase accordingly. This “Disciplining” process will happen within a second, every 400 seconds until GNSS clock is available as the PEC FSM which sends interrupt, phase error value and phase sign is driven by the GNSS clock i.e. the disciplining methodology has a time window of only 1 second to detect the interrupt sent by the reporting function in FPGA and adjust the oscillator’s frequency, afterwards all these values will be reset by the FPGA State Machine.
66. Since the disciplining methodology in the arm side is a continuous process the phase error values are averaged/smoothened using adaptive moving average method for smoothening the error values.
67. Once the GNSS clock is not available then the PEC FSM stops as it is driven by the GNSS clock and the disciplining process no longer happens. In such cases the local oscillator should perform on its own without being continuously disciplined/corrected.
68. This means there would be no clock to take as a reference to discipline the local oscillator and it should continue to provide accurate 1pps signals based on the disciplining done earlier. This scenario is called as holdover.
69. The system can go into holdover in 2 cases: When GNSS clock stops or when there is a forced/deliberate holdover request (from ARM) to protect the system from various deliberate timing interferences. The holdover performance depends upon the disciplining methodology and the duration for which the disciplining has been done.
70. FIG. 5 shows the flow chart of the disciplining methodology in the ARM side which receives the phase error and sends the corresponding correction value to the rubidium oscillator, in accordance with an embodiment of the present disclosure.
71. Thus, an aspect of the present disclosure pertains to a disciplining methodology that is oscillator independent. In other words, the same methodology can be used for different kinds of oscillators. In an aspect, a Global Navigation Satellite system (GNSS) based disciplined reference clock circuitry and method thereof includes a GNSS receiver generating a reference pulse; a Field Programmable Gate Array (FPGA); an Advanced RISC Machine (ARM) processing side; an Oscillator, wherein the oscillator is locked to the reference pulse from GNSS module and tuned/disciplined using the methodology implemented inside System on Chip (SoC).
72. In an aspect, the circuitry further comprises a methodology of logical blocks tasked to analyse two accurate time sources and compute the error between them if any, to the best of the oscillator’s resolution without using any external hardware circuits like conventional Phased lock loop (PLL) or Analog to Digital Convertor (ADC).
73. In an aspect, the methodology has a sign-based identification to determine the oscillator’s speed/phase.
74. In an aspect, the methodology in which the difference between the actual number of pulses from oscillator and the expected number of pulses over a specified duration is computed using FPGA of SoC.
75. In an aspect, the methodology in which the ARM side of SoC receives the error or difference values then computes the correction values and sends the correction values to the oscillator for disciplining.
76. In an aspect, the methodology is able to derive both the course value and fine value from the phase error.
77. In an aspect, the methodology averages out the phase error values by adaptive moving average principle.
78. In an aspect, the methodology which puts the system into holdover when the GNSS clock is not available or into deliberate holdover even when the GNSS clock is present to protect the system from any kind of timing interferences.
79. Thus, the present disclosure provides the following benefits among others. (i) the disciplining methodology proposed is oscillator independent i.e. the same methodology can be used for different kinds of oscillators and will also calculates the error and discipline the oscillator to the best of its resolution; (ii) the disciplining methodology comprising of logical blocks tasked to analyse two accurate time sources and compute the difference between them if any, without using any external hardware circuits like conventional PLL’s, ADC, etc; (iii) sign based identification methodology to determine the phase/speed of the Oscillator; (iv) the methodology adaptively smoothens out the errors computes the correction values and writes them to the oscillator within a second; (v) the disciplining methodology ensures a holdover of less than 2sec in 24Hrs; (vi) a feature which puts the system into holdover automatically, even if GNSS signals are present when a deliberate timing interference is noticed/detected.
80. In an embodiment, a GNSS-disciplined Clock consists of a high-quality (precision) oscillator that is continuously being corrected using the coordinated universal timing signal (UTC), or standard second, in the form of 1PPS pulses recovered from the GNSS signals. In theory, the rising edge of the One-Pulse-Per-Second (1PPS) represents the beginning of a standard second. If clock from GNSS is lost for any reason, the oscillator’s output will be able to remain within specification for two reasons: the oscillator is kept at a constant high temperature that insures no significant drifts, and the disciplining done to the oscillator when the clock from GNSS was present.
81. Time server is one apparatus in which the present invention would be very useful, as a Time server maintains time of the entire network. Since there are many time sensitive systems connected in the network, Time server has to be accurately synchronized to GNSS and in case of GNSS outage the Time server should continue to provide accurate timing (holdover) to its peers and clients.
82. The present disclosure is envisioned to be performed using appropriate physical devices that may be appreciated by a person skilled in the art. As such all physical devices comprising respective various physical materials serve their respective functions and all such materials and their respective manufacturing methods are intended to be covered by this disclosure.
83. Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures can be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
84. While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
85. In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
86. As used herein, and unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other)and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with" are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
87. It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps can be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
88. While the foregoing describes various embodiments of the invention, other and further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
89. The present disclosure provides a method for clock disciplining and holdover.
90. The present disclosure provides a simple and effective method for clock disciplining and holdover.
91. The present disclosure provides a reliable and efficient method for clock disciplining and holdover.
92. The present disclosure provides a robust method for clock disciplining and holdover.
,CLAIMS:1. A circuitry for achieving accurate clock sourcing, the circuitry comprising:
a global navigation satellite system (GNSS) receiver configured to generate a reference pulse;
an oscillator configured to lock to the reference pulse from a GNSS module associated with the GNSS receiver;
afield programmable gate array (FPGA) configured to compare clocks from the GNSS receiver and the oscillator, derive a clock error of the oscillator with respect to the clock associated with the GNSS receiver, and compute correction values for disciplining the oscillator for better holdover performances; and
an advanced RISC machine (ARM) processing side;
wherein the oscillator is tuned and disciplined by means of a methodology implemented on a System on Chip (SoC); and
wherein the circuitry is a GNSS based disciplined reference clock circuitry.
2. The circuitry of claim 1, wherein the methodology includes logical blocks tasked to analyse two accurate time sources and compute error therebetween without using any external hardware circuits including conventional Phased lock loop (PLL) or Analog to Digital Convertor (ADC).
3. The circuitry of claim 2, wherein the methodology has a sign-based identification to determine the oscillator’s speed or phase.
4. The circuitry of claim 3, wherein the methodology includes a comparison module to determine a difference between the actual number of pulses from oscillator and the expected number of pulses over a specified duration, being computed by means of the FPGA or the SoC.
5. The circuitry of claim 4, wherein the methodology including a ARM side computing module to wherein the ARM side of SoC receives the error or difference values then computes the correction values and sends the correction values to the oscillator for disciplining.
6. The circuitry of claim 5, wherein the methodology is configured to derive both the course value and fine value from the phase error.
7. The circuitry of claim 6, wherein the methodology is capable of averaging out the phase error values by adaptive moving average principle.
8. The circuitry of claim 7, wherein the methodology is configured to allow a holdover when the GNSS clock is not available; and wherein the methodology is configured to allow a deliberate holdover even when the GNSS clock is present to protect from any kind of timing interferences.
9. The circuitry of claim 8, wherein the methodology proposed is oscillator independent.
10. The circuitry of claim 9, wherein the methodology is capable of being utilized with different kinds of oscillators.