Claims:We Claim:

1. A method to minimize recovery time and improve logging linearity of logarithmic amplifiers with a digital solution, the method comprising:
receiving radio frequency signals as an input from antenna by a RF transceiver;
conditioning the received radio frequency signal by the RF signal conditioning chain, wherein the RF signal conditioning chain comprising of fixed, variable gain stage, filter and temperature sensitive attenuator for conditioning the signal to enhanced level;
sampling and converting the received radio frequency signal to a digital radio frequency signal by an analog to digital convertor without down conversion to intermediate frequency; and
converting a digitally converted radio frequency signal to a video signal by a field programmable gate array, wherein the field programmable gate array has a filter and a digital log detector.

2. The method as claimed in claim 1, wherein the recovery time of logarithmic amplifier is minimized due to very low aperture delay of Analog to Digital Converter and less transient time of Radio Frequency signal conditioning chain.

3. The method as claimed in claim 1, wherein the method minimizes recovery time and improves logging linearity of logarithmic amplifiers with digital solution and it is achieved with minimum pulse stretch.

4. The method as claimed in claim 1, wherein the excellent logging linearity of logarithmic amplifier is achieved by introducing temperature sensitive attenuators in the conditioning chain, operating signal condition chain in linear region, usage of minimum quantization error in analog to digital Converter and digital implementation of logarithmic amplifiers.

5. The method as claimed in claim 1, wherein the method provides flexibility to change output voltage swing/slope of logarithmic amplifier.

6. The method as claimed in claim 1, wherein the fixed and variable gain stage, filter and temperature sensitive attenuator of radio frequency conditioning chain mainly decides the recovery time of the digital logarithmic amplifier.

7. A system to minimize recovery time and to improve logging linearity of logarithmic amplifiers, the system comprising:
a RF signal conditioning chain, wherein the RF signal conditioning chain receives radio frequency signal as a input for processing to superior level;
an analog to digital converter coupled to an output of the RF signal conditioning chain, wherein the analog to digital convertor is to sample and to convert the radio frequency signal to digital radio frequency signal without down conversion to intermediate frequency; and
a field programmable gate array coupled to the output of the analog to digital convertor, wherein the field programmable gate array consists of a filter and a digital log detector which process the digital radio frequency signal to a digital video signal.

8. The system as claimed in claim 1, wherein the radio frequency conditioning chain further comprising of fixed and variable gain stage, filter and temperature sensitive attenuator.

9. The system as claimed in claim 1, wherein the system minimizes recovery time and improves logging linearity of logarithmic amplifiers using digital implementation.

10. The system as claim in claim 1, wherein the recovery time of the digital logarithmic amplifier is minimized due to very low apertures delay of analog to digital converter and less transient time of radio frequency signal condition chain.
, Description:FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10, rule 13)

“A method to minimize recovery time and improve logging linearity of logarithmic amplifiers with digital solution”

By
BHARAT ELECTRONICS LIMITED
Nationality: Indian
of
M/s. Bharat Electronics Limited, Corporate Office, Outer Ring Road, Nagavara, Bangalore-560045, Karnataka, India

The following specification particularly describes the invention and the manner in which it is to be performed.

Field of the invention
The present invention mainly relates to a logarithmic amplifiers and more particularly to the recovery time and logging linearity of logarithmic amplifiers.

Background of the invention
A logarithmic amplifier is well known in the art which is a linear circuit in which the output voltage will be a constant times the natural logarithm of the input. The basic output equation of a log amplifier is Vout = K ln (Vin/Vref), where Vref is the constant of normalisation and K is the scale factor. Log amplifier finds a lot of application in electronic fields like multiplication or division (they can be performed by addition or subtraction of the logs of the operand), computerised process control, compression, RMS value detection etc. Basically there are two log amp configurations: Opamp-diode log amplifier and Opamp-transistor log.
In general, the principal application of log amplifier is to measure signal strength, as opposed to detecting signal content. The example of this is using a log amplifier in an automatic gain control loop, to regulate the gain of a variable-gain amplifier. The receiver of a cellular base station, for example, might use the signal from a log amp to regulate the receiver gain. In transmitters, log amps are also used to measure and regulate transmitted power.
Presently, the log amplifier uses hardware components like diodes, high impedance circuit which makes the process temperature as well fabrication dependent to maintain linear characteristics. In the prior art, the change in slope of logarithmic amplifier is dependent on physical components. Further, the techniques used in prior art limits the input power to logarithmic amplifier because of high recovery time.
For example, in US007389692B2 titled “Digital log amplifier for ultrasonic testing" describes a method and system for processing acoustic signals for use in ultrasonic inspection and testing, and more particularly to simultaneously process an acoustic signal with multiple linear amplifiers to obtain a combined linear digital output signal having a dynamic response range that is greater than the individual ranges of the amplifier.
Further, in US 20030003885A1 titled "Successive log video pad power detector and method" describes the limitation of Successive log video amplifier (SLVA) in terms of fabrication cost and handling of lower power signals only. Because of usage of series of diode detectors, sampled signal can be divided among the detector. In this method sampled signal is divided and divided signals are detected by a unidirectional device. Detected signals are summed to provide a control signal. Sampled signal is divided prior to detection without using active circuit elements.
Further, the paper titled “A True logarithmic amplifier for RADAR IF applications” used bipolar technology to produce a true logarithmic amplifier capable of working at radar Intermediate Frequencies with minimal phase variation with signal level. The close internal component matching as well as matching between dual-gain stages which are essential to produce a good logarithmic amplifier have also been achieved. Phase shift or delay through the log amplifier should not vary with input signal level.
Furthermore, the paper titled “An L-Band temperature compensated ultra-low power successive detection logarithmic amplifier “describes temperature compensated L-band GaAs Monolithic Microwave Integrated Circuit successive detection logarithmic amplifier (SDLA) featuring ultra-low power consumption. Log-linearity of ?2.5 decibels and a dynamic range of 60 decibels were achieved over a 100 degree temperature range. This device shows no sacrifice of performance over larger, labor intensive hybrid Monolithic Integrated Circuit approaches. Transfer function of the successive detection logarithmic amplifier is a piecewise linear approximation and to achieve the theoretical accuracy inherent in the piecewise linear approximation of the Successive detection logarithmic amplifier, all the Radio Frequency amplifiers, detectors and limiters must be identical. To achieve a temperature-stable design, the sensitivity of the detectors and the limiting voltage of the limiters must not change with temperature.
Therefore there is a need in the art with a method to minimize the recovery time of logarithmic amplifiers and improve logging linearity with digital solution.

Objective of the invention
The main objective of the present invention is to minimize the recovery time of Logarithmic amplifier.
Another objective of the present invention is to provide flexibility to change the output voltage swing/slope of Logarithmic amplifier.
Further objective of the present invention is to provide high dynamic range with minimum pulse stretch.
Furthermore objective of the present is to provide excellent logging linearity of logarithmic amplifiers.

Summary of the Invention
An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.
Accordingly, in one aspect of the present invention relates to a method to minimize recovery time and improve logging linearity of logarithmic amplifiers with a digital solution, the method comprising: receiving radio frequency signals as an input from antenna by a RF transceiver, conditioning the received radio frequency signal by the RF signal conditioning chain, wherein the RF signal conditioning chain comprising of fixed, variable gain stage, filter and temperature sensitive attenuator for conditioning the signal to enhanced level, sampling and converting the received radio frequency signal to a digital radio frequency signal by an analog to digital convertor without down conversion to intermediate frequency and converting a digitally converted radio frequency signal to a video signal by a field programmable gate array, wherein the field programmable gate array has a filter and a digital log detector.
Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

Brief description of the drawings
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:
Figure 1 shows a functional block diagram of conventional Successive Detection Logarithmic Intermediate Frequency Amplifier.
Figure 2 shows a system functional block diagram of digital log detector developed with high speed Analog to Digital Converter and Field Programmable Gate Array, according to one embodiment of the present invention.
Figure 3 shows a Time domain Pulse modulated Identification, Friend or Foe signal with pulse width 0.45micro seconds and period 1.45micro seconds which is fed to receiver for evaluation.
Figure 4 illustrates demodulated output from existing Analog Identification.
Figure 5 illustrates Radio Frequency input demodulation output of the Direct Radio Frequency sampling Digital Receivers, according to one embodiment of the present invention.
Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure.
Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

Detailed description of the invention
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces.
By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.
Figs. 1 through 5, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way that would limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged communications system. The terms used to describe various embodiments are exemplary. It should be understood that these are provided to merely aid the understanding of the description, and that their use and definitions, in no way limit the scope of the invention. Terms first, second, and the like are used to differentiate between objects having the same terminology and are in no way intended to represent a chronological order, unless where explicitly stated otherwise. A set is defined as a non-empty set including at least one element.
Referring now to FIG. 1 there is shown the prior art i.e. a functional block diagram of conventional Successive Detection Logarithmic Intermediate Frequency Amplifier. The amplifier includes N number of RF amplifiers connected in ‘series to receive and cascade amplify an input RF signal applied to input terminal. A radio frequency limiter may also be connected to the output of each of the amplifiers for limiting the RF output of successive amplifier stages. The limiters are set to saturate at a certain predetermined RF power level. The output of each limiter may fed to a detector which demodulates the signal passed by the limiter to produce a video output which is introduced onto a summing line such that the video outputs of successive cascaded amplifier stages are added on the summing line to produce the total output video signal across the load.
Figure 2 shows a system functional block diagram of digital log detector developed with high speed Analog to Digital Converter and Field Programmable Gate Array, according to one embodiment of the present invention. The system includes a RF signal conditioning chain, where the RF signal conditioning chain receives radio frequency signal as an input for processing to superior level. The radio frequency conditioning chain further comprising of fixed and variable gain stage, filter and temperature sensitive attenuator.
Further, the system includes an analog to digital converter which is coupled to the output of the RF signal conditioning chain. The analog to digital convertor is to sample and to convert the radio frequency signal to digital radio frequency signal without down conversion to intermediate frequency. The system further includes a field programmable gate array (FPGA) which is coupled to the output of the analog to digital convertor. The field programmable gate array further includes a filter and a digital log detector which process the digital radio frequency signal to a video signal.
In an operation, to achieve minimize recovery time and improve logging linearity of logarithmic amplifiers, the present invention provides a digital solution. The receiving radio frequency signals are received as an input from antenna by a RF transceiver. Upon receiving, the received radio frequency signal are conditioned by the RF signal conditioning chain, where the RF signal conditioning chain comprising of fixed, variable gain stage, filter and temperature sensitive attenuator for conditioning the signal to enhanced level. The fixed and variable gain stage, filter and temperature sensitive attenuator of radio frequency conditioning chain mainly decides the recovery time of the digital logarithmic amplifier.
Further, upon conditioning, the received radio frequency signal are sampled and converted to a digital radio frequency signal using an analog to digital convertor. The sampling and conversion of the signal are without down conversion to intermediate frequency. Further, converting a digitally converted radio frequency signal to a video signal by a field programmable gate array (FPGA), where the field programmable gate array has a filter and a digital log detector. By using FPGA, the operation achieves minimized recovery time and improves logging linearity of logarithmic amplifiers with digital solution and it is achieved with minimum pulse stretch.Further, it also provides flexibility to change output voltage swing/slope of logarithmic amplifier.
The system minimizes recovery time and improves logging linearity of logarithmic amplifiers using digital implementation. The excellent logging linearity of logarithmic amplifier is achieved by introducing temperature sensitive attenuators in the conditioning chain, operating signal condition chain in linear region, usage of minimum quantization error in analog to digital Converter and digital implementation of logarithmic amplifiers. Furthermore, the recovery time of the digital logarithmic amplifier is minimized due to very low apertures delay of analog to digital converter and less transient time of radio frequency signal condition chain.
Figure 3 shows a Time domain Pulse modulated Identification, Friend or Foe signal with pulse width 0.45micro seconds and period 1.45micro seconds which is fed to receiver for evaluation.
Figure 4 illustrates demodulated output from existing Analog Identification, Friend or Foe receiver, where input is fed at higher side of spurious free dynamic range. The input pulse width is 450nano seconds whereas the measured output demodulated pulse expands by 68%. Extended pulse width in Identification, Friend or Foe receiver after Pulse extraction shows presence of two closed targets instead of single target.
Figure 5 illustrates for same Radio Frequency input demodulation output of the Direct Radio Frequency sampling Digital Receivers. Measured demodulated pulse width of digital receiver expands by 2.2 % which is almost equal to input Radio Frequency pulse width.
Those skilled in this technology can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.
Figs. 1-5 are merely representational and are not drawn to scale. Certain portions thereof may be exaggerated, while others may be minimized. Figs. 1-5 illustrate various embodiments of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.
In the foregoing detailed description of embodiments of the invention, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description of embodiments of the invention, with each claim standing on its own as a separate embodiment.
It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively.

We Claim:

1. A method to minimize recovery time and improve logging linearity of logarithmic amplifiers with a digital solution, the method comprising:
receiving radio frequency signals as an input from antenna by a RF transceiver;
conditioning the received radio frequency signal by the RF signal conditioning chain, wherein the RF signal conditioning chain comprising of fixed, variable gain stage, filter and temperature sensitive attenuator for conditioning the signal to enhanced level;
sampling and converting the received radio frequency signal to a digital radio frequency signal by an analog to digital convertor without down conversion to intermediate frequency; and
converting a digitally converted radio frequency signal to a video signal by a field programmable gate array, wherein the field programmable gate array has a filter and a digital log detector.

2. The method as claimed in claim 1, wherein the recovery time of logarithmic amplifier is minimized due to very low aperture delay of Analog to Digital Converter and less transient time of Radio Frequency signal conditioning chain.

3. The method as claimed in claim 1, wherein the method minimizes recovery time and improves logging linearity of logarithmic amplifiers with digital solution and it is achieved with minimum pulse stretch.

4. The method as claimed in claim 1, wherein the excellent logging linearity of logarithmic amplifier is achieved by introducing temperature sensitive attenuators in the conditioning chain, operating signal condition chain in linear region, usage of minimum quantization error in analog to digital Converter and digital implementation of logarithmic amplifiers.

5. The method as claimed in claim 1, wherein the method provides flexibility to change output voltage swing/slope of logarithmic amplifier.

6. The method as claimed in claim 1, wherein the fixed and variable gain stage, filter and temperature sensitive attenuator of radio frequency conditioning chain mainly decides the recovery time of the digital logarithmic amplifier.

7. A system to minimize recovery time and to improve logging linearity of logarithmic amplifiers, the system comprising:
a RF signal conditioning chain, wherein the RF signal conditioning chain receives radio frequency signal as a input for processing to superior level;
an analog to digital converter coupled to an output of the RF signal conditioning chain, wherein the analog to digital convertor is to sample and to convert the radio frequency signal to digital radio frequency signal without down conversion to intermediate frequency; and
a field programmable gate array coupled to the output of the analog to digital convertor, wherein the field programmable gate array consists of a filter and a digital log detector which process the digital radio frequency signal to a digital video signal.

8. The system as claimed in claim 1, wherein the radio frequency conditioning chain further comprising of fixed and variable gain stage, filter and temperature sensitive attenuator.

9. The system as claimed in claim 1, wherein the system minimizes recovery time and improves logging linearity of logarithmic amplifiers using digital implementation.

10. The system as claim in claim 1, wherein the recovery time of the digital logarithmic amplifier is minimized due to very low apertures delay of analog to digital converter and less transient time of radio frequency signal condition chain.

Abstract
A method to minimize recovery time and improve logging linearity of logarithmic amplifiers with digital solution

The invention relates to a method to minimize recovery time and improve logging linearity of logarithmic amplifiers with a digital solution. In one embodiment, this is accomplished by receiving radio frequency signals as an input, conditioning the signal by the RF signal conditioning chain. Further, sampling and converting the received radio frequency signal to a digital radio frequency signal by an analog to digital convertor without down conversion to intermediate frequency. Digitally converting the signal to a video signal by a field programmable gate array.

Figure 2 (for publication)