FIELD OF INVENTION
The present invention relates to a plasma display apparatus and its driving method, more particularly related to sustain period capable of enhancing luminous efficacy by application of Mix-Mode bipolar sustain pulses on each of sustain and address electrodes.
BACKGROUND OF THE INVENTION
Plasma Display Panel (PDP) is composed of a matrix of discharge cells that are formed by partitions made by barrier ribs between a pair of glass substrates. A Ne-Xe discharge between pair of electrodes on top glass substrate occurs in discharge cell to display visual effects. Each pair of electrodes form a capacitor between them and these electrodes are known as display electrodes, shown in Fig.1, herein after referred as X (sustain) and Y (scan) electrodes. The third electrode is used for application of address voltage, herein after referred as A-electrode. Three different phosphors for Red, Blue and Green colors are provided on the surface of the respective barrier ribs, and the cell volume is filled with a gas mixture (Ne + Xe). During PDP operation, the gas discharge takes place between electrodes in the cells resulting in the generation of Vacuum Ultra Violet (VUV) photons with a wavelength of 147 nm and 173 nm. The phosphors absorb these VUV photons and emit visible light to display a picture including characters and graphics.
Plasma Displays are considered the natural successors to the CRT TV, the household name for last 6-8 decades. Like CRTs, PDPs provide an emissive, phosphor-based solution that is well suited to showing full-color; fast moving video images with high Dark Room Contrast Ratio and wide viewing angle. The only drawback of PDP is its low luminous efficacy due to low brightness and high power consumption. Low brightness also leads to low Bright Room Contrast Ratio. A PDP is classified as DC (direct current) PDP and AC (alternating current) PDP depending on discharge mode and drive waveform of driving voltage applied thereto. In case of capacitive impedance, at discharge site an alternating voltage applied. The picture frame (fields) of the PDP comprises of the number of subfields to provide the necessary gray levels. One subfield is composed of reset period, a scan period and sustain period, in temporal sequence.
In reset period a voltage across X, Y and A electrodes is maintained in such way that a weak discharge, in dark discharge regime, occurs for duration of few hundred of microseconds. This discharge is used for conditioning of the cell with appropriate charges on the wall to facilitate addressing. During the addressing period, a cell is selected for tuming-ON/OFF. An address voltage is applied between Y and A electrodes leading to a strong discharge. Thereafter voltages on X and Y electrode is maintained to accumulate appropriated wall charges such that the breakdown of Ne-Xe gas mixture occurs at voltage lower than breakdown voltage (VB) between X and Y electrodes. During sustain period an
AC voltage (sustain voltage, Vs) is applied between X and Y electrodes and discharge sustains in glow regime. It results in the form of visible light output in every half cycle of the applied sustain pulse. The overall luminance of the Plasma Display is the cumulative of the number of sustain pulses applied in different subfields required to demonstrate particular gray level.
The drawback of the PDP is low luminous efficacy which is defined as the ratio of the total light output (luminance) to the power consumed in generating it. Low luminous efficacy in the conventional PDP contributes to high electrical power consumption for operation. Lower efficacy in PDP results from various factors like ion heating, losses to the walls & Phosphor ability to convert VUV to visible light conversion. It is noted in various approaches that the change in driving waveform and modification in discharge cell structure improve the performance of the plasma displays remarkably. At present various efforts are on to improve the luminous efficacy of PDP though modification of the driving waveform.
In AC-PDP, a capacitance exists between sustain (X) and scan (Y) electrodes. This capacitance acts as capacitive load between the electrodes while sustaining. Conventionally sustain waveforms (Figure3) following ADS (Address display separated) are used in driving PDP. This waveform suffers from the drawback that it uses high operation voltage (190-210 volts) leading to high capacitive losses. This waveform allows sufficient time for ions to gain energy and dump it on cathode thus leading to higher ion heating losses. This waveform also allows build up of positive charges on the address electrodes (A) resulting in phosphor erosion and thus deteriorates the operational life time of the plasma display panels.
US 2005/0195134 A1 patent proposes a driving method for a plasma display panel capable of prolonging a life span of the plasma display panel and improving luminous efficiency. This is achieved by applying bipolar pulses to sustain electrodes which decreases the accumulation of positive charges in address electrodes and lowers the capacitive losses.
In aforementioned prior art, the light emission occur during initial period of applied potential the remaining period of the sustain voltage does not generate light output, rather provides sufficient time to ions to gain translational energy which is dumped on the cathode of discharge cell surface during each half-cycle and resulting in higher sustain current and hence high power consumption.
In this invention the inventors propose a Mix-Mode sustain driving waveform which limits the ion heating losses through asymmetric short bipolar pulse width and uses the left over time in each half cycle to generate second light output through participation of the address discharge.
OBJECT OF THE INVENTION
Luminous efficacy of conventional AC PDP is low because of low brightness and high power consumption. The prime objective of this invention is to provide a method for driving a PDP with reduced power consumption and enhanced brightness.
Yet another objective of the invention is to improve luminous efficacy of the AC-PDP by improving brightness by enhancing light emission at least twice during each half cycle of sustain pulse.
Yet another objective of the present invention is to provide a driving scheme for enhancing luminance of the primary discharge.
Yet another objective of the present invention is to provide a driving scheme for enhancing luminance by creating a secondary discharge in same sustain half cycle
Yet another objective of the present invention is to provide a driving scheme for application of asymmetric bi-polar sustain voltages on each of the sustain electrodes to reduce ion heating losses.
Yet another objective of the present invention is to provide a driving scheme for lower capacitive losses by application of asymmetric bi-polar sustain pulses.
STATEMENT OF INVENTION
Accordingly this invention provides a method of driving a plasma display panel having at least two electrodes forming discharge cells at the intersection of the electrodes, i.e. address (A), scan (Y) and sustain (X) electrodes and visual effects are displayed on PDP by application of driving signals to said electrodes wherein one frame of image information is divided into numbers of subfields and each subfields has reset period, address period and sustain period as shown in figure 2, The waveform used in each subfield is shown in figure 5, the sustain pulse of shorter pulse-width of the negative polarity and amplitude Vx is applied to the X - electrode, and the wider pulse-width positive polarity pulse of amplitude Vy is applied to the Y-electrode during one half cycle. The amplitude Vx and Vy may be equal or different, The sum of the amplitudes of the positive and negative voltage pulses is the total sustain voltage (Vs), the rise time of the positive polarity and the negative polarity sustain pulse may vary from 10 ns to 500 ns respectively. The pulse width of the positive polarity pulse and the negative polarity may be different and may vary in the range of 100ns to 5000ns, the negative sustain pulse is divided in at least two pulses of narrow pulse widths. The pulse widths and the amplitudes of these two negative pulses may be equal or different.
In the embodiment of present invention Positive polarity Address pulse is applied on the A- electrode superimposing the second narrow negative sustain pulse of same half cycle. In another embodiment of the present invention the Positive polarity Address pulses are applied on the A- electrode superimposing the first and second narrow negative sustain pulse of same half cycle, The pulse widths and the amplitudes of the two address pulses in sustain period may be equal or different.
BREIF DESCRIPTION OF DRAWINGS:
The accompanying drawings, which are incorporated in and constitute a part of specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of invention.
FIG. 1 Illustrates a cross section view of the panel with straight barrier ribs used for AC PDP.
FIG. 2 Illustrates the single frame structure ADS (Address Display Separated), corresponding number of subfields (SF1-SF8), division of each subfield into reset period, address (or scan) period and sustain period.
FIG. 3 Illustrates the ADS (Address Display separated) driving waveform applied to all three electrodes namely Y scan, X sustain used in the PDP.
FIG. 4 Illustrates the ADS driving waveform, with symmetric bi-polar sustain voltage pulses, applied to the X & Y display electrode.
FIG. 5 Illustrates the ADS driving waveform, with asymmetric bi-polar sustain voltage pulses applied to the X & Y display electrode. Two negative short pulse width pulses of increasing amplitude is applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Address pulse at A-electrode is super imposed on the second negative polarity pulse.
FIG. 6 Illustrates the ADS driving waveform, with asymmetric bi-polar sustain voltage pulses applied to the X & Y display electrode. Two negative short pulse width pulses of equal amplitude is applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Positive polarity Address pulse at A-electrode is super imposed on the second negative polarity pulse.
FIG. 7 Illustrates the ADS driving waveform, with asymmetric bi-polar sustain voltage pulses applied to the X & Y display electrode. Negative pulses of short pulse width of increasing amplitude are applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Positive
polarity Address pulses of increasing amplitude at A-electrode are superimposed on the first and second negative polarity pulse.
FIG. 8 Illustrates the ADS driving waveform, with asymmetric bi-polar sustain voltage pulses applied to the X & Y display electrode. A negative pulse of wide width range (500ns - 5microsec) & higher amplitude is applied to one of the display electrode and narrow pulse of the shorter amplitude is applied to the other display electrode. The positive polarity address pulse is applied to the A -electrode after the narrow positive pulse come to the ground level.
DETAILED DESCRIPTION OF DRAWINGS:
In the following detailed descriptions, various exemplary embodiments of the invention has been shown and described, simply to illustrate a best mode contemplated by inventors for carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly drawings and descriptions are to be regarded as illustrative in nature, and not restrictive.
In some figures, some parts not related to description have been omitted for the better understanding of the present invention, and through out the specification same reference numeral is assigned to the same parts. However the numerals related to the temporal sequence of waveform in FIG. 4 to FIG. 8 are same and denoted with alpha-numeral sequence as t1, t5, t10 etc. Also the temporal sequence numerals of FIG. 4 to FIG. 7 are used to illustrate different waveforms of the present invention. The first and second electrodes are referred as terminals of the capacitor forming discharge cells.
In reference to above mentioned figures, the ground voltage (GND) is referred as 0 V and all the voltages are measured with respect to GND. Also the sustain voltage is denoted as Vs herein after. When a terminal of the capacitor forming discharge cell between the X & Y electrode is connected to negative or positive voltage source through switches, the time taken by voltage pulse to attain the maximum applied voltage is referred as rise-time, time for which voltage is maintained at maximum level is referred as ON time, time taken to fall from maximum applied voltage to lower voltage / GND level is referred as fall-time and time for which GND voltage is maintained at the terminal of the capacitor forming discharge cell is referred as OFF time.
Hereinafter, a description will be given for the method for driving an exemplary embodiment PDP for enhanced brightness and limiting discharge current according to this invention with reference to accompanying drawings.
FIG. 1: Illustrates the structure a micro discharge cells forming sub-pixels and pixels for display of images. As in figure 1, the front glass substrate (1) and back glass substrate (2) are shown. In the front glass substrate (1), display electrodes are made of transparent ITO sheet (3). To reduce the resistance of the display electrode, opaque electrically conducting bus electrodes (4) are made over the ITO electrodes. The display electrode is covered with a transparent dielectric layer (5) to limit the discharge current. Then the electron emissive layer (6) is deposited over the transparent dielectric layer (5). On the back glass substrate (2), a plurality of address electrodes (7) are formed with one address electrode (7) is formed in each sub-pixel. The address electrodes (7) are covered with a dielectric layer (8) to limit the discharge current and for light reflection. The straight channel barrier ribs (9) are formed over the dielectric layer (8). The R (10a), G (10b), B (10c) phosphor layers are formed in the barrier rib (9) channel spaces.
FIG.2: Illustrates the single frame structure comprised of different subfields (SF1-SF8) and each subfield divided into reset period, address (or scan) period and sustain period with appropriate number of sustains representing different gray levels. The different combination of subfields is fired to produce desired colors for true reproduction of the visual effects.
FIG. 3 Illustrates the conventional ADS unipolar driving waveform of surface discharge type AC PDP. In this figure, the driving voltage waveforms are applied to the corresponding three electrodes Y (scan), X (sustain) and A (address). The driving scheme includes number of subfields and each subfield introduces three periods such as reset period, address period and sustain period. During one subfield three driving waveforms are applied simultaneously to three electrodes. During the reset period, the scan waveform (Y scan) introduces ramp-up and ramp-down stage, the ground voltage (0V) is maintained to the sustain electrode (X sustain) up to ramp-up stage and meanwhile the ground voltage is maintained at the address electrode (A address) up to ramp-down period. Before starting the ramp down period the sustain voltage or less than sustain voltage is applied to the sustain electrode (X sustain) up to end of the address period, this voltage is called "X shelf Voltage (Vx shelf)". During the address period, the negative scan pulse is applied to the scan electrode for scanning the address lines and simultaneously the positive address pulse of address voltage (e.g. 70V) is applied to the address electrode for selecting the particular line. During the Sustain period, the alternating sustaining pulses are applied to the scan and sustain electrode for creating the sustain discharge of selected cells.
In the reset period, ramp up voltage is applied to the scan electrode Y that rises from Vsus (e.g. 200V) to predetermined reset voltage level ,V reset (e.g. 270V). The ramp up voltage causes discharge at the cell in the entire screen. The ramp up discharge serves to build the wall charges on the dielectric surface of three electrodes.
The reset pulse of ramp down waveform is provided to the scan electrode Y during ramp down period that goes down from scan base voltage level, Vsus ( e.g. 200V) to negative bias voltage level, -V y( e.g. -40V).The reset pulse of ramp down waveform causes discharge i.e. weak erasure discharge at each of the discharge cell to erase a portion of the wall charges from the electrode Y, X and A excessively formed and simultaneously serve to build the same charge formation on the three electrodes and leads to stable address discharge .
The pulse of X shelf voltage waveform is applied to the Sustain electrode X starting from earlier ramp down period to the end of address period that rises from ground potential (0V) to the sustain voltage or less than sustain voltage say Vxshelf (e.g. 185V).This voltage waveform introduces the sharp transition that controls the strong light emission during the reset period.
In the address period, the negative pulse of scanning voltage waveform Vscan (e.g. 80V) is applied to the scan electrodes Y and simultaneously the positive pulse of address voltage Vadd (e.g.70V) is applied to the address electrodes A The resultant voltage is added to the wall voltage generated ramp down discharge to cause the stable address discharge for selecting the cells.
In sustain period, the alternating pulses of sustain voltage waveform are applied to the scan Y and sustain X electrode. The sustain voltage Vs (e.g.200V) is added to the wall voltage produced in the address discharge enough to create the strong sustain discharge i.e. surface discharge between the scan Y and sustain X electrode. This discharge produces the gray scale image on the pre-addressed cells.
The driving waveform used in driving of AC PDP as shown in FIG.3 has some drawbacks. This sustain waveform could not limit the discharge ion current and restricts the utilization of electron energy for excitation resulting in low luminous efficacy of the panel.
FIG. 4 illustrates the waveform that comprised of the reset period, address period and the sustain period with bipolar sustain voltage pulses applied on each of the X and Y sustain display electrode.
In the reset period, the voltage is applied on the X electrode at time t1 till it attains the peak voltage of -Vs/2 at time t2. Simultaneously at time t1, the voltage is applied on Y electrode that attains the peak voltage of +Vs/2 at time t2. A ramp up voltage is applied on Y electrode at time t3 till the voltage rises to (Vs/2(e.g. 100V) + Vreset (e.g. 270V)) at time t8. This ramp up waveform in the reset period is used to create the wall charges of positive polarity on X and negative charges on Y electrode. Thereafter the voltage on the Y electrode is brought down to from (Vs/2+ V reset) to (Vs/2) at time t10. The voltage on the X electrode is pulled up from -Vs/2 to Ground potential at time t11. The next phase of the reset period is the ramp down waveform. A ramp down voltage is applied on the Y electrode
which was at scan base voltage level, Vsus (e.g. 100V) from the time t10 to the time t13 till it reaches to a negative bias voltage level, -V y (e.g. -40V) at time t16. After the voltage of -Vy is achieved at point t16 another voltage called Vxshelf (e.g. +100V amplitude) is applied on the X electrode before the ramp down period at time t12 and is maintained at this voltage till the end of the Addressing period (i.e. till the time t28).This ramp down period of the reset pulse on Y electrode is used to erase the excess wall charges from the Y, X electrodes. The residual uniformly distributed wall charges on these electrodes produce a stable address discharge in the address phase. This total period starting from t1 to t16 is called the reset period.
The address period starts from the time t16 and continues to the time t28. In this address period a negative scanning pulse voltage Vscan (e.g. 80V) is applied on the scan Y electrodes and a positive pulse of address voltage Vadd (e.g.70V) is applied to the address electrodes A in synchronous with negative scanning pulse of scan Y electrodes. The resultant voltage of Vscan and Vadd is used to produce address discharge within the cells.
The sustain pulses initiates from the time t30. A voltage (say +V or positive voltage) is applied on Y electrode at time t30 with a rise time of order of 25-700 ns, to time t31 where the voltage on the Y electrode raises to +Vs/2 from ground. Simultaneously a voltage with opposite polarity (say -V or negative voltage) is applied on the X electrode with a rise time equal to that of the rise time of the voltage applied on the Y electrode, at time t30 to the time t31 where the X electrode reaches the voltage of -Vs/2. The voltages on both the Y and X electrodes remain at +Vs/2 and -Vs/2 respectively till the time t34. The Y electrode is brought to the Ground voltage from the time t34 to time t35 with the fall time equaling the rise time with which the Y electrode is charged to the voltage of +Vs/2. Similarly, the X electrode is brought to the Ground voltage from the time t34 to time t35 with the fall time equaling the rise time with which the X electrode is charged to the voltage of +Vs/2. This completes the half of the sustain cycle. In the next cycle, the polarities of the voltages applied on the Y and the X electrodes are reversed. At time t36, a negative voltage is applied on the Y electrode which rises the voltage to -Vs/2 from the Ground voltage at time t37 with the rise time equaling the rise time with which the Y electrode is charged to the voltage of +Vs/2 in the first half cycle. Simultaneously a voltage is applied on the X electrode with a rise time equal to that of the rise time of the voltage applied on the Y electrode in the second half of the sustain cycle, at time t36 to the time t37 where the X electrode reaches the voltage of +Vs/2. Both the electrodes, i.e. Y and X electrodes retain their respective voltages till the time t40. The Y electrode is brought to the Ground voltage from the time t40 to time t41 with the fall time equaling the rise time with which the Y electrode is charged to the voltage of -Vs/2 in the second half of the sustain cycle. Similarly, the X electrode is brought to the Ground (GND) voltage from the time t40 to time t41 with the fall time equaling the rise time with which the Y electrode is brought to
Ground voltage in the second half of sustain cycle. This completes the full sustain cycle.
FIG. 5 illustrates the waveform that comprised of the reset period, Address period and sustain period with the conventional ADS driving waveform, with asymmetric bi-polar sustain voltage pulses applied to the X & Y display electrode. Two negative short pulse-width pulses of increasing amplitude are applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Address pulse at A-electrode is super imposed on the second negative polarity pulse
The reset period and the address period operate in the same manner as described for the waveform shown in the fig. 4.
Sustain period starts from the time t29 and the net applied sustain voltage (Vs) is the sum of the voltages applied to X (Vx) & Y-electrode (Vy) which peaks at time t30. The potential difference (Vs) between the X&Y electrodes is added to the wall voltage (created by wall charges) of the addressing phase results the forms of intense sustain discharge. After the discharge initiation the charges (ions & electrons) accumulate over the dielectric surface (wall) to create a wall voltage opposing the applied sustain voltage resulting in extinction of the discharge. These wall charges, forming the wall voltage, remain accumulated over the dielectric wall even after the extinction of the discharge. These wall charges help to initiate the next discharge in second half cycle of the opposite polarity. How ever to create a second discharge in remaining time span of the first half cycle, it is required to create the sufficient potential difference (above breakdown voltage) against the wall voltage of the previous sustain discharge. To achieve this condition, a second negative polarity pulse of higher amplitude (50-250 V) is applied to the X-electrode at t36. Simultaneously a positive voltage pulse (10-110 V) is applied to the address (A) electrode at the same point t36. Now the potential difference between X and A-electrode will be above the breakdown voltage to ignite a discharge between the X-electrode and A-electrode which further sustains the X -Y discharge using their space charges. This is resulted in the form of a second light output in the same half cycle. This secondary discharge will increase the luminance of the plasma display. In the similar manner, using the further narrower pulses of higher amplitudes, more discharge events can be initiated to enhance the luminance of the PDP.
FIG. 6 Illustrates the conventional ADS driving waveform, with asymmetric bipolar sustain voltage pulses applied to the X&Y display electrode. Two negative short pulse width pulses of equal amplitude are applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Positive polarity Address pulse at A-electrode is superimposed on the second negative polarity pulse.
The reset period and the address period remain the same as shown in FIG. 4.
The sustain period starts from t30 and the net applied sustain voltage (Vs) is the sum of the voltages applied to X (Vx) & Y-electrode (Vy) which peaks at time t31. The potential difference (Vs) between the X&Y electrodes is added to the wall voltage (created by wall charges) of the addressing phase and it results in the form of intense first sustain discharge.
Second discharge is initiated between the display X - electrode and the address A - electrode. This will further sustain the coplanar discharge. In this waveform the equal voltage amplitude of the negative polarity voltage pulses facilitates the use of the single voltage source for both the negative pulses. The required potential difference for breakdown is achieved thru increasing the address voltage in the range of 50 -100 V.
FIG. 7 Illustrates the conventional ADS driving waveform, with asymmetric bipolar sustain voltage pulses applied to the X & Y display electrode. Two negative short pulse width pulses of increasing amplitude are applied to one of the display electrode. A wide pulse of the positive polarity is applied to other display electrode. Two Positive polarities Address pulses of increasing / equal amplitude are applied at A-electrode and super imposed on the first and second negative polarity pulse.
The first address pulse superimposing first short sustain pulse on X electrode is used to enhance the discharge efficiency of the primary discharge. The second address pulse superimposing second sustain pulse on X electrode is used to create the secondary discharge in the same half cycle. This increases the overall luminance of the plasma display.
FIG. 8 Illustrates the conventional ADS driving waveform, with asymmetric bipolar sustain voltage pulses applied to the X & Y display electrode. A wide width negative pulse of higher amplitude is applied to one of the display electrode and narrow pulse of the shorter amplitude is applied to the other display electrode. The positive polarity address pulse is applied to the A - electrode after the narrow positive pulse come to the ground level. This embodiment provides the similar results as above mentioned embodiments in figure 5 to 7.
In the embodiment of present invention, voltage sources on X and Y electrodes are interchanged to get the same desired effect. Moreover, appropriate temporal sequence arrangement of applied voltages result in square-waveform, triangular waveform, sine waveform etc. While this invention has been described in connection with what is presently considered to be most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements possible with in the spirit and scope of the appended claims.

What is claimed is
1. A method of driving a plasma display panel having at least two electrodes forming discharge cells at the intersection of the electrodes, i.e. address (A), scan (Y) and sustain (X) electrodes and visual effects are displayed on PDP by application of driving signals to said electrodes wherein one frame of image information is divided into numbers of subfields and each subfields has reset period, address period and sustain period as shown in figure 2. The waveform used in each subfield is shown in figure 5.
Wherein,
a) The sustain pulse of shorter pulse-width with the negative polarity and of amplitude Vx is applied to the X - electrode, and the wider pulse-width positive polarity pulse of amplitude Vy is applied to the Y-electrode during one half cycle. The amplitude Vx and Vy may be equal or different.
b) The sum of the amplitudes of the positive and negative voltage pulses is the total sustain voltage (Vs)
c) The rise time of the positive polarity (t30-t29) sustain pulse and the negative polarity (t31-t30) sustain pulse may vary from 10 ns to 500 ns.
d) The pulse width of the positive polarity pulse (t37-t30) and the negative polarity (t31-t30) may be same or different and vary in the range of 100ns to 5000ns.
e) The negative sustain pulse is divided in at least two pulses of narrow pulse width. The pulse width and the amplitude of the two negative pulses may be equal or different.
f) Positive polarity Address pulse is applied on the A- electrode superimposing the second narrow negative sustain pulse of same half cycle.
g) Positive polarity Address pulses are applied on the A- electrode superimposing the first and second narrow negative sustain pulse of same half cycle.
h) The pulse width and the amplitude of the two address pulses in sustain period may be equal or different.
2. The waveform as claimed in claim 1 will provide at least two discharges in one half cycle of the sustain pulse.
3. The waveform as claimed in claiml is used to reduce the displacement current or capacitive losses.
4. The waveform as claimed in claiml is used to reduce the discharge current and hence the power consumption.
5. The waveform as claimed in claiml is used to enhance the luminance and the luminous efficacy of the PDP.
6. The similar enhancement in luminance and luminous efficacy is achieved by reversing the polarity of wider pulse-width pulse as shown in figure 8.