DESC:TECHNICAL FIELD

The present subject matter is related in general to the field of power electronics, more particularly, but not exclusively to an apparatus and a method for equalizing voltage for efficient energy storage in an electrical system to prolong battery life.

BACKGROUND

Batteries are employed in many applications for energy storage. In order to maximize the life of a battery, the battery must be charged and discharged within manufacturer specified current and voltage limits. Overcharge and over-discharge of the battery can significantly reduce the battery life, thereby, leading to poor cost-effectiveness of an entire energy storage system. Overcharge occurs when the battery voltage exceeds a maximum voltage limit during charging and over-discharge happens when a battery voltage falls below a minimum discharge voltage of the battery during discharge. Generally, the Battery Management System (BMS) ensures that the battery voltage remains within the minimum and maximum bounds of terminal voltage. The terminal voltage of a battery cell is typically small. So, in medium to high power electronics applications, a number of batteries are connected in series to achieve high terminal voltage. A bi-directional power converter is normally employed to charge and discharge the entire array of battery in such applications. Ideally, the batteries connected in series have same terminal voltages as they have same charge capacity and they are charged and discharged together. But, due to unequal aging, manufacturing tolerance and unequal temperature distribution, charge capacities of the batteries in an array of battery can be slightly different from each other. Hence, if the BMS monitors only the terminal voltage of the series connected battery array, then the battery having lower capacity than others, can be overcharged and over-discharged even if the voltage of the array of battery is within acceptable limits. Instead, if the BMS monitors each battery voltage, then it must stop charging or discharging when the terminal voltage of the battery with lowest capacity, reaches its limit, thereby, leading to under-utilization of all other batteries. So, it is necessary to use a voltage equalizer circuit, which can equalize the voltages of all the series connected batteries leading to prolong battery life. Analogously, the voltage equalizer circuit tries to achieve the same purpose of equalizing voltages for series connected ultra-capacitors.

The information disclosed in this background of the disclosure section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

SUMMARY

In an embodiment, the present disclosure may relate to a voltage equalizer circuit for equalizing voltage on a plurality of power sources connected in series, the voltage equalizer circuit comprising a half-bridge circuit connected to each power source in the plurality of power sources, wherein the half-bridge circuit comprises first and second electronic switches connected in series and a first capacitor connected in parallel with the each power source, a controller configured to generate gate drive signal for each of the first and second electronic switches, wherein the gate drive signal is a square wave signal, a second capacitor connected with an inductor in series to a common node of the first and second electronic switches, and a third capacitor connected in parallel to each of the first and second electronic switches for soft-switching.

In an embodiment, the present disclosure may relate to a method for equalizing voltage on a plurality of power sources connected in series using a voltage equalizer circuit, the voltage equalizer circuit comprising a half-bridge circuit including first and second electronic switches connected in series and a first capacitor connected in parallel with the each power source, a second capacitor connected with an inductor in series to a common node of the first and second electronic switches, and a third capacitor connected in parallel to each of the first and second electronic switches for soft-switching, the method comprising the steps of connecting the half-bridge circuit to each power source in the plurality of power sources, and generating, by a controller, gate drive signal for each of the first and second electronic switches, wherein the gate drive signal is a square wave signal.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and together with the description, serve to explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described below, by way of example only, and with reference to the accompanying figures.

Fig. 1a illustrates a schematic circuit diagram of a voltage equalizer circuit for equalizing voltages of a plurality of power sources connected in series in accordance with some embodiments of the present disclosure.

Fig. 1b illustrates a square wave function, Sq(t), in accordance with some embodiments of the present disclosure.

Fig. 2a shows a schematic circuit diagram of kth half-bridge circuit along with first, second and third capacitors and inductor for kth power source in accordance with some embodiments of the present disclosure.

Fig. 2b shows a diagram with the waveforms of modulation signals and corresponding voltages and currents in kth voltage equalizer circuit for kth power source in accordance with some embodiments of the present disclosure.

Fig. 3 illustrates a schematic circuit diagram in a modular format of voltage equalizer circuits in accordance with some embodiments of present disclosure.

Fig. 4 illustrates a flowchart showing control flow for a voltage equalizer circuit in accordance with some embodiments of the present disclosure.

Fig. 5 illustrates a flowchart showing a voltage equalization method for diagnosing state of a power source in accordance with some embodiments of the present disclosure.

It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION

In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.

In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.

Embodiments of the present disclosure relate to a voltage equalizer circuit and a method for equalizing voltage on a plurality of power sources connected in series to prolong battery life. The voltage equalizer circuit presented in this application offers a multi-cell to multi-cell power transfer, thus, providing fast equalization of power sources such as batteries, ultra-capacitors, and the like, with simple circuit implementation and minimum circulation of power. The present invention, also, achieves soft-switching to improve efficiency of the equalization process and reduces switching noise. The cell currents do not reduce with progress in voltage equalization, which helps to achieve faster voltage equalization compared to many existing multi-cell to multi-cell topologies. For batteries subjected to high charge-discharge rate, ultra-capacitors and hybrid ultra-capacitors, fast equalization is necessary. The voltage equalizer circuit presented in this application is useful for these applications. Furthermore, a novel modularization technique is presented for the voltage equalizer circuit to ensure that capacitors of different modules have same voltage ratings irrespective of number of modules connected in series. This modularization approach, also, provides a direct charge transfer path from any battery of one module to any battery of another module. Therefore, the speed of modularization does not reduce with increasing number of modules.

Fig. 1a illustrates a schematic circuit diagram of a voltage equalizer circuit for equalizing voltage on a plurality of power sources connected in series in accordance with some embodiments of the present disclosure.

A power source 1011 may be connected to a half-bridge circuit of the voltage equalizer circuit. Analogously, a plurality of power sources 1011, 1012, 1013,…101n may be connected in series and may be connected to corresponding half-bridge circuits as shown in fig. 1a. The power sources may include, but not limited to, batteries, ultra-capacitors, hybrid ultra-capacitors, fuel cells that are connected as a stack and solar modules that are connected in series as a string array. A person skilled in the art would understand that, any power source, not mentioned explicitly, may also be used as the power source in the present disclosure. The voltage equalizer circuit may comprise a half-bridge circuit connected to each power source in the plurality of power sources 1011, 1012, 1013,…101n. The half-bridge circuit may in turn comprise two switches i.e. first electronic switch 10311 and second electronic switch 10312. These two electronic switches may be connected in series. Low voltage rated semiconductor devices such as Si MOSFETs, GaN MOSFETs, and the like may be used as electronic switches or switching devices for the half-bridge circuit. The voltage equalizer circuit may further comprise a capacitor Cdc (also, may be referred as first capacitor) connected in parallel with each power source. Another capacitor Cs (also, may be referred as third capacitor) and a diode may be connected in parallel to each of the first electronic switch 10311 and second electronic switch 10312. The presence of capacitor Cs would allow soft-switching of the first electronic switch 10311 and second electronic switch 10312. Furthermore, a DC blocking capacitor C (also, may be referred as second capacitor) may be connected in series with an inductor L to a common node/pole of the first electronic switch 10311 and second electronic switch 10312. The presence of DC blocking capacitor C and inductor L would block DC component and limit switching frequency component, respectively. The voltage equalizer circuit may comprise a controller (not shown in fig.) configured to generate gate drive signal for each of the first and second electronic switches. Here, a square-wave modulation signal may be used to achieve multi-cell to multi-cell simultaneous charge transfer while ensuring soft-switching of all the switching devices. Furthermore, the controller may control the gate drive signal for each of the first electronic switch 10311 and second electronic switch 10312 based on voltage of the each power source. The gate drive signal for each of the first electronic switch 10311 and second electronic switch 10312 may be separated by a minimum dead time required for soft-switching.

Here, the term half-bridge circuit in the present application may, also, be referred as half-bridge converter or just a converter.

The working of fig. 1a is explained hereafter. The modulation signal used here may be square wave with suitable phase-shifts. The modulation signal for the half-bridge circuit of a discharging battery may have a leading phase compared to that of a charging battery. The top switches in the half-bridge circuits may be controlled by phase shifted square wave gate signals with 0.5 duty ratio. For describing this signal and subsequent analysis, a periodic function Sq(t) of time period Ts may be defined as shown in fig. 1b. The gate signal reference of the top switch of kth voltage equalizer circuit may be given by,

Here, dkTs may be the phase of the square-wave for kth voltage equalizer circuit. The power flow may depend on the phases of the gate signals. If the phase of the gate signal of a voltage equalizer circuit for a battery may be leading compared to another battery, then the power flows from the former battery to the later battery. The phase may be set to 0 for discharging voltage equalizer circuits and -dTs for charging batteries. The gate signals for all discharging batteries may be the same and the gate signal of the top device may be given by,

The gate signals for all charging batteries may, also, be the same and gate signal for the top device may be given by,

For all the batteries which are not to be charged or discharged, both the switches in the half-bridge circuit may be turned off. Hence, these batteries may not take part in power transfer. The condition for power flow from the discharging batteries to charging batteries may be given by,

If a battery voltage is within the acceptable voltage range then both the switches of the corresponding half-bridge circuit may be turned off so that the battery does not take part in the voltage equalization process.

Fig. 2a shows a schematic circuit diagram of kth half-bridge circuit along with first, second and third capacitors and inductor of the voltage equalizer circuit for kth power source in accordance with some embodiments of the present disclosure. Fig. 2b shows a diagram with the waveforms of modulation signals and corresponding voltages and currents in kth voltage equalizer circuit for kth power source in accordance with some embodiments of the present disclosure. The fig. 2a and fig. 2b will be explained together below.

Fig. 2a shows the kth half-bridge circuit of the voltage equalizer circuit where the kth battery may be discharging. The current and voltage waveforms of kth voltage equalizer circuit are shown in fig. 2b. It may be observed from fig. 2b, the turn-on transition for the top device begins at t = 0. However, the device turns on only after a small dead time. The inductor current may be negative during this transition. Since both the switches may turned off during dead time, the negative current may flow through the top diode and the top device may turn on under zero voltage switching (ZVS) condition. The condition for ensuring ZVS is that inductor current is negative when the switch turns on. The inductor current may not be controlled in closed loop. However, it may be possible to find an upper limit on inductor current at t = 0 for all battery condition as shown below,

Similarly, the turn-on transition for the bottom device may begin at t = Ts/2. During the dead time, the inductor current may be positive which may have the following lower limit,

Hence, the current may flow through the bottom diode and the bottom switch may turn on under ZVS condition. Thus, ZVS turn on is ensured for all the switches of half-bridge circuits for discharging batteries under all load conditions. A similar explanation may show that ZVS is ensured for half-bridge circuits for charging batteries as well.

In order to achieve soft-switching during turn off transitions, an additional capacitor, Cs i.e. the third capacitor may be connected in parallel with each switch as shown in fig. 1a. The energy stored in these capacitors during turn off transition may be recycled during turn on transition. The presence of Cs capacitors may reduce power loss during the turn off transition by slowing down the voltage rise across the switches. The value of Cs may be large enough so that the reduced power loss is small compared to a hard-switched turn off transition. Higher value of Cs may reduce power loss in switch but increases required dead time. The required dead time must be more than capacitor voltage rise time tr. It may be assumed that tf << tr and inductor current does not change significantly in the duration tr. Here, tf may be the current fall time. Then the minimum required dead time td(min) may be given by,

Where, ik(0) may be the inductor current for kth half-bridge circuit at t = 0.

In brief, the gate drive signal for each of the first and second electronic switches may be separated by a minimum dead time required for soft-switching.

Fig. 3 illustrates a schematic circuit diagram in a modular format of voltage equalizer circuits in accordance with some embodiments of present disclosure.

In fig. 3, a plurality of the half-bridge circuit, the inductor, the first capacitor, the second capacitor and the third capacitor are connected in series to form a module. Here, each of the plurality of the half-bridge circuit is connected to corresponding power source in the plurality of power sources. Two such modules are connected in series to form a modular circuit as shown in fig. 3. In principle, any number of modules may be formed and connected in series. For sake of explanation, the power source used here may a battery. The power source may be, but not limited to, an ultra-capacitor, a hybrid ultra-capacitor, a fuel cell or a solar module. As the number of batteries increases, multiple modules are connected together using additional capacitor Cmod (also, may be referred as fourth capacitor) and an additional low power rated resistor Rc as shown in fig. 3. The fourth capacitor is connected in series between common points of inductors of any two adjacent modules to block DC voltage between the common points of inductors of two adjacent modules and the resistor is connected between a module reference and a node between the second capacitor and the inductor for the first half-bridge converter of each of the module to reduce the DC voltage of common node of the inductors to the module reference and to ensure that voltage of second capacitor does not change with number of modules. This modularization method ensures that voltage rating of capacitor C i.e. the second capacitor does not depend on the number of modules connected. This modularization method, also, provides a direct charge transfer path between any battery of one module and any battery of another module.

The necessity of modularization is explained below. The voltage blocked by the capacitor C i.e. the second capacitor in the kth voltage equalizer circuit in fig. 1a may be expressed as follows,

Where Vo_dc may be the DC component of the voltage of the common inductor node with respect to the ground in fig. 1a. So, the maximum voltage may be blocked by the capacitor C i.e. the second capacitor of nth voltage equalizer circuit and it may be given below,

The above expression may indicate that the voltage rating of capacitor C i.e. the second capacitor increases with the number of batteries. Hence, for a large number of batteries in series, the required voltage rating of capacitor C may become high and this capacitor may become costly and bulky. Furthermore, once the voltage rating of the capacitor C may be decided, the maximum number of batteries may, also, be decided. Hence, the voltage equalizer circuit designed for a particular battery bank may not be used for another battery bank with a higher number of batteries. A modular voltage equalizer may have multiple modules to equalize a large number of batteries in series. Each module may be connected to a small number of batteries. If there are p number of modules and each module can be connected to n batteries then, total pn number of batteries may be equalized. The number of modules may be adjusted according to the total number of batteries. Hence, the same module may be used for battery banks with different numbers of batteries. Again, since the number of batteries in each module may be small, the voltage rating of capacitor C may, also, be small leading to a less costly and compact equalizer design. However, the modularization technique should have the following properties, (1) voltage rating of capacitor C should be independent of the number of modules connected, and (2) there should be a direct charge transfer path from any cell/power source in one module to any cell/power source in another module so that voltage equalization speed does not reduce with the number of modules.

In fig. 3, each module has the additional capacitor Cmod and the resistor Rc. Due to the presence of the capacitors C i.e. the second capacitors, the current in resistor Rc may be purely an AC quantity. Hence, the DC component of the pole voltage of the first half-bridge circuit of each module may be dropped only across the capacitor Cmod. Using Kirchhoff's Voltage Law (KVL) averaged over a switching period the maximum possible voltage of capacitor C i.e. the second capacitor in each module may be obtained as follows,

Where, Vb_max is the maximum possible battery voltage. The value of the resistor Rc may be chosen to be high so that power loss in Rc is negligible compared to the power rating of the voltage equalizer circuit. The DC voltages of the inductor L common points of the two modules may not be the same. Hence, the DC blocking capacitor Cmod i.e. the fourth capacitor may be required to allow AC power flow between two modules. The maximum voltage stress on the capacitor Cmod may be given by,

The value of Cmod may be chosen to be large enough so that it offers negligible impedance at the switching frequency. Hence, it may be observed from fig. 3 that there is a direct path from any voltage equalizer circuit of a module to any voltage equalizer circuit of another module at the switching frequency. Therefore, the speed of voltage equalization does not reduce with the number of modules. The maximum voltage stress on capacitor C i.e. Vc_max does not depend on the number of modules connected. Hence, the voltage rating of capacitor C may be same for each module.

Fig. 4 illustrates a flowchart showing control flow for a voltage equalizer circuit in accordance with some embodiments of the present disclosure.

For sake of explanation, the control flow for the voltage equalizer circuit is explained here with respect to a battery as a power source. The power source may be, but not limited to, an ultra-capacitor, a hybrid ultra-capacitor, a fuel cell or a solar module. With reference to fig. 4, for each battery, a decision may be taken whether to charge it or discharge it or disconnect it from voltage equalization process. The voltages of all the batteries may be measured with voltage sensors (not shown in fig.). A low-cost non-isolated voltage sensor may be utilized for this sensing purpose. The average voltage of all the batteries may be given by,

A battery voltage may be considered to be in acceptable range if it is within a small tolerance voltage Vtol around Vavg. The value of Vtol may be decided based on a type of battery and the particular application. Hence, the upper threshold limit Vh and the lower threshold limit Vl of an acceptable voltage range may be defined as follows,

So, the voltage of the kth battery may be acceptable if,

If the above condition may not be valid then the kth battery is charged or discharged until it becomes equal to the average voltage Vavg. The above explanation implemented as control flow is shown in the form of flowchart in fig. 4. The flowchart, also, indicates how to set the modulation signals Sk, S'k of both the first electronic switch and the second electronic switch of kth voltage equalizer circuit based on Vbk i.e. kth battery voltage.

In brief, the controller (not shown in fig.) of the voltage equalizer circuit may be configured to produce the square wave gate drive signals for the first and second electronic switches, with a leading phase when a voltage of a power source is greater than a high threshold voltage, with a lagging phase when the voltage of the power source is lower than a low threshold voltage and no gate drive signals for the first and second controllable electronic switches when the voltage of the power source is lower than the high threshold voltage and higher than the low threshold voltage.

Fig. 5 illustrates a flowchart showing a voltage equalization method for diagnosing state of a power source in accordance with some embodiments of the present disclosure.

For sake of explanation, the power source considered here is a battery. The power source may be, but not limited to, an ultra-capacitor, a hybrid ultra-capacitor, a fuel cell or a solar module. With reference to fig. 5, if series-connected batteries of same charge capacities are charged or discharged from the same initial voltage, then their voltages should ideally be the same during the entire charge/discharge process. However, in practice, the charge capacities of different batteries are not identical due to unequal aging and manufacturing tolerances. The voltage of the battery with the lowest charge capacity will change faster than the voltages of other batteries although the same current flows through all the batteries. Hence, the voltage of the battery with the lowest charge capacity will diverge from the average voltage faster than other batteries.

The voltage equalization method for diagnosing state of a power source may monitor all the battery voltages and may decide which batteries to be charged and which batteries to be discharged. If a particular battery is selected for charging/discharging more frequently than other batteries, then this particular battery may have the lowest charge capacity among all the other batteries. If a particular battery is charged or discharged by the voltage equalizer most of the time, then it may be concluded that this particular battery has much lower charge capacity than expected charge capacity. Hence, this particular battery may have reached its cycle life and should be replaced by a new battery. The method to achieve this battery diagnostics task is shown in fig. 5. In order to determine the damaged battery, the following ratio for the kth battery is defined below,

The equalization time of the kth battery is given by the total time of charging and discharging of this battery by the voltage equalizer circuit. When this ratio becomes large then it may be concluded that the kth battery has lower capacity compared to other batteries. When this ratio exceeds a predefined threshold xth, the battery may be considered to be damaged and may be replaced by a new battery.

In brief, the controller (not shown in fig.) of the voltage equalizer circuit may be configured to measure equalization time for each of the plurality of power sources, wherein the equalization time is total time of charging and discharging of a power source. In the next step, the controller may calculate equalization ratio of the power source by using the equalization time of the power source and an average equalization time of the plurality of power sources. Following which the controller may compare the equalization ratio of the power source with a predefined threshold value and determine state of the power source based on the comparison. The state of the power source may be considered to be, damaged when the equalization ratio of the power source is greater than the predefined threshold value and normal when the equalization ratio of the power source is lesser than or equal to the predefined threshold value.

The voltage equalization circuit presented in this disclosure may be suitable for battery and ultra-capacitor banks whose voltage rating is in the range of 10V – 1000V and current rating in the range of 10A - 1000A.

Some of the advantages of the present disclosure are listed below.

In an embodiment, the present disclosure offers a multi-cell to multi-cell voltage equalization where the equalization current does not reduce with progress in voltage equalization. The power level of the voltage equalizer circuit is usually a small fraction of the power rating of the battery/ultra-capacitor bank. For a given power level, the voltage equalization will be faster if unnecessary charging and discharging can be avoided and all necessary charging and discharging can be done simultaneously. A multi-cell to multi-cell topology presented in the present application has following advantages: (1) charge transfer from multiple batteries to multiple batteries happens directly and simultaneously, and (2) the battery currents in the present invention do not depend on the voltage differences among the power sources and its equalization power does not reduce with time. Thus, the present invention achieves fast voltage equalization.

In an embodiment, the voltage equalizer circuit uses capacitors for isolation, which are compact and efficient than high frequency transformers typically used.

In an embodiment, the present invention uses the square wave signal modulation, which has following advantages: (1) the ratings of different passive circuit elements reduce significantly. Thus, the cost and size of the voltage equalizer circuit reduce, and (2) the generation of square wave modulation signals requires fewer computational resources compared to other methods such as the generation of the sinusoidal modulation signal. Hence, a square wave-based controller for the equalizer can be implemented with a low-cost processor.

In an embodiment, soft-switching in the voltage equalizer circuit leads to higher efficiency and enables high frequency circuit operation in comparison to most of the existing voltage equalizer topologies, which cannot achieve soft-switching.

In an embodiment, the voltage equalizer circuit of the present invention can achieve soft-switching for all battery condition. The circuit inherently possesses zero voltage switching during turn-off transition. Furthermore, a small additional capacitor is used to achieve zero voltage switching during turn-off transition. The value of this additional capacitor can be chosen to ensure that soft-switching is achieved for all battery/capacitor conditions.

In an embodiment, the modularization technique used for the voltage equalizer circuit in the present invention provides direct charge transfer path from any cell in one module to any cell in another module. Thus, the speed of voltage equalization does not reduce with number of modules.

In an embodiment, the voltage equalizer circuit offers simpler circuit implementation and control compared to the common energy bus based existing topology.

In an embodiment, the present invention uses a simple method to charge and discharge all the power sources to achieve voltage equalization. The method can be implemented in a digital controller with less computation resources.

In an embodiment, the present invention uses a voltage equalization method for power source diagnosis. The charging and discharging of any particular power source are actively decided by the voltage equalization method. Since a battery with low charge capacity compared to others will be charged/discharged frequently, the charging/discharging information can be used to detect any damaged or aged battery for replacement.

The described operations may be implemented as a method, system or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “non-transitory computer readable medium”, where a processor may read and execute the code from the computer readable medium. The processor is at least one of a microprocessor and a processor capable of processing and executing the queries. A non-transitory computer readable medium may include media such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. Further, non-transitory computer-readable media include all computer-readable media except for a transitory. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.).

The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the invention(s)” unless expressly specified otherwise.

The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.

The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.

A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary, a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention.

When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the invention need not include the device itself.

The illustrated operations of figs. 4 and 5 show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

REFERRAL NUMERALS:

Reference number Description
1011, 1012…101n Plurality of power sources
10311, 10312,…,103n1, 103n2 Plurality of electronic switches
101k kth power source
103k1 First electronic switch in kth half-bridge circuit
103k2 Second electronic switch in kth half-bridge circuit
301 Module 1
303 Module 2
,CLAIMS:We claim:

1. A voltage equalizer circuit for equalizing voltages of a plurality of power sources connected in series, the voltage equalizer circuit comprising:
a half-bridge circuit connected to each power source in the plurality of power sources, wherein the half-bridge circuit comprises first and second electronic switches connected in series and a first capacitor connected in parallel with the each power source;
a controller configured to generate gate drive signal for each of the first and second electronic switches, wherein the gate drive signal is a square wave signal;
a second capacitor connected with an inductor in series to a common node of the first and second electronic switches; and
a third capacitor connected in parallel to each of the first and second electronic switches for soft-switching.

2. The voltage equalizer circuit as claimed in claim 1, further comprising:
a plurality of the half-bridge circuit, the inductor, the first capacitor, the second capacitor and the third capacitor connected to the half-bridge and the plurality of power sources connected in series form a module, wherein each of the plurality of the half-bridge circuit is connected to corresponding power source in the plurality of power sources.

3. The voltage equalizer circuit as claimed in claim 2, further comprising:
a fourth capacitor connected in series between common points of inductors of any two adjacent modules to block DC voltage between the common points of inductors of the adjacent modules; and
a resistor connected between a module reference and a node between the second capacitor and the inductor for the first half-bridge converter of each of the module to reduce the DC voltage of the common node of the inductors to the module reference and to ensure that voltage of second capacitor does not change with number of modules.

4. The voltage equalizer circuit as claimed in claim 1, wherein the gate drive signal for each of the first and second electronic switches are controlled by the controller based on voltage of the each power source.

5. The voltage equalizer circuit as claimed in claim 1, wherein the gate drive signal for each of the first and second electronic switches is separated by a minimum dead time required for soft-switching.

6. The voltage equalizer circuit as claimed in claim 4, the controller is configured to produce the square wave gate drive signals for the first and second electronic switches,
with a leading phase when a voltage of a power source is greater than a high threshold voltage,
with a lagging phase when the voltage of the power source is lower than a low threshold voltage, and
no gate drive signals for the first and second controllable electronic switches when the voltage of the power source is lower than the high threshold voltage and higher than the low threshold voltage.

7. The voltage equalizer circuit as claimed in claim 1, the controller is configured to:
measure equalization time for each of the plurality of power sources, wherein the equalization time is total time of charging and discharging of a power source;
calculate equalization ratio of the power source by using the equalization time of the power source and an average equalization time of the plurality of power sources;
compare the equalization ratio of the power source with a predefined threshold value; and
determine state of the power source based on the comparison.

8. The voltage equalizer circuit as claimed in claim 7, wherein the state of the power source is considered to be,
damaged when the equalization ratio of the power source is greater than the predefined threshold value, and
normal when the equalization ratio of the power source is lesser than or equal to the predefined threshold value.

9. A method for equalizing voltages of a plurality of power sources connected in series using a voltage equalizer circuit, the voltage equalizer circuit comprising of a plurality of half-bridge circuits with one half-bridge circuit for each power source including first and second electronic switches connected in series and a first capacitor connected in parallel with the each power source, a second capacitor connected with an inductor in series to a common node of the first and second electronic switches, and a third capacitor connected in parallel to each of the first and second electronic switches for soft-switching, the method comprising the steps of:
connecting the half-bridge circuit to each power source in the plurality of power sources; and
generating, by a controller, gate drive signal for each of the first and second electronic switches,
wherein the gate drive signal is a square wave signal.

10. The method as claimed in claim 9, further comprising the steps of:
blocking, by a fourth capacitor connected in series between common points of inductors of any two adjacent modules, DC voltage between the common points of inductors of two adjacent modules, wherein the module comprises a plurality of the half-bridge circuit, the inductor, the first capacitor, the second capacitor, and the third capacitor connected to the half-bridge connected in series, wherein each of the plurality of the half-bridge circuit is connected to corresponding power source in the plurality of power sources; and
reducing the DC voltage of the common node of the inductors to the module reference in order to ensure that voltage rating of second capacitor does not depend on number of modules, by connecting a resistor between the module reference and a node between the second capacitor and the inductor for the first half-bridge circuit of each of the module.

11. The method as claimed in claim 9, further comprising the steps of:
controlling, by the controller, the gate drive signal for each of the first and second electronic switches based on voltage of the each power source.

12. The method as claimed in claim 9, wherein the gate drive signal for each of the first and second electronic switches is separated by a minimum dead time required for soft-switching.

13. The method as claimed in claim 11, further comprising the steps of:
producing, by the controller, the square wave gate drive signals for the first and second electronic switches,
with a leading phase when a voltage of a power source is greater than a high threshold voltage,
with a lagging phase when the voltage of the power source is lower than a low threshold voltage, and
no gate drive signals for the first and second controllable electronic switches when the voltage of the power source is lower than the high threshold voltage and higher than the low threshold voltage.

14. The method as claimed in claim 9, further comprising the steps of:
measuring equalization time for each of the plurality of power sources, wherein the equalization time is total time of charging and discharging of a power source;
calculating equalization ratio of the power source by using the equalization time of the power source and an average equalization time of the plurality of power sources;
comparing the equalization ratio of the power source with a predefined threshold value; and
determining state of the power source based on the comparison.

15. The method as claimed in claim 14, wherein the state of the power source is considered to be,
damaged when the equalization ratio of the power source is greater than the predefined threshold value, and
normal when the equalization ratio of the power source is lesser than or equal to the predefined threshold value.

16. A voltage equalizer circuit for equalizing voltages of a plurality of power sources connected in series and a method thereof as herein substantiated in the description along with accompanied drawings.
Dated this 22nd Day of July, 2019

Madhusudan S T
IN/PA-1297
Of K & S Partners
Agent for the Applicant