DESC:PLEASE SEE THE ATTACHMENTS. ,CLAIMS:1. A p-type Gallium Nitride (p-GaN) based enhancement mode Field Effect Transistor
(FET) (901), the p-GaN FET (901) comprising:
a Tantalum Nitride (TaN) gate contact (205);
a multi-layered gate stack comprising a plurality of layers (103) of gate metals; and
a p-type doped layer (207) below the TaN gate contact (205) to provide zero charge
below the gate contact (205) of the p-GaN FET (901), wherein the p-type doped layer (207)
is the topmost layer of an epitaxial wafer stack (101) and the TaN gate contact (205) is stacked
on the p-type doped layer (207).
2. The p-GaN FET (901) as claimed in claim 1, wherein the TaN gate contact (205) is
stacked as at least one of:
a topmost layer of the multi-layered gate stack; or
a bottommost layer of the multi-layered gate stack; or
both as the topmost layer and the bottommost layer of the multi-layered gate stack.
3. The p-GaN FET (901) as claimed in claim 1, wherein the TaN gate contact (205) is
stacked on the p-type doped layer (207) using at least one of a reactive ion sputtering technique,
a magnetron sputtering technique or an e-beam evaporation technique.
4. The p-Gan FET (901) as claimed in claim 1, wherein a stoichiometry of the TaN gate
contact (205) is in a range of 45%-55% of Tantalum (Ta) and 55%-45% of Nitride (N), and
wherein a thickness of the TaN gate contact (205) ranges from 100nm to 1000nm.
5. The p-GaN FET (901) as claimed in claim 1, wherein the p-type doped layer (207)
comprises at least one of p-type doped Gallium Nitride (p-GaN), p-type doped Aluminium
Gallium Nitride (AlGaN), a p-type doped Indium Gallium Nitride (InGaN), a p-type doped
Indium Aluminium Nitride (InAlN), a p-type doped Indium Aluminium Gallium Nitride
(InAlGaN).
6. The p-GaN FET (901) as claimed in claim 1, further comprising a passivation layer
(903) configured to protect the p-GaN FET from air or moisture or to passivate surface states,
wherein a thickness of the passivation layer (903) ranges from 100nm to 500nm.
7. A method (1100) of fabricating a p-type Gallium Nitride (p-GaN) based enhancement
mode Field Effect Transistor (FET) (901), the method (1000) comprising:
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forming (1102) a multi-layered gate stack comprising a plurality of layers (103) of gate
metals;
performing (1104) selective etching on a p-type doped layer (207) to form a source
contact (203) and a drain contact (201) of the p-GaN FET (901), wherein the p-type doped
layer (207) is a topmost layer of an epitaxial wafer stack (101);
depositing (1106) a Tantalum Nitride (TaN) gate metal above the p-type doped stack
layer (207) to form a TaN gate contact (205), wherein a lift-off process is performed on the
deposited TaN gate metal to form the TaN gate contact (205); and
performing (1108) a post-metal deposition annealing at a first predefined temperature
in a Nitrogen (N2) atmosphere for a first predefined time period.
performing (1110) a selective removal of the p-type doped layer (207) in access regions
between source region (203) and a gate region (205), and between the gate region (205) and a
drain region (201) using a reactive ion etching, wherein the TaN gate metal serves as a hard
mask while etching.
8. The method (1100) as claimed in claim 7, further comprising:
performing device to device mesa isolation by etching a channel between the source
contact (203), the gate contact (205), and the drain contact (201) using dry etch chemistry to
fabricate the p-GaN FET (901) with the multi-layered gate stack.
9. The method (1100) as claimed in claim 7, wherein performing selective etching on the ptype
doped layer (207) comprises:
performing a rapid thermal annealing at a second predefined temperature for a second
predefined time period in the Nitrogen (N2) atmosphere.
10. The method (1100) as claimed in claim 7, further comprising:
depositing a passivation layer (903) over a top surface of the p-GaN FET (901) to
protect the p-GaN FET (901) from air or moisture or to passivate surface states, wherein the
thickness of the optional passivation layer (903) ranges from 100nm to 500nm.