Description:PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which is to be performed.
A MULTI-PORT CONVERTER SYSTEM AND METHOD FOR CONVERTING ALTERNATING CURRENT (AC) TO DIRECT CURRENT (DC)
CROSS REFERENCE TO RELATED APPLICATION
This application claims priority from Indian patent application No. 202341080811, filed November 28, 2023, the content of which is incorporated herein by reference in its entirety.
FIELD OF INVENTION
The present subject matter generally relates to multi-port converter circuits, more particularly relates to a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC).
BACKGROUND
A conventional electric vehicle (EV) EV battery charger includes a boost-type Power Factor Correction (PFC) circuit for shaping the input current, followed by an isolated DC-DC converter for voltage regulation. Some of the popular topologies commonly used for these chargers, include a conventional boost type PFC or a totem-pole PFC followed by a DC-DC converter such as a Phase-shifted full-bridge, a resonant LLC, or a dual active bridge (DAB) type converter.
Usually, in a boost-type power factor correction (PFC) circuit, a PFC stage is hard-switched, and a DC-DC stage is soft-switched. A semiconductor undergoes soft-switching when the voltage across it is zero during turn ON or current through the switch is zero during turn OFF. Soft switching the PFC stage may open up interesting possibilities. One such possibility may include a DAB based soft-switched single-stage AC-DC converter for battery charging applications. In such converters, a grid voltage is initially folded and then applied to a DAB converter. Further, a wide variation of voltage on the primary (due to folding operation) and secondary (due to battery load) sides may impact a soft switching of the DAB converter. As a result, analysis, design, and practical implementation of such converters become quite complicated.
A current fed type isolated boost PFC multi-port converter is another possibility where the PFC stage is soft switched. In such converters, a diode bridge is typically used on a secondary side of a transformer to rectify high-frequency transformer voltage. When an uncontrolled diode bridge is employed on the secondary side of the transformer, an output voltage becomes tightly coupled to a clamp capacitor voltage through the turn’s ratio of the transformer. This tight coupling of voltages limits the ability of the converter to vary the output voltage over a wide range, consequently restricting the range over which the output power can be varied, which may not be attractive. Although the PFC converter is employed for battery charging, such PFC converter lacks capability to allow the wide variation of voltages at the output stage. The minimum output voltage is constrained to avoid overmodulation of the converter. While this PFC converter provides soft switching and active clamping for improved efficiency, its limited output voltage range restricts its applicability in situations where flexibility in the output voltage is a critical requirement. .
Hence, tan improved multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction and soft switching is proposed to address the aforementioned issues.
SUMMARY
In accordance with an embodiment of the present disclosure, a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) is disclosed. The system may include: a multi-port converter. The multi-port converter includes a primary stage and a plurality of secondary stages.
In accordance with an embodiment, each stage includes a plurality of switches, wherein the multi-port converter is configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC output voltages and powers with a plurality of converter DC ports. The multi-port converter is configured to transfer power between the plurality of converter DC ports and the AC port.
In accordance with an embodiment, the primary stage and each of the plurality of secondary stages is isolated from each other using a high-frequency multi-winding transformer.
In accordance with an embodiment, the system includes a plurality of voltage sensors configured to measure a plurality of voltage levels at a plurality of nodes associated with the multi-port converter.
In accordance with an embodiment, the system includes a plurality of current sensors configured to measure a plurality of current levels through a plurality of circuit elements associated with the multi-port converter.
In accordance with an embodiment, the system includes a controller unit, communicatively coupled to the multi-port converter. The controller unit is configured to receive the measured plurality of voltage levels from the plurality of voltage sensors and the measured plurality of current levels from the plurality of current sensors. Further, the controller unit is configured to determine one or more power flow modes for channelizing the power between an alternating current (AC) port and the plurality of converter DC ports based on at least one of a source, a storage, and a load connected to each of the AC port and the plurality of converter DC ports. Further, the controller unit is configured to generate one or more desired reference voltage levels and a desired reference current levels to allow regulation of a range of DC voltages and currents at the plurality of converter DC ports based on the determined one or more power flow modes. Further, the controller unit is configured to determine one or more control parameters corresponding to the primary stage, and the plurality of secondary stages. The, control parameters comprise at least one of a duty ratio of the primary stage , a duty ratio for each of the plurality of secondary stages, and a control phase shift between a primary voltage associated with the primary stage , and each of the plurality of secondary voltages associated with the plurality of secondary stages , a switching frequency, a dead time of the primary stage , and a dead time of each of the plurality of secondary stages ; In accordance with an embodiment, the controller unit is configured to modulate the determined one or more control parameters corresponding to the primary stage, and the plurality of secondary stages.
In accordance with an embodiment, the controller unit is configured to generate a plurality of control signals for the plurality of switches based on the modulated one or more control parameters.
In accordance with an embodiment, the controller unit is configured to control the plurality of switches in the primary stage and the plurality of secondary stages based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting Power Factor (PF) of the multi-port converter. The switching pattern is configured to enable soft switching of the plurality of switches over most parts of the fundamental line cycle.
In accordance with an embodiment, the system includes a plurality of drive circuits configured to apply the generated plurality of control signals at the plurality of switches based on the modulation scheme and the switching pattern.
In accordance with another embodiment, a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) is disclosed. The method includes receiving, by a controller unit, a plurality of voltage levels and a plurality of current levels measured from a multi-port converter. The multi-port converter includes a primary stage, and a plurality of secondary stages. Each stage comprises a plurality of switches, and the primary stage and each of the plurality of secondary stages is isolated from each other using a high-frequency multi-winding transformer.
In accordance with an embodiment, the method includes determining, by the controller unit, one or more power flow modes for channelizing the power between an alternating current (AC) port and a plurality of converter DC ports based on at least one of a source, a storage, and a load connected to each of the AC port and the plurality of converter DC ports.
In accordance with an embodiment, the method includes generating, by the controller unit, one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a plurality of converter DC ports and transfer power between the plurality of converter DC ports and the AC port based on the determined one or more power flow modes.
In accordance with an embodiment, the method includes determining, by the controller unit, one or more control parameters corresponding to the primary stage, and the plurality of secondary stages. The control parameters comprise at least one of a duty ratio of the primary stage , a duty ratio for each of the plurality of secondary stages, and a control phase shift between a primary voltage associated with the primary stage, and each of the plurality of secondary voltages associated with the plurality of secondary stages , a switching frequency, a dead time of the primary stage, and a dead time of each of the plurality of secondary stages.
In accordance with an embodiment, the method includes modulating, by the controller unit, the determined one or more control parameters corresponding to the primary stage, and the plurality of secondary stages.
In accordance with an embodiment, the method further includes generating, by the controller unit, a plurality of control signals for the plurality of switches based on the modulated one or more control parameters.
In accordance with an embodiment, the method further includes controlling, by the controller unit through the plurality of drive circuits, the plurality of switches in the primary stage and the plurality of secondary stages based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting a Power Factor (PF) of the multi-port converter. The switching pattern is configured to enable soft switching of the plurality of switches over most parts of the fundamental line cycle.
To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.
BRIEF DESCRIPTION OF DRAWINGS
The disclosure will be described and explained with additional specificity and detail with the accompanying figures in which:
FIG. 1 is an exemplary circuit diagram illustrating a current fed multi active bridge type Alternating Current (AC) to Direct Current (DC) boost power factor correction (PFC) converter with an active clamp and a plurality of secondary full bridge configuration, in accordance with an embodiment of the present disclosure;
FIG. 2A is an exemplary graphical representation depicting a clamp capacitor voltage, a grid voltage, and grid current waveforms, in accordance with an embodiment of the present disclosure;
FIG. 2B is another exemplary graphical representation depicting output voltages and output currents at multiple DC ports in accordance with another embodiment of the present disclosure;
FIG. 2C is another exemplary graphical representation depicting high-frequency AC port voltages and AC port currents, in accordance with an embodiment of the present disclosure;
FIG. 3 is a block diagram illustrating an exemplary controller unit, in accordance with an embodiment of the present disclosure;
FIG. 4A is a block diagram illustrating a multi-port converter system configured to allow power transfer from the AC port to each of the DC ports when each of the DC ports is connected to a DC load, in accordance with an embodiment of the present disclosure;
FIG. 4B is a block diagram illustrating a multi-port converter system configured to allow power transfer from the plurality of DC ports to the AC port, when each of the DC ports is connected to a DC source, in accordance with an embodiment of the present disclosure;
FIG. 4C is a block diagram illustrating a multi-port converter system configured to allow power transfer from AC port and DC port 2 to DC port 1, when DC port 2 is connected to a DC source and DC port 1 is connected to a DC load, in accordance with an embodiment of the present disclosure;
FIG. 4D is a block diagram illustrating a multi-port converter system configured to allow power transfer from DC port 1 to AC port and DC port 2, when DC port 1 is connected to a DC source and DC port 2 is connected to a DC load, in accordance with an embodiment of the present disclosure;
FIG. 4E is a block diagram illustrating a multi-port converter system configured to allow power transfer from AC port and DC port 1 to DC port 2, when DC port 1 is connected to a DC source and DC port 2 is connected to a DC load, in accordance with an embodiment of the present disclosure;
FIG. 4F is a block diagram illustrating a multi-port converter system configured to allow power transfer from DC port 2 to AC port and DC port 1, when DC port 2 is connected to a DC source and DC port 1 is connected to a DC load, in accordance with an embodiment of the present disclosure;
FIG. 5 is an exemplary overall architecture diagram depicting a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC), in accordance with an embodiment of the present disclosure; and
FIG. 6 is a flow diagram illustrating a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC), in accordance with embodiment of the present disclosure.
Further, those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and may not have necessarily been drawn to scale. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the figures by conventional symbols, and the figures may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the figures with details that will be readily apparent to those skilled in the art having the benefit of the description herein.

DETAILED DESCRIPTION OF THE DISCLOSURE
For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe them. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as would normally occur to those skilled in the art are to be construed as being within the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof.
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The terms "comprise", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that one or more devices or sub-systems or elements or structures or components preceded by "comprises... a" does not, without more constraints, preclude the existence of other devices, sub-systems, additional sub-modules. Appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but not necessarily do, all refer to the same embodiment.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The system, methods, and examples provided herein are only illustrative and not intended to be limiting.
Accordingly, the term “module” or “subsystem” should be understood to encompass a tangible entity, be that an entity that is physically constructed permanently configured (hardwired) or temporarily configured (programmed) to operate in a certain manner and/or to perform certain operations described herein.
Embodiments of the present disclosure provides a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction. The multi-port converter system provides a wide output range at the DC ports and AC-DC power factor correction (PFC) is achieved in a single stage. All the power semiconductors in the topology may undergo soft switching over most parts of the fundamental line cycle. The present invention may interface multiple DC ports (sources, storage, and load) /with the AC grid using a multi-winding transformer.
Referring now to the drawings, and more particularly to FIG. 1 through FIG. 6, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments, and these embodiments are described in the context of the following exemplary system and/or method.
FIG. 1 is an exemplary circuit diagram illustrating a current-fed multi active bridge type alternating current (AC)-direct current (DC) boost power factor correction (PFC) converter 100 with an active clamp and a secondary full bridge configuration, in accordance with an embodiment of the present disclosure. According to FIG. 1, a current-fed multi active bridge type alternating current-direct current AC-DC boost power factor correction (PFC) converter 100 (also referred herein as multi-port converter 100) is disclosed. In an exemplary embodiment, the multi-port converter 100 may include a primary stage 104a and a plurality of secondary stages 104b-n. The primary stage 104a may be configured to correct a power factor (PF) in the secondary full bridge configuration. The multi-port converter 100 may be configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC output voltages and powers. The primary stage 104a and each of the plurality of secondary stages 104b-n may be galvanically isolated from each other In an exemplary embodiment, the primary stage 104a may include a line-frequency H-bridge 102, a clamp circuit 116, and a high-frequency-H-bridge 103. In an embodiment, the line-frequency H-bridge 102 may include a first set of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d which may be electrically interfaced with an AC supply voltage vg. The first set of switches Sa 106a, Sb 106b, Sc 106c, and Sd 106d may be configured to operate in a range of line frequencies for synchronous rectification to limit conduction losses. The range of line frequency may include, but not limited to, a frequency range between 45–65 Hz (up to 1 kHz).
Further, the primary stage 104a may include a primary inductor 114 connected in series between the first set of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d (hereinafter referred to as the first switches S 106) and a clamp circuit 116. The first switches S 106 may be configured to enable bidirectional power flow by selecting polarity of load current, io through a closed loop control strategy. The closed loop control strategy may include a closed loop controller (not shown in FIG. 1) that determines and manages the direction of power flow in the circuit. This strategy may include feedback and control mechanisms to make real-time decisions about the polarity of the load current (i.e., the direction in which current flows through the load/source). For power flow from a load side to grid side, high-frequency voltages from secondary stages 104b-n may lead the voltage associated with the primary stage. Consequently, a polarity of a control phase shift angle may be adjusted shown in FIG. 3. The closed loop controller may be configured to generate the phase shift angle. The phase shift angle may include an angular measurement that quantifies the time delay or phase difference between two waveforms. The phase shift angle may be typically measured in degrees or radians and indicate how much one waveform lags or leads the other in time. The clamp circuit 116 may include a controlled auxiliary switch Saux 112 connected in series with a clamp capacitor 113. The clamp circuit 116 is electrically connected across a high-frequency H-bridge 103, and the clamp circuit 116 is configured to clamp a voltage across each of a second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d (hereinafter referred to as the second switches S 108) within the high-frequency H-bridge 103 of the primary stage 104a. In an exemplary embodiment, the high-frequency H-bridge 103 may include the second set of controlled switches S 108 electrically connected across the clamp circuit 116. The second switches S 108 may be configured to operate in a range of frequency higher than the range of line frequency (for example 10 kHz – 1 MHz). The second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a are modulated in synchronization with the controlled auxiliary switch Saux 112 for power factor correction (PFC).
The multi-port converter 100 may include a high-frequency multi-winding transformer 120 electrically coupled to the primary stage 104a and the plurality of secondary stages 104b-n through a plurality of optional inductors 126a-n and plurality of optional capacitors 128a-n. The high-frequency multi-winding transformer 120 may be configured to provide a galvanic isolation. The plurality of secondary stages 104b-n may include a third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, (hereinafter referred to as the third switches S 110) and capacitors 122,122a-n electrically interfaced with each secondary winding of the high-frequency multi-winding transformer 120 through a plurality of optional inductors 126a-n and plurality of optional capacitors 128a-n. The switches S 106, S 108, Saux 112, S 110, may include, but not limited to, silicon metal-oxide-semiconductor field-effect transistor (Si MOSFET), Silicon based insulated-gate bipolar transistor (Si IGBT), silicon carbide (SiC) MOSFET, gallium nitride (GaN) high-electron-mobility transistor (HEMT), and the like.
The third switches S 110 may be configured to control an output current or a DC output voltage. The voltage of the clamp capacitor 113 may be maintained above a threshold level, and a current waveform of the primary inductor 114 may be modulated to track a desired pattern for correcting the power factor. The threshold level of the clamp capacitor voltage 113 is higher than the peak value of the grid voltage, vg. The threshold level may be higher than, but not limited to, 1.414 times the rms value of the grid voltage. The rms value of the grid voltage may vary from 85V-265V for universal applications. For modulating the current waveform of the primary inductor 114, the primary stage 104a may be configured to switch the second switches S108 in synchronization with the controlled auxiliary switch Saux 112 using a modulation technique. The modulation technique may include, but not limited to, a pulse width modulation technique, and the like. The pulse width modulation technique may include applying a plurality of voltage vectors across the primary inductor 114. The voltage vectors may include combinations or patterns of voltage applied across the primary inductor 114. The primary stage 104a may be configured to modify a time interval associated with the plurality of voltage vectors. The time interval of the voltage vectors may refer to the voltage duration or timing of voltage patterns applied across the primary inductor 114. The time interval of the voltage vectors may be varied sinusoidally over afundamental cycle (for instance 20 millisecond period for a 50 Hz AC application) to obtain a rectified sinusoid waveform. The primary stage 104a may be configured to modulate the current waveform of the primary inductor 114 to track the desired pattern (such as for example, a sine wave pattern) based on the modified time interval and vary a pulse width of the primary voltage v00’ associated with the primary stage 104a. A converter input port 118 may be configured to actively manipulate grid current values, ig, so that the grid current values ig closely resemble a sinusoidal waveform and are phase-aligned with the grid voltage, vg.
In an embodiment, the first switches S 106 are operated at line frequency for synchronous rectification to limit conduction losses. Furthermore, the first switches S 106 may enable bidirectional power transfer. Alternatively, an input diode bridge may be used for low-cost and low-power applications with unidirectional power flow requirements. The second switches S108, are modulated in synchronization with the auxiliary switch, Saux 112 for PFC operation. The pulse width of the primary voltage v00’ is governed by the duty ratio, which varies sinusoidally for PFC operation. The primary-side control system regulates the clamp capacitor voltage, vclamp, and shapes the inductor current, iL, into a rectified sinusoidal waveform. The plurality of secondary bridges 104b-n may be modulated to generate a square-type or quasi-square-type voltage waveform at the secondary AC ports (11’ and 22’). The representative operating waveforms are given in FIG.2.
The clamp circuit 116 may be configured to create a pathway for the current in the primary inductor 114 when one of the second switches S 108 in the high-frequency H-bridge 103 are turning OFF. The clamping operation is essential for clamping the voltage across each of the second switches S 108 within the high-frequency H-bridge 103 of the primary stage 104a. The controlled auxiliary switch Saux 112 and the second switches S 108 in the primary stage 104a may be configured to allow voltage states to be controllably applied across nodes 0-0’ of the high-frequency H-bridge 103. The voltage states may include, but not limited to, a positive voltage, a negative voltage, and a zero voltage.
In an embodiment of the present disclosure, a secondary side diode bridge (not shown) may be replaced with the third switches S 110. The third switches S 110 may be configured to apply voltages across the nodes 1-1’, 2-2’…n-n’ secondary stages 104b-n in a precisely controlled manner. The voltage states may include, but not limited to, a positive voltage, a negative voltage, and a zero voltage. When an uncontrolled diode bridge (not shown) is used on each of the secondary sides, output voltages (vo1 -von) are tightly linked to the clamp capacitor voltage (vclamp) through a transformer turns ratio (n:1) of the high-frequency transformer 120. This linkage imposes a lower limit on both vclamp and (vo1 -von) to prevent overmodulation. However, through the incorporation of the third switches S 110 on the secondary stages 104b-n, the output voltage (vo1 -von) may be decoupled from the clamp capacitor voltage (vclamp). This decoupling enables a broad spectrum of adjustments in the output voltage (vo1 -von) for a specific power level, and, inversely, extensive modulation of the output power for a given output voltage (vo1 -von). This level of flexibility in voltage and power control may be unattainable when employing the secondary diode bridge (not shown).
In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a and the third switches S 110 of the plurality of secondary stages 104b-n may be configured to operate in a soft switching mode over most parts of the fundamental line cycle. Each of controlled auxiliary switch Saux 112, the second switches S 108 and the third switches S 110 may be configured to be softly activated using a switching pattern.
The multi-port converter 100 may include inductors 114, 126a-c such as a primary inductor L 114, optional inductors L0,L1…Ln 126a-n and optional DC blocking capacitors Cd0,Cd1…Cdn128a-n.. When any of the switching patterns listed in Table.1 is employed, it may result in an interruption in the current flow through at least one of these inductors 114, 126a in the primary stage. This interruption may result in a voltage overshoot occurring across the second switches S 108, due to rate of change of current, expressed as Ldi/dt. The controlled auxiliary switch Saux 112 may be positioned in a specific orientation to ensure a pathway for a flow of inductor current within the converter 100. For example, if a power MOSFET is used to realize Saux 112, a source terminal of 112 may be connected to the inductor 114, and a drain terminal may be connected to the clamp capacitor 113. Hence, the controlled auxiliary switch Saux 112 and the clamp capacitor 113, serve as the active clamp circuit 116. The positions of the auxiliary switch Saux 112 and the clamp capacitor 113 may be interchanged to realize the clamp circuit 116 without compromising its functionality. The controlled auxiliary switch Saux 112 and the clamp capacitor 113, clamps the voltage across the second switches S 108 to vclamp during turn OFF (prohibiting voltage overshoots). The controlled auxiliary switch Saux 112 may be not employed on the plurality of secondary stages 104b-n since the plurality of secondary stages 104b-n are voltage fed, which prevents any voltage overshoots across the third switches S110.
In an exemplary embodiment, the switches auxiliary switch Saux 112, S 108, S 110 may be configured to be softly activated when the voltage across the auxiliary switch Saux 112, switches S 108, S 110 is zero while they are gated ON. The current may be directed through a body diode of the respective switch Saux 112 or first switches S108 or second switches S110under consideration by appropriately modulating the remaining switches. For modulation technique, the below table lists the combination of switches and voltage generated for primary side switches:
Table 1. Modulation techniques and switching patterns for the primary side switches
Modulation scheme 1
Saux S1 S2 S3 S4 v00’ vL
ON ON OFF OFF ON vclamp (+ve) |vg|-vclamp
ON OFF ON ON OFF -vclamp (-ve) |vg|-vclamp
OFF ON ON ON ON zero |vg|
Modulation scheme 2
Saux S1 S2 S3 S4 v00’ vL
ON ON OFF OFF ON vclamp (+ve) |vg|-vclamp
ON OFF ON ON OFF -vclamp (-ve) |vg|-vclamp
OFF ON ON OFF OFF Zero |vg|
OFF OFF OFF ON ON zero |vg|

TABLE. 1
For modulation technique, the below table, Table. 2 and Table. 3 lists the combination of switches and voltage generated for secondary side switches shown in FIG. 1:
Table 2. Modulation technique for secondary side bridge 1
S5 S6 S7 S8 v11’
ON OFF OFF ON vo1
ON OFF ON OFF Zero
OFF ON OFF ON Zero
OFF ON ON OFF -vo1
TABLE. 2

Table 3. Modulation technique for secondary side bridge 2
S9 S10 S11 S12 v22’
ON OFF OFF ON vo2
ON OFF ON OFF Zero
OFF ON OFF ON Zero
OFF ON ON OFF -vo2
TABLE. 3
The controlled auxiliary switch Saux 112, the second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a and the third switches S 110 of the plurality of secondary stages 104b-n may be configured to operate in a soft switching mode over most parts of the fundamental line cycle. Each of controlled auxiliary switch Saux 112, the second switches S 108 and the third switches S 110 may be configured to be activated using the switching pattern as shown in Table. 1, 2 and 3.
FIG. 2A is another exemplary graphical representation 200a depicting a clamp capacitor voltage, a grid voltage and grid current waveforms, in accordance with an embodiment of the present disclosure. The waveforms 200a include a grid voltage waveform 210a, a grid current waveform 210b, and a clamp capacitor voltage waveform 210c. In this representation, the voltage values across the clamp capacitor, vclamp (for example, the clamp capacitor 113), may be carefully regulated to maintain a average voltage 400 V. Additionally, the grid current values, ig, may be actively manipulated to assume the grid current waveform 210b that closely resembles a sinusoidal waveform, and it is phase-aligned with the grid voltage, vg shown in the grid voltage waveform 210a. This phase alignment helps correct the power factor of the multi-port PFC converter 100.
FIG. 2B is another exemplary graphical representation 200b depicting output voltages and output currents at multiple DC ports, in accordance with an embodiment of the present disclosure. The output voltages and output current waveforms 200b may include, output voltage waveforms 212a and 212c and output current waveforms 212b and 212d. Within this visual depiction, the output voltage waveforms 212a and 212c may include an output voltage values, vo1-von, the output current waveforms 212b and 212d may include output current values io1-ion..
FIG. 2C is another exemplary graphical representation 200c depicting AC port voltages and AC port currents, in accordance with an embodiment of the present disclosure. The voltage and current waveforms 200c include primary voltage waveforms 214a, and primary current waveforms 214b. The AC port voltages may include v00’,v11’,v22’ and so on. The AC port currents may include i0,i1,i2 and the like. The voltage and current waveforms 214a, 214b may include the high frequency switching waveforms of the voltages and currents.
FIG. 3 is a block diagram illustrating an exemplary controller unit 300, in accordance with an embodiment of the present disclosure. The controller unit 300 may be communicatively coupled to the multi-port converter 100 shown in FIG. 5. The controller unit 300 may include voltage and current control loops 301, an optimization module 302, a pulse width modulator 304 hosted on a micro-controller unit MCU. The voltage and current control loops 301 may include a second order generalized-integrator (SOGI) filter 306, a voltage controller 308, a current controller 310, DC port voltage controllers 312a-b, and DC port current controllers 314a-b. The SOGI filter 306, the voltage controller 308, the current controller 310, the DC port voltage controller 312a-b, and the DC port current controller 314a-b may be configured to determine control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n. The control parameters may include, but not limited to, the control parameters comprise at least one of a duty ratio of the primary stage (104a), a duty ratio for each of the plurality of secondary stages (104b-n), and a control phase shift between a primary voltage (v00’) associated with the primary stage (104a), and each of the plurality of secondary voltages (v11’,v22’…vnn’) associated with the plurality of secondary stages (104b-n), a switching frequency, a dead time of the primary stage (104a), and a dead time of each of the plurality of secondary stages (104b-n), and the like. The power flow may be controlled by varying the phase shift between a primary bridge voltage waveform and plurality of secondary bridge voltage waveforms, varying the duty ratio dsec of each of the plurality of secondary bridge voltage waveforms (applicable when using the secondary full bridge), or varying switching frequency of the multi-port converter 100 shown in FIG. 3. The switching frequency fsw may be dynamically varied through the implementation of the optimization module 302. The optimization module 302 may be configured to send commands to the pulse width modulator 304 for generating appropriate switching pulses. The switching frequency fsw may be varied by modifying specific registers within the microcontroller unit (MCU). The pulse width modulator 304 may be configured to generate a carrier waveform. The carrier waveform may be used for pulse width modulation based on a switching pattern.
The optimization module 302 may be configured to modulate determined control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n and generate control signals for switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112. Gate pulses are brief electrical signals or voltage waveforms used to control the switching of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4.., and Saux 112. These pulses determine when these switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4 , and Saux 112 turn ON or OFF. The first set of switches Sa, Sb, Sc, Sd enable synchronous rectification based on grid voltage vg. The optimization module 302 and a switching pattern may be configured to control the switches Saux 112, Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, , in the primary stage 104a and the plurality of secondary stages 104b-n respectively based on the generated control signals for correcting Power Factor (PF) of the multiport converter 100. The controller unit 300 may be configured to generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a multiport converter output port.
FIG. 4A is a block diagram illustrating a multi-port converter system configured to allow active power transfer from the AC port to each of the DC ports when each of the DC ports is connected to a DC load, in accordance with an embodiment of the present disclosure. The power flow may be controlled by independently or simultaneously varying the phase shifts f1 and f2 between bridge voltage waveforms, v00’, v11’ and v00’, v22’ respectively, the duty ratio of the secondary bridge voltage waveforms, d1, d2 or by varying the switching frequency of the converter as shown in FIG. 3. The power flow is governed by:
P0 = P1+P2……equation (1)
where P0 refers to the active power flow associated with the primary stage 104a;
where P1 and P2 refers to the active power flow associated with the secondary bridges 1 and 2 respectively.
In an example embodiment, the one or more power flow modes for channelizing the active power between an alternating current (AC) port 118 and the plurality of converter DC ports 124a-n are determined based on at least one of a source, a storage, and a load connected to each of the AC port 118 and the plurality of converter DC ports 124a-n.
FIG. 4B is a block diagram illustrating a multi-port converter system configured to allow active power transfer from the plurality of DC ports to the AC port, when each of the DC ports is connected to a DC source, in accordance with an embodiment of the present disclosure. The power flow may be controlled by independently or simultaneously varying the phase shifts f1 and f2 between bridge voltage waveforms, v00’, v11’ and v00’, v22’ respectively, the duty ratio of the secondary bridge voltage waveforms, d1, d2 or by varying the switching frequency of the converter as shown in FIG. 3. The active power flow is governed by equation (1) as described above.
FIG. 4C is a block diagram illustrating a multi-port converter system configured to allow power transfer from AC port and DC port 2 to DC port 1, when DC port 2 is connected to a DC source and DC port 1 is connected to a DC load, in accordance with an embodiment of the present disclosure. The power flow is governed by:
P1 = P0 + P2……equation (2)
where P0 refers to the active power flow associated with the primary stage 104a.
where P1 and P2 refers to the active power flow associated with the secondary bridge 1 and 2 respectively.
FIG. 4D is a block diagram illustrating a multi-port converter system configured to allow active power transfer from DC port 1 to AC port and DC port 2, when DC port 1 is connected to a DC source and DC port 2 is connected to a DC load, in accordance with an embodiment of the present disclosure. The power flow may be controlled by independently or simultaneously varying the phase shifts f1 and f2 between bridge voltage waveforms, v00’, v11’ and v00’, v22’ respectively, the duty ratio of the secondary bridge voltage waveforms, d1, d2 or by varying the switching frequency of the converter as shown in FIG. 3. The power flow is governed by equation (2) as described above.
FIG. 4E is a block diagram illustrating a multi-port converter system configured to allow active power transfer from AC port and DC port 1 to DC port 2, when DC port 1 is connected to a DC source and DC port 2 is connected to a DC load, in accordance with an embodiment of the present disclosure. The power flow is governed by:
P2 = P0 + P1……equation (3)
where P0 refers to the active power flow associated with the primary stage 104a.
where P1 and P2 refers to the active power flow associated with the secondary bridge 1 and 2 respectively.
FIG. 4F is a block diagram illustrating a multi-port converter system configured to allow active power transfer from DC port 2 to AC port and DC port 1, when DC port 2 is connected to a DC source and DC port 1 is connected to a DC load, in accordance with an embodiment of the present disclosure. The power flow may be controlled by independently or simultaneously varying the phase shifts f1 and f2 between bridge voltage waveforms, v00’, v11’ and v00’, v22’ respectively, the duty ratio of the secondary bridge voltage waveforms, d1, d2 or by varying the switching frequency of the converter as shown in FIG. 3. The active power flow is governed by equation (3) as described above.
In an embodiment, power factor correction involves actively manipulating the current iL, that flows through the primary inductor L 114. This manipulation may be performed to shape the inductor current, iL, into a rectified sinusoidal waveform which is phase-aligned with the rectified grid voltage |vg|. As a result of this clever shaping, the grid current ig, may include the sinusoidal waveform that perfectly synchronizes with the grid voltage, vg. This synchronization of the current and voltage waveforms enables effective correction of the power factor in the single-phase module. FIG. 5 is an overall architecture diagram 500 depicting a multi-port converter system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction, in accordance with an embodiment of the present disclosure. The system 500 may include the converter 100, the controller unit 300, a plurality of voltage sensors 502, a plurality of current sensors 504, analog to digital converters 506, and a gate drive circuitry 508. The plurality of voltage sensors 502 may be configured to measure a plurality of voltage levels at a plurality of nodes associated with the multi-port converter 100. The plurality of current sensors 504 may be configured to measure a plurality of current levels through plurality of circuit elements associated with the multi-port converter 100. The controller unit 300 may be communicatively coupled to the multi-port converter 100. The controller unit 300 may be configured to receive the measured plurality of voltage levels from the plurality of voltage sensors 502 and the measured plurality of current levels from the plurality of current sensors 504. The controller unit 300 may be configured to generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a multi-port converter output port. The controller unit 300 may be configured to determine one or more control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n.
The control parameters may include, but not limited to, at least one of a duty ratio of the primary stage (104a), a duty ratio for each of the plurality of secondary stages (104b-n), and a control phase shift between a primary voltage (v00’) associated with the primary stage (104a), and each of the plurality of secondary voltages (v11’,v22’…vnn’) associated with the plurality of secondary stages (104b-n), a switching frequency, a dead time of the primary stage (104a), and a dead time of each of the plurality of secondary stages (104b-n) and the like. The controller unit 300 may be configured to modulate the determined one or more control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n. The controller unit 300 may be configured to generate a plurality of control signals for the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112 based on the modulated one or more control parameters. The controller unit 300 may be configured to control the plurality of switches in the primary stage 104a and the plurality of secondary stages 104b-n based on the generated plurality of control signals, by using a modulation scheme and the switching pattern, for correcting Power Factor (PF) of the multi-port converter 100, the switching pattern is configured to enable soft switching of the plurality of switches S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112, over most parts of the fundamental line cycle Finally, the plurality of drive circuits (gate drive circuitry) 508 may be configured to apply the generated plurality of control signals at the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112 based on the modulation scheme and the switching pattern.
According to exemplary embodiment of the present disclosure, various voltage ranges are available based on the specific application requirements. In an embodiment of the present disclosure, a first option may include voltage ranges between 40 to 120 V and is suitable for charging electric two-wheelers and three-wheelers. These types of vehicles typically have lower voltage battery systems. In another embodiment of the present disclosure, a second option may include voltage range is set between 250 to 500 V. This range is ideal for charging four-wheelers, particularly those equipped with a 400 V nominal battery pack. Many modern electric cars may fall within this category. In another embodiment of the present disclosure, a third option may include the voltage range expands to 600 to 1000 V, catering to four-wheelers with a higher 800 V nominal battery pack. Electric vehicles with higher voltage systems, such as some luxury and performance cars, fall into this category. These options may represent distinct voltage ranges tailored to meet the charging needs of different types of electric vehicles. The choice of option depends on the specific application and the voltage characteristics of the electric vehicle battery.
FIG. 6 is a flow diagram 600 illustrating an exemplary method for converting Alternating Current (AC) to Direct Current (DC) is disclosed, in accordance with embodiment of the present disclosure. At step 602, a plurality of voltage levels and a plurality of current levels measured from a multi-port converter 100 are received by a controller unit 300. In an embodiment of the present disclosure, the multi-port converter 100 may include a primary stage 104a and a plurality of secondary stages 104b-n. Each stage may include a plurality of switches, and the primary stage 104a anc each of the pluralilty of secondary stages 104b-n is galvanically isolated from each other using a high-frequency multi-winding transformer 120.
At step 604, one or more power flow modes are determined by the controller unit 300 for channelizing the power between an alternating current (AC) port and a plurality of converter DC ports 124a-n based on at least one of a source, a storage, and a load connected to each of the AC port and the plurality of converter DC ports 124a-n.
At step 606, one of a desired reference voltage level and a desired reference current level is generated by the controller unit 300 to allow regulation of a range of DC output voltages and currents at plurality of converter DC ports 124a-n and transfer power between the plurality of converter DC ports 124a-n and the AC port 118 based on the determined one or more power flow modes.
At step 608, one or more control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n is determined via the controller unit 300. In an embodiment of the present disclosure, the one or more control parameters include at least one of a duty ratio of the primary stage 104a, a duty ratio of each of the plurality of secondary stages 104b-n, and a control phase shift between a primary voltage v00’ associated with the primary stage 104a, and each of the plurality of secondary voltages v11’,v22’…vnn’ associated with the plurality of secondary stages 104b-n, a switching frequency, a dead time of the primary stage 104a, and a dead time of each of the plurality of secondary stages 104b-n. In an embodiment of the present disclosure, in determining the one or more control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n, the method 600 may include measuring an AC supply voltage, a clamp capacitor voltage, and an inductor current corresponding to the primary stage 104a and one or more DC output voltages, and one or more DC output currents corresponding to the plurality of secondary stages 104b-n. The method 600 further includes generating a voltage set point for the clamp capacitor voltage and a reference current pattern as a function of the AC supply voltage. The method 600 further includes generating a voltage or current setpoint for the DC voltage or the DC current at each of the plurality of converter DC ports 124a-n, and determining a duty ratio of the primary stage dpri 104a, a duty ratio of the plurality of secondary stages dsec 104b-n, a phase shift between the primary voltage v00’associated with the primary stage 104a, and each of plurality of the secondary voltages v11’,v22’…vnn’ associated with the plurality of secondary stages 104b-n, a switching frequency, a dead time of the primary stage 104a, and a dead time of each of the plurality of secondary stages 104b-n.
According to an exemplary embodiment of the present disclosure, a clamp capacitor voltage of a clamp capacitor 113 is maintained above a threshold level. A current waveform of a primary inductor 114 is modulated to track a desired pattern for correcting a power factor. In an embodiment of the present disclosure, a second switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a are switched in synchronization with a controlled auxiliary switch Saux 112 to apply a plurality of voltage vectors across the primary inductor 114. In an embodiment of the present disclosure, a time interval associated with the plurality of voltage vectors is modified and an induction current waveform is modulated to track the desired pattern based on the modified time interval.
At step 610, determined one or more control parameters corresponding to the primary stage 104a, and the plurality of secondary stages 104b-n are modulated by the controlled unit 300.
At step 612, a plurality of control signals are generated by the controller unit 300 for the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4,Saux 112 based on the modulated one or more control parameters.
At step 614, the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4,Saux 112 in the primary stage 104a and the plurality of secondary stages 104b-n are controlled by the controller unit 300 through the plurality of drive circuits 508 based on generated plurality of control signals. In an embodiment of the present disclosure, the plurality of switches S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112).are controlled by using a modulation scheme and a switching pattern, for correcting a power factor (PF) of the multi-port converter 100.
The switching pattern is configured to enable soft switching of the plurality of switches S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112 over most parts of the fundamental line cycle. The modulation scheme and the switching pattern are determined for the multi-port converter 100. The second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 in the primary stage 104a are modulated in synchronization with the controlled auxiliary switch Saux 112 for power factor correction. The voltage across each of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d within the high-frequency H-bridge 103 of the primary stage 104a is clamped by the clamp circuit 116. The third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, are modulated in the plurality of secondary stages 104b-n based on the determined modulation scheme and the switching pattern, for regulating a range of DC output voltage and currents. In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4,of the plurality of secondary stages 104b-n are modulated to allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across the nodes 0-0’ of the high-frequency H-bridge 103 and the plurality of nodes 1-1’, 2-2’ … n-n’ of the secondary stages 104b-n. The high-frequency multi-winding transformer 120 is configured to provide galvanic isolation between the primary stage 104a and each of the plurality of secondary stages 104b-n.
In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a, and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4 of the plurality of secondary stages 104b-n are operated in a soft switching mode over most parts of the fundamental line cycle. Each of the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4 are configured to be activated using the switching pattern. In an embodiment of the present disclosure, clamping the voltage across each of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d within the high-frequency H-bridge 103 of the primary stage 104a may include, creating a path for the inductor current when at least one of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d in the high-frequency H-bridge 103 of the primary stage 104a are turning OFF.
In an exemplary embodiment, the method 600 may further include maintaining a clamp capacitor voltage of the clamp capacitor 113 above a threshold level and modulating a current waveform of a primary inductor 114 to track a desired pattern for correcting the PF, switching the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a in synchronization with the controlled auxiliary switch Saux 112 to apply a plurality of voltage vectors across the primary inductor 114; modifying a time interval associated with the plurality of voltage vectors; and modulating the inductor current waveform to track the desired pattern based on the modified time interval.
Various embodiments of the system 100 and method for converting Alternating Current (AC) to multiport Direct Current (DC) as described above provides effective power factor correction, enhancing the efficiency of AC to DC conversion. The system 100 allows regulation of a wide range of DC output voltages and powers, making it adaptable for various applications. The system 100 employs a high-frequency multi-winding transformer 120 to obtain galvanic isolation between a primary stage 104a and each of the plurality of secondary stages 104b-n, enhancing safety and performance. Voltage and current sensors 502, 504, coupled with a controller unit 300, enable precise monitoring and control of the conversion process. Further, the system 100 determines control parameters for both primary 104a and plurality of secondary stages 104b-n, including duty ratios, phase shift, switching frequency, and dead times, to optimize performance. A modulation scheme and switching pattern is employed to enable soft switching of the switches over most parts of the fundamental line cycle, reducing switching losses and improving efficiency. Furthermore, the system 100 modulates voltage vectors across the inductor 114, to modulate the current through inductor 114 to track a desired pattern for power factor correction, ensuring an efficient conversion process. The system 100 is suitable for single-phase multi-phase module configurations, making it adaptable for different electrical systems. A clamp circuit 116 helps prevent voltage overshoots across the switches S 108. In addition, auxiliary switch Saux 112, S108 and S 110 allow control over positive, negative and zero voltage applied across nodes 0-0’ of primary H-bridge 103 and nodes 1-1’, 2-2’ … n-n’ of the secondary stages 104b-n. The system 100 utilizes soft-switching schemes to reduce switching losses and enhance system efficiency.
The embodiments herein can comprise hardware and software elements. The embodiments that are implemented in software include but are not limited to, firmware, resident software, microcode, etc. The functions performed by various modules described herein may be implemented in other modules or combinations of other modules. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments. Also, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open-ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise.
Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the embodiments of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
, Claims:WE CLAIM:
1. A system for converting Alternating Current (AC) to Direct Current (DC) using a multi-port converter, the system comprising:
a multi-port converter (100), comprising a primary stage (104a) and a plurality of secondary stages (104b-n), wherein each stage (104a, 104b-n) comprises a plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112), wherein the multi-port converter (100), with an AC port and multiple DC ports, is configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC voltages and powers at a plurality of converter DC ports(124a-n), and wherein the multi-port converter (100) is configured to transfer power between the plurality of converter DC ports (124a-n) and the AC port (118) and wherein the primary stage (104a) and each of the plurality of secondary stages (104b-n) is galvanically isolated from each other using a high-frequency multi-winding transformer (120);
a plurality of voltage sensors (502) configured to measure a plurality of voltage levels at a plurality of nodes associated with the multi-port converter (100);
a plurality of current sensors (504) configured to measure a plurality of current levels through plurality of circuit elements associated with the multi-port converter (100); and
a controller unit (300), communicatively and electrically coupled to the multi-port converter (100), wherein the controller unit is (300) configured to:
receive the measured plurality of voltage levels from the plurality of voltage sensors (502) and the measured plurality of current levels from the plurality of current sensors (504);
determine one or more power flow modes for channelizing the power between an alternating current (AC) port (118) and the plurality of converter DC ports (124a-n) based on at least one of a source, a storage, and a load connected to each of the AC port (118) and the plurality of converter DC ports (124a-n);
generate one or more desired reference voltage levels and a desired reference current levels to allow regulation of a range of DC voltages and currents at the plurality of converter DC ports (124a-n) based on the determined one or more power flow modes;
determine one or more control parameters corresponding to the primary stage (104a), and the plurality of secondary stages (104b-n), wherein the control parameters comprise at least one of a duty ratio of the primary stage (104a), a duty ratio for each of the plurality of secondary stages (104b-n), and a control phase shift between a primary voltage (v00’) associated with the primary stage (104a), and each of the plurality of secondary voltages (v11’,v22’…vnn’) associated with the plurality of secondary stages (104b-n), a switching frequency, a dead time of the primary stage (104a), and a dead time of each of the plurality of secondary stages (104b-n);
modulate the determined one or more control parameters corresponding to the primary stage (104a), and the plurality of secondary stages (104b-n);
generate a plurality of control signals for the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112), based on the modulated one or more control parameters; and
control the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112), in the primary stage (104a) and the plurality of secondary stages (104b-n) based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting Power Factor (PF) of the multi-port converter (100), wherein the switching pattern is configured to enable soft switching of the plurality of switches (S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112) over most parts of the fundamental line cycle; and
a plurality of drive circuits (508) configured to apply the generated plurality of control signals at the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112), based on the modulation scheme and the switching pattern.

2. The system as claimed in claim 1, wherein the multi-port converter (100) comprises:
the primary stage (104a), configured to correct the Power Factor (PF), comprising:
a line-frequency H-bridge (102) comprising:
a first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d), electrically interfaced with an AC supply voltage, wherein the first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d) are configured to operate in a range of line frequency; and
a primary inductor (114) connected in series between the first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d) and a clamp circuit (116);
the clamp circuit (116) comprising:
a controlled auxiliary switch Saux (112) connected in series with a clamp capacitor (113), wherein the clamp circuit (116) is electrically connected across a high-frequency H-bridge (103), and wherein the clamp circuit (116) is configured to clamp a voltage across each of a second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a); and
the high-frequency H-bridge (103) comprising:
the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) electrically connected across the clamp circuit (112), wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) are configured to operate in a range of frequency higher than the range of line frequency;
the high-frequency multi-winding transformer (120) electrically coupled to the primary stage (104a) and the plurality of secondary stages (104b-n), through optional inductors (126a-n) and optional DC blocking capacitors (128a-n) wherein the high-frequency multi-winding transformer (120) is configured to provide galvanic isolation; and
the plurality of secondary stages (104b-n) comprising:
a third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) electrically interfaced with a respective secondary winding of the high-frequency multi-winding transformer (120) through optional inductors (126 b-n) and optional DC blocking capacitors (128b-n), and a plurality of capacitors (122a, 122b … 122n), wherein the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) are configured to control at least one of DC currents and DC voltages, characterized in that, wherein the plurality of secondary stages (104b-n) comprises at least two or more DC ports (124a-n).

3. The system as claimed in claim 2, wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) are modulated in synchronization with the controlled auxiliary switch Saux (112) for the PF correction.

4. The system as claimed in claim 2, wherein the voltage of the clamp capacitor (113) is maintained above a threshold level and wherein the current waveform of the primary inductor (114) is modulated to track a desired pattern for correcting the PF.

5. The system as claimed in claim 4, wherein for modulating the current waveform of the primary inductor (114) to track the desired pattern, the primary stage (104a) is configured to:
switch the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in synchronization with the controlled auxiliary switch Saux (112) using a pulse width modulation technique to apply a plurality of voltage vectors across the primary inductor (114);
modify a time interval associated with the plurality of voltage vectors;
modulate the current waveform of the primary inductor (114) to track the desired pattern based on the modified time interval; and
vary a pulse width of the primary voltage (v00’) associated with the primary stage (104a).

6. The system as claimed in claim 2, wherein for clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a), the clamp circuit (116) is configured to create a path for the current in the primary inductor (114) when at least one of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) in the high-frequency H-bridge (103) are turning OFF.

7. The system as claimed in claim 2, wherein the controlled auxiliary switch Saux (112) and the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across nodes 0-0’ of the high-frequency H-bridge (103).

8. The system as claimed in claim 2, wherein the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) of the plurality of secondary stages (104b-n) allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across the corresponding secondary nodes 1-1', 2-2'…n-n' of the secondary stages (104b-n).

9. The system as claimed in claim 2, wherein the controlled auxiliary switch Saux (112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) of the plurality of secondary stages (104b-n) are configured to operate in a soft switching manner over most parts of the fundamental line cycle, wherein each of controlled auxiliary switch Saux (112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) are configured to be activated using a switching pattern.

10. The system as claimed in claim 2, wherein the range of line frequency is between 20 – 1000 Hz.

11. A method for converting Alternating Current (AC) to Direct Current (DC), the method comprising:
receiving, by a controller unit (300), a plurality of voltage levels and a plurality of current levels measured from a multi-port converter (100), wherein the multi-port converter (100) comprises a primary stage (104a), and a plurality of secondary stages (104b-n), wherein each stage (104a, 104b-n) comprises a plurality of switches, and wherein the primary stage (104a) and each of the plurality of secondary stages (104b-n) is galvanically isolated from each other using a high-frequency multi-winding transformer (120);
determining, by the controller unit (300), one or more power flow modes for channelizing the power between an alternating current (AC) port and a plurality of converter DC ports (124a-n) based on at least one of a source, a storage, and a load connected to each of the AC port and the plurality of converter DC ports (124a-n);
generating, by the controller unit (300), one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC voltages and currents at a plurality of converter DC ports (124a-n) and transfer power between the plurality of converter DC ports (124a-n) and the AC port (118) based on the determined one or more power flow modes;
determining, by the controller unit (300), one or more control parameters corresponding to the primary stage (104a), and the plurality of secondary stages (104b-n), wherein the control parameters comprise at least one of a duty ratio of the primary stage (104a), a duty ratio of each of the plurality of secondary stages (104b-n), and a control phase shift between a primary voltage (v00’) associated with the primary stage (104a), and each of the plurality of secondary voltages (v11’,v22’…vnn’) associated with the plurality of secondary stages (104b-n), a switching frequency, a dead time of the primary stage (104a), and a dead time of each of the plurality of secondary stages (104b-n);
modulating, by the controller unit (300), the determined one or more control parameters corresponding to the primary stage (104a), and the plurality of secondary stages (104b-n);
generating, by the controller unit (300), a plurality of control signals for the plurality of switches based on the modulated one or more control parameters; and
controlling, by the controller unit (300) through the plurality of drive circuits, the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4,Saux 112) in the primary stage (104a) and the plurality of secondary stages (104b-n) based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting a Power Factor (PF) of the multi-port converter (100), wherein the switching pattern is configured to enable soft switching of the plurality of switches (S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4, Saux 112) over most part of the fundamental line cycle.

12. The method as claimed in claim 11, wherein determining the one or more control parameters corresponding to the primary stage (104a), and the plurality of secondary stages (104b-n) comprises:
measuring an AC supply voltage, a clamp capacitor voltage, and an inductor current corresponding to the primary stage (104a) and one or more DC voltages, and one or more DC currents corresponding to the plurality of secondary stages (104b-n);
generating a voltage set point for the clamp capacitor voltage and a reference current pattern as a function of the AC supply voltage;
generating a voltage or current setpoint for the DC voltage or the DC current at each of the plurality of converter DC ports (124a-n); and
determining a duty ratio of the primary stage (104a), a duty ratio of each of the plurality of secondary stages (104b-n), a phase shift between the primary voltage (v00’) associated with the primary stage (104a), and each of the plurality of secondary voltages (v11’,v22’…vnn’) associated with the plurality of secondary stages (104b-n), a switching frequency, a dead time of the primary stage (104a), and a dead time of each of the plurality of secondary stages (104b-n).

13. The method as claimed in claim 11, wherein controlling the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4,Saux 112) in the primary stage (104a) and the plurality of secondary stages (104b-n) with the generated plurality of control signals by using the modulation scheme and the switching pattern for correcting the power factor of the multi-port converter (100) comprises:
determining the modulation scheme and the switching pattern for the multi-port converter (100);
modulating the second set of controlled switches based on the determined modulation scheme and the switching pattern, wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) are modulated in synchronization with the controlled auxiliary switch Saux (112) for power factor correction;
clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a);
modulating the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) in the plurality of secondary stages (104b-n) based on the determined modulation scheme and the switching pattern, for regulating a range of DC voltages and currents;
modulating the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a), and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) of the plurality of secondary stages (104b-n) to allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across nodes 0-0’ of the high-frequency H-bridge (103) and one or more secondary nodes 1-1’, 2-2’ ..n-n’ of the secondary stages (104b-n), wherein the high-frequency multi-winding transformer (120) is configured to provide galvanic isolation between the primary stage (104a) and each of the plurality of secondary stages (104b-n);
operating the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a), and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) of the plurality of secondary stages (104b-n) wherein each of the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d, S9 110e, S10 110f, S11 110g, S12 110h … Sn1 110n1, Sn2 110n2, Sn3 110n3, Sn4 110n4) are configured to be activated using the switching pattern.

14. The method as claimed in claim 13, wherein clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a) comprises:
creating a path for the inductor current when at least one of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) in the high-frequency H-bridge (103) of the primary stage (104a) are turning OFF.

15. The method as claimed in claim 11, further comprising:
maintaining a clamp capacitor voltage of the clamp capacitor (113) above a threshold level and modulating a current waveform of a primary inductor (114) to track a desired pattern for correcting the PF;
switching the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a) in synchronization with the controlled auxiliary switch Saux (112) to apply a plurality of voltage vectors across the primary inductor (114);
modifying a time interval associated with the plurality of voltage vectors; and
modulating the inductor current waveform to track the desired pattern based on the modified time interval.
Dated this 18th day of July 2024

Name: Sanath MV
Prasa IP
Patent Agent (IN/PA-5004) Agent for the Applicant