DESC:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

TITLE OF THE INVENTION
A NARROW C BAND ULTRA-LOW NOISE AMPLIFIER

APPLICANT(S) BHARAT ELECTRONICS LIMITED
OUTER RING ROAD, NAGAVARA, BANGALORE -560045, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

TECHNICAL FIELD
[0001] The present disclosure relates to communication systems. The disclosure, more particularly, relates to techniques for a narrow C-band ultra-low noise amplifier in radio frequency communication.
BACKGROUND
[0002] In general, C-band refers to a range of frequencies used in radio frequency communication. Low noise amplifier is a main component in receiver portion of radar and communication systems. LNAs are used to reduce undesired noise content in the first stage of amplification of the receiver. For high sensitivity of the receiver, LNA must have low noise figure and good gain. Wideband amplifiers are having advantage of wider bandwidth but there is limitation in their performance characteristics of achieving ultra-noise figures. LNA noise will impact Signal-to-Noise ratio of the receiver.
[0003] CN207339798U discloses a C Band Low noise amplifier which incorporates a power supply stabilization circuit and consists of two stages of amplification. The Noise Figure is around 3dB and 20dB gain with in-band flatness of 2dB.The disclosed LNA has been realized using discrete QFNs and power supply stabilization circuit uses additional discrete components. The invention is not a monolithic realization.
[0004] WO 2011011754Al discloses a multi-mode low noise amplifier (LNA) with transformer source degeneration. It incorporates technique of using inductors at source of the NMOS devices in each stage of the LNA to improve linearity. This is mainly intended for use in wireless applications such as Bluetooth, Wi-Fi, and mobile handsets. The technology used is Silicon. The technique of source degeneration used in multi stage amplifiers in Silicon technology may not be suitable for direct application in microwave frequency, long range applications such as RADAR.
[0005] US9641130 discloses Low noise amplifier with noise and linearity improvement. The LNA includes an amplifying transistor and an auxiliary transistor. However, the frequency of operation is 0.5 to 4 GHz and requires two different technologies i.e BJT/HBT as an amplifying transistor and MOSFET/PHEMT as an auxiliary transistor.
[0006] CN104753470A discloses an x band low noise Amplifier & mentions techniques to realize a Low Noise Amplifier using discrete components but does not detail the techniques to achieving the same on single GaAs substrate.
[0007] Therefore, there is a need for an invention which provides a monolithic C-Band Self-biased two stage LNA to achieve the above objective.
OBJECT OF THE INVENTION
[0008] The principal object of the embodiments herein is to provide a system for narrow C-band ultra-low noise amplifier in radio frequency communication.
[0009] Another object of the embodiments herein is to provide a method for narrow C-band ultra-low noise amplifier in radio frequency communication.
SUMMARY OF THE INVETION
[0010] The present invention provides a novel C-band two stage low noise amplifier Monolithic Microwave Integrated Circuit which provides stable gain of 22dB typical and noise figure less than 1dB, is fabricated using InGaAs pseudomorphic high electron mobility transistor(pHEMT) technology with a die size of less than 1.5mm in both x and y directions.
[0011] In one aspect, a narrow C-band ultra-low noise amplifier comprises at least two amplifier stages having an input stage amplifier (102) and an output stage amplifier (104) connected between input (RFIN) & output (RFOUT) RF signal ports through at least three matching networks including an input matching network (101), an intermediate matching network (103) and an output matching network (105); wherein in first amplifier stage, the input matching network (101) connected between the input RF signal and the input stage amplifier (102), the input matching network (101) receives input RF signal and matches 50 Ohm RF impedance of input impedance of input stage amplifier (102); the inter-stage matching network (103) connected between the input stage amplifier (102) and the output stage amplifier (104), the inter-stage matching network (103) matches 50 Ohm RF impedance of output impedance of the first stage amplifier (102) to 50 Ohm RF impedance of input impedance of the output stage amplifier (104); and in the second amplifier stage, the output matching network (105) connected between the output RF signal port (RFOUT) and the output stage amplifier (104), the output matching network (105) matches 50 Ohm RF impedance of output impedance of the second stage amplifier (104) to 50 Ohm RF impedance of the output RF signal port (RFOUT).

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0012] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0013] Figure 1 illustrates block diagram of C-Band GaAs Monolithic Microwave Integrated Circuit (MMIC) low noise amplifier, according to an exemplary implementation of the present invention.
[0014] Figure 2 illustrates design of C-Band GaAs MMIC low noise amplifier, according to an exemplary implementation of the present invention.
[0015] Figure 3 illustrates output graph, according to an exemplary implementation of the present invention shows return losses are 15dB typical at both the input and the output ports over the C Band frequency and gain of 22dB typical.
[0016] Figure 4 illustrates output power 1dB compression (OP1) response of LNA, according to an exemplary implementation of the present invention. It shows the output power at which the amplifier gain compressed by 1dB from its actual values and is +10dBm in C band frequency.
[0017] Figure 5 illustrates measured output IP3dBm (OIP3) of proposed LNA at 3.5V, according to an exemplary implementation of the present invention. For this, two fundamental tones are applied at the input of the amplifier with frequency separation of 10MHz. The OIP3 output is monitored at amplifier output and is 20dB typical in C band frequency.
[0018] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0019] The various embodiments of the present disclosure describe about techniques for allowing authorized access to any computing devices enabled with biometric sensors.
[0020] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0021] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present disclosure and are meant to avoid obscuring of the present disclosure.
[0022] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0023] The GaAs based monolithic microwave integrated circuits are vastly used in Radar & communication systems because of its high yield and reliable performance. Active electronically scanned array (AESA) radar is one such area where low noise amplifiers are used for miniaturizing size as well as improved signal to noise ratio. Transmit/Receive modules are the core component of AESA radars, LNA used in the receiver path plays a key role in receiver signal sensitivity. Hence for a low noise amplifier intended for use in T/R modules it is essential to achieve lower size, weight, power at lower cost. This LNA is specially designed for transmit/receive modules used in Active Electronically Scanned Array (AESA) RADAR.
[0024] In one embodiment, a narrow C-band ultra-low noise amplifier comprises at least two amplifier stages having an input stage amplifier (102) and an output stage amplifier (104) connected between input (RFIN) & output (RFOUT) RF signal ports through at least three matching networks including an input matching network (101), an intermediate matching network (103) and an output matching network (105); wherein in first amplifier stage, the input matching network (101) connected between the input RF signal and the input stage amplifier (102), the input matching network (101) receives input RF signal and matches 50 Ohm RF impedance of input impedance of input stage amplifier (102); the inter-stage matching network (103) connected between the input stage amplifier (102) and the output stage amplifier (104), the inter-stage matching network (103) matches 50 Ohm RF impedance of output impedance of the first stage amplifier (102) to 50 Ohm RF impedance of input impedance of the output stage amplifier (104); and in the second amplifier stage, the output matching network (105) connected between the output RF signal port (RFOUT) and the output stage amplifier (104), the output matching network (105) matches 50 Ohm RF impedance of output impedance of the second stage amplifier (104) to 50 Ohm RF impedance of the output RF signal port (RFOUT).
[0025] In another embodiment, a method for ultra low noise amplification comprising receiving input signal for amplification. The input matching network (101) matches 50 Ohm RF impedance to the input impedance of the FET (102) which matched for better noise figure. The inter-stage matching network (103) after the first amplifier (102) matches the output impedance of the first stage amplifier (102) to the input impedance of the second stage amplifier (104). The second stage amplifier (104) consists of a single FET of 300µm gate periphery. The output impedance of the second stage amplifier (104) is matched to 50 Ohm by the output matching network (105) for better return loss at the output.
[0026] In another embodiment, wherein the first stage amplifier (102) has of a single FET of 300µm gate periphery.
[0027] In another embodiment, wherein the second stage amplifier (104) has of a single FET of 300µm gate periphery.
[0028] In another embodiment, wherein the input matching network (101) comprises a FET (206) and a RC network (201).
[0029] In another embodiment, wherein the inter-stage matching network (103) comprises lumped circuit (202).
[0030] In another embodiment, wherein the output matching network (105) comprises series of capacitors (205) of effective capacitance value less than 0.1pF and resistor circuit (204) wherein the output power of output matching network (105) can be controlled by using the resistor circuit (204).
[0031] In another embodiment, wherein the amplifier (100) is dc blocked internally using the FET (206, 207) and is self-biased by the RC network (201,203).
[0032] In another embodiment, wherein return losses are better than 15dB at both the input and the output ports over the C Band frequency.
[0033] In another embodiment, wherein the amplifier (100) is self-biased circuit with single supply operation can operate from 2V to 4V with low current consumption of 30mA typical at 3V supply.
[0034] In another embodiment, wherein output power compression of the amplifier (100) at 1dB is minimum +10dBm and Output third order intercept point of minimum +20dBm.
[0035] In another embodiment, wherein the amplifier (100) is unconditionally stable up to 40GHz analysed by using Nyquist and stability circle criteria.
[0036] In another embodiment, wherein the output power of amplifier (100) is controlled by changing gate bias of second stage amplifier (104).
[0037] In another embodiment, wherein maximum power handling capability of the amplifier (100) is upto +27dBm.
[0038] In another embodiment, wherein reverse recovery time of the amplifier (100) is less than 110nS.
[0039] In another embodiment, wherein the amplifier (100) is a single chip having a die size less than 1.5mm X 1.5 mm with ultra-low noise figure, high gain and miniature in size operating in continuous wave mode.
[0040] In another embodiment, wherein the amplifier (100) is realized using 0.15 µm GaAs pHEMT (pseudomorphic high electron mobility transistor) process in C-band.
[0041] Wide bandwidth radio frequency amplifiers has limitation on its performance characteristic to meet low noise figures with high gain. The C-Band GaAs MMIC low noise amplifier (100) as disclosed herein is a single chip having a die size less than 1.5mm X 1.5 mm with ultra-low noise figure, high gain and miniature in size operating in continuous wave mode. This LNA (100) is realized using 0.15 µm GaAs pHEMT (pseudomorphic high electron mobility transistor) process in C-band. It is a monolithic, self-biased, single supply, 2 stage low noise amplifier consisting of input matching network (101), first stage amplifier (102), inter-stage matching network (103), second stage amplifier (104) and output matching network (105) . The LNA operates in the C Band with a bandwidth of 500MHz offering a gain of 22dB typical and noise figure of <1dB.
[0042] The block diagram of such computing devices is as shown in Figure 1. The C-Band GaAs MMIC low noise amplifier (100) as disclosed herein is a single chip having a die size of less than 1.5mm in both x and y directions. It is low noise, high gain and miniature in size operated in continuous wave mode realized using 0.15 µm GaAs pHEMT (pseudomorphic high electron mobility transistor) process in C-band. The LNA consists of two amplifier stages viz. input stage amplifier (102) and output stage amplifier (104). The two amplification stages are connected between the input (RFIN) & output (RFOUT) through 3 matching networks namely input matching network (101), intermediate matching network (103) and output matching network (105).
[0043] The input matching network (101) receives input signal for amplification. For better Sensitivity, the LNA designed should have low noise contribution and should be able to receive very low input signals. Hence, stage1 of the amplifier is focussed on noise level reduction in trade off with return loss. The first stage amplifier (102) consists of a single FET of 300µm gate periphery. The input matching network (101) matches 50 Ohm RF impedance to the input impedance of the FET (102) which matched for better noise figure. The inter-stage matching network (103) after the first amplifier (102) matches the output impedance of the first stage amplifier (102) to the input impedance of the second stage amplifier (104). The second stage amplifier (104) consists of a single FET of 300µm gate periphery. The output impedance of the second stage amplifier (104) is matched to 50 Ohm by the output matching network (105) for better return loss at the output.
[0044] Referring to figure 2, The first stage amplifier (102) consists of a single FET of 300µm gate periphery. The input matching network (101) matches 50 Ohm RF impedance (RF IN) to the input impedance of the FET (102) which matched for better noise figure. The inter-stage matching network (103) after the first amplifier (102) matches the output impedance of the first stage amplifier (102) to the input impedance of the second stage amplifier (104). The second stage amplifier (104) consists of a single FET of 300µm gate periphery. The output impedance of the second stage amplifier (104) is matched to 50 Ohm (RF OUT) by the output matching network (105) for better return loss at the output. The amplifier is dc blocked internally using FET (206, 207) and is self-biased by RC network (201, 203). The inter-stage matching network (103) is matched with lumped circuit (202). The output matching network (105) is designed with series of capacitors mentioned as (205). Output power can be controlled by using resistor circuit (204).
[0045] The low noise amplifier (100) has been self-biased to ensure single supply operation. For maintaining stability of the amplifier (100), Rollet’s stability factor and Nyquist stability analysis was used. The design focused on low noise figure, high gain with moderate return losses at both input and output ports.
[0046] Referring to figure 3, shows return losses are 15dB typical at both the input and the output ports over the C Band frequency and gain of 22dB typical.
[0047] Referring to figure 4, it shows the output power 1dB compression (OP1) response of LNA. The output power at which the amplifier gain compressed by 1dB from its actual values and is +10dBm in C band frequency.
[0048] Referring to figure 5, it shows the measured output IP3dBm (OIP3) of proposed LNA at 3.5V. For this, two fundamental tones are applied at the input of the amplifier with frequency separation of 10MHz. The OIP3 output is monitored at amplifier output and is 20dB typical in C band frequency.
[0049] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We Claim:
1. A narrow C-band ultra-low noise amplifier comprising:
at least two amplifier stages having an input stage amplifier (102) and an output stage amplifier (104) connected between input (RFIN) & output (RFOUT) RF signal ports through at least three matching networks including an input matching network (101), an intermediate matching network (103) and an output matching network (105); wherein
in first amplifier stage, the input matching network (101) connected between the input RF signal and the input stage amplifier (102), the input matching network (101) receives input RF signal and matches 50 Ohm RF impedance of input impedance of input stage amplifier (102);
the inter-stage matching network (103) connected between the input stage amplifier (102) and the output stage amplifier (104), the inter-stage matching network (103) matches 50 Ohm RF impedance of output impedance of the first stage amplifier (102) to 50 Ohm RF impedance of input impedance of the output stage amplifier (104); and
in the second amplifier stage, the output matching network (105) connected between the output RF signal port (RFOUT) and the output stage amplifier (104), the output matching network (105) matches 50 Ohm RF impedance of output impedance of the second stage amplifier (104) to 50 Ohm RF impedance of the output RF signal port (RFOUT).
2. The narrow C-band ultra-low noise amplifier as claimed in claim 1, wherein the first stage amplifier (102) has of a single FET of 300µm gate periphery.
3. The narrow C-band ultra-low noise amplifier as claimed in claim 1, wherein the second stage amplifier (104) has of a single FET of 300µm gate periphery.
4. The narrow C-band ultra-low noise amplifier as claimed in claim 1, wherein the input matching network (101) comprises a FET (206) and a RC network (201).
5. The narrow C-band ultra-low noise amplifier as claimed in claim 1, wherein the inter-stage matching network (103) comprises lumped circuit (202).
6. The narrow C-band ultra-low noise amplifier as claimed in claim 1, wherein the output matching network (105) comprises series of capacitors (205) of effective capacitance value less than 0.1pF and resistor circuit (204) wherein the output power of output matching network (105) can be controlled by using the resistor circuit (204).
7. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the amplifier (100) is dc blocked internally using the FET (206, 207) and is self-biased by the RC network (201, 203).
8. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein return losses are better than 15dB at both the input and the output ports over the C Band frequency.
9. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the amplifier (100) is self-biased circuit with single supply operation can operate from 2V to 4V with low current consumption of 30mA typical at 3V supply.
10. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein output power compression of the amplifier (100) at 1dB is minimum +10dBm and Output third order intercept point of minimum +20dBm.
11. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the amplifier (100) is unconditionally stable up to 40GHz analysed by using Nyquist and stability circle criteria.
12. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the output power of amplifier (100) is controlled by changing gate bias of second stage amplifier (104).
13. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein maximum power handling capability of the amplifier (100) is upto +27dBm.
14. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein reverse recovery time of the amplifier (100) is less than 110nS.
15. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the amplifier (100) is a single chip having a die size less than 1.5mm X 1.5 mm with ultra-low noise figure, high gain and miniature in size operating in continuous wave mode.
16. The narrow C-band ultra-low noise amplifier (100) as claimed in claim 1, wherein the amplifier (100) is realized using 0.15 µm GaAs pHEMT (pseudomorphic high electron mobility transistor) process in C-band.

Dated this 30th day of March, 2023

For BHARAT ELECTRONICS LIMITED
(By their Agent)

D. MANOJ KUMAR (IN/PA-2110)
KRISHNA & SAURASTRI ASSOCIATES LLP.