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Title -
A Near-Threshold 10T SRAM Cell With High Read and Write Margins for Tri-Gated FinFET Technology

BACKGROUND
FIELD OF THE INVENTION
Embodiments of the present invention relate to semiconductor memory device, and more particularly to a low power consumption static random access memory (SRAM) cell that is designed for low voltage (near-threshold) operation.
BACKGROUND OF THE INVENTION
Increasing demand of clinical needs has in turn increased use of battery-operated implantable medical devices. These devices employ programmable SOCs, where SRAM occupies a considerable portion of the total power consumption. In order to maximize the battery life, ultra-low power consumption becomes the primary requirement of such devices. An effective way to reduce power consumption of SRAM is to scale down the supply voltage (VDD), as it delivers quadratic saving in dynamic power consumption, and a linear reduction in leakage power. The benefit of sizeable reduction in power consumption without experiencing the severe speed degradation makes near-threshold (VDD near to threshold (Vj)) operating region the choice of interest in ultra low power and high performance digital circuits designs.
On the other hand, operating SRAM cell in near-Vy region reduces ON/OFF current ratio and diminishes the static noise margin (SNM). Further, at low VDD, cell is more susceptible to VT variability caused by process variations. Fig. 1 shows circuit diagram of the commercial and widely used SRAM 6T cell (100) according to the prior art. SRAM cell (100) comprises a latching circuitry, a write port including two pass transistors (PGL, PGR), two bit lines (BL and BLB) and a word line (WL). However, the commercial 6T cell is susceptible to functional failures at low VDD due to its poor read data stability, higher susceptibility to process variations and device mismatch. Hence, the SRAM cell (100) fails to achieve reliable operation in near-Vr operating region. Both theoretical and measured analysis show that standard SRAM cell (100) is limited to operating voltages of no lower than 700 mV.
Efforts of reducing the functional failures at low VDD and improving data stability (SNM) have been made at different levels of abstractions (device, circuit and system) in SRAM design. Improvement at device level is attempted with the help of an advanced MOSFET device - FinFET. The three-dimensional gate structure of FinFET can control the channel more effectively and inhibit leakage current. Further, FinFET can greatly reduce the size of semiconductor chips and the power consumed by each logical gate as compared to the conventional MOSFET. Improvement at the circuit level is attempted by adding transistors into the conventional 6T SRAM cell (100) configuration. Several new MOSFET based SRAM cell configurations like 7T, 8T, 9T, 10T have been proposed in the past.
Fig. 2 shows a circuit diagram of a recently reported MOSFET based differential sensing 10T P-P-N SRAM cell (200) according to the prior art. In SRAM cell (200), each of the

cross-coupled inverter is composed of three transistors cascaded in a P-P-N sequence from top to bottom. The nodes between the two cascaded P-MOS transistors are called pseudo storage nodes (pQ and pQB), which are separate from the true storage nodes (Q and QB). SRAM Cell (200) includes separate bit line discharging path (PGL-PDU, PGR-PDRI) on each side of the cell. Since bit lines are isolated from the true storage node through pseudo storage node, this cell offers similar data stability during read and hold operation. In addition to the standard IO of SRAM cell (100), SRAM cell (200) includes one extra signal VGND. This signal is connected to GND during read operation; otherwise it is connected to VDD to curb bit-line leakage current.
However, write path of the SRAM cell (200) consists of two transistors and it is longer as compared to that of SRAM cell (100). Moreover, during write operation, data flipping process at low supply voltage is also slower in this cell due to conflict in the charge and discharge currents. This in turn produces larger write delay and degraded write margin (WM) in near-Vr operating region. Further, the extra signal VGND demands additional periphery causes significant area overhead.
SUMMARY
The objective of present invention is to provide a SRAM cell having higher data stability and robust functionality in near-Vr operating region with extended write margin and smaller write delay.
Additional, and/or other aspects and/or advantages of the embodiments of the present invention are set forth in the detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
The drawings that are related to the present invention use reference numbers to choose similar or equivalent elements.
In the accompanying drawings:
FIG. 1 is a circuit diagram of a commercial 6-T SRAM cell (100) according to the prior art;
FIG. 2 is a circuit diagram of a 10T P-P-N SRAM cell (200) according to the prior art;
FIG. 3 is a circuit diagram of a SRAM cell according to an embodiment of the present invention;
FIG. 4A is a circuit diagram that shows how the read-0 operation is carried out in SRAM cell according to an embodiment of the present invention;

FIG. 4B is a circuit diagram that shows how the write-1 operation is carried out in SRAM cell according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a FinFET based implementation of a 10T P-P-N SRAM cell.
FIG. 6 shows butterfly curves along with measured read static noise margin (RSNM) values in near-Vr operating region for the SRAM of the present invention and the 10T P-P-N cell.
DETAILED DESCRIPTION
For the purposes of this disclosure, the term "VDD" is understood to refer to a power supply node with a potential suitable for source node of p-type Fin-type-Field Effect Transistor (FinFET). Similarly, the term "GND" is understood to refer to a power supply node with a potential suitable for source nodes of n-type FinFET, and is lower than the VDD potential. The term "Word line" is understood to denote an interconnect element connected to gate nodes of pass transistors of SRAM cell. The terms "bit line" and "bit-bar line" are understood to refer to data lines connected to pass transistors of write port and read buffers of a SRAM cells. The term "bit-side" is understood to refer to elements such as pass transistor connected to a storage node in an SRAM cell. Similarly, the term "bit-bar-side" is understood to refer to elements connected to an opposite storage node from the bit-side node in the SRAM cell. A bit-side data line is commonly referred to as a bit line. A bit-bar-side data line is commonly referred to as a bit-bar line.
Fig. 3 is a circuit diagram of a FinFET based near-Vx differential sensing 10T SRAM cell (300) formed according to an embodiment of the present invention. The SRAM cell (300) is implemented using tri-gated FinFET devices at 20nm technology with different number of fins. In the Fig. 3, the numbers in the bracket indicate the number of fins for the respective FinFET device. The FinFET technology parameters used in this embodiment have a minimum channel length (L) of 24 nm, equivalent oxide thickness (EOT) of 0.84 nm, fin thickness (tSi) of 15 nm, and fin height (Hfjn) of 28 nm. The work function of n-type FinFET and p-type FinFET is 4.56 eV and 4.62eV respectively.
The SRAM cell (300) comprises a latching circuitry (314), write port, bit-side storage node (322), bit-bar-side storage node (324), first read buffer (330), second read buffer (338), write word line (316), read word line (332), bit line (326), bit-bar line (328), VDD node (302) and VSS node (304).
Latching circuitry (314) comprises a pair of cross-coupled inverters. The inverter formed at bit-side includes a p-type FinFET (306) acting as a load transistor and n-type FinFET (308) acting as a driver transistor. Similarly, the inverter formed at bit-bar-side includes a load transistor (310) and driver transistor (312). The gate node of the load and driver transistors are connected to an opposite storage node of SRAM cell. A source node of load transistors (306 and 310) is connected to node VDD (302). A source node of a driver transistor is connected to a VSS node (304).

Write port of the SRAM cell (300) comprises bit-side pass gate FinFET (318) and bit-bar-side pass gate FinFET (320). A gate node of FinFET (318) and FinFET (320) are connected to write word line (316). A first source/drain of bit-side pass gate FinFET is connected to the bit-side storage node (322) and a second source/drain of bit-side pass gate FinFET is connected to the bit-line (326) respectively. Similarly, a first source/drain of bit-bar-side pass gate FinFET is connected to the bit-bar-side storage node (324) and second source/drain of bit-bar-side pass gate FinFET is connected to bit-bar line (328).
The first read buffer (300) includes two n-type FinFETs. One of them acts as a switching transistor (334) and another as a pass gate transistor (336). A first source/drain node of switching transistor (334) is connected to read word line (332) and second source/drain node of switching transistor (334) is connected to gate node of pass gate transistor (336). The gate node of switching transistor (334) is connected to opposite storage node (324). A first source/drain node of pass gate transistor (336) is connected to bit-line (326) and second source/drain node of pass gate transistor (336) is connected to ground potential through a VSS node (304).
The second read buffer (338) is configured similarly to the first read buffer (330). The second read buffer (338) includes switching transistor (340) and pass gate transistor (342). A first source/drain node of switching transistor (340) is connected to read word line (332) and second source/drain node of switching transistor (340) is connected to gate node of pass gate transistor (342). The gate node of switching transistor (334) is connected to opposite storage node (322). A first source/drain node of pass gate transistor (342) is connected to bit-line (328) and second source/drain node of pass gate transistor (342) is connected to ground potential through a VSS node (304).
Fig. 4A is a circuit diagram that shows how read-0 operation is carried out using first read buffer (330) of SRAM cell (300) by assuming data condition at storage node (322) as '0' and (324) as T. To perform a read operation, the read wordline (332) is driven to VDD and write wordline (316) is discharged to ground. Based on the above data conditions, switching transistor (334) of first read buffer (330) turns ON while switching transistor (340) of second read buffer (338) turns OFF. This turns ON the pass transistor (336) of first read buffer and turns OFF the pass transistor (342) of second read buffer. Hence, bit line (326) discharges through pass transistor (336) while bit-bar line (328) maintains voltage level VDD- Since, storage data (322) is isolated from bit line (326) by first read buffer (330), read current (bit line discharging current) does not flow through the storage node (322). This suppresses voltage level rising at noise-vulnerable storage node (322) and offers near-ideal inverter characteristics having Vtnp point close to VQD/2. These in turn offers similar data stability during read and hold operations and makes the SRAM cell (300) robust in near-Vj operating region and also under the influence of process variations. Two series connected pMOS transistors (PULI-PUL2 and PURI-PUR2) reduce the pull-up strength of the inverter pair in 10T P-P-N SRAM cell (200) and reduces the read data stability as compared to SRAM cell (300).

Moreover, during read operation, bit line (326) has to discharge through single pass transistor (336) only, once switching transistor (334) turns ON. This improves access delay as compared to SRAM cell (200). However, while operating SRAM cell (300) in the near-Vj region, it is essential to boost up the voltage level of read word line (332) in order to conduct one of the pass transistors (336) in the strong inversion region and subsequently to reduce the read delay. Additionally, gate voltage of the pass transistor (336) is quite smaller than VDD (Voltage level of read word line (332) - threshold voltage of switching transistor (334)) in the SRAM cell (300). However, gate voltage of pass transistor is equal to VDD in the 10T P-P-N SRAM cell, which limits the read current in the SRAM cell (300) resulting in to smaller active read power dissipation than 10T P-P-N SRAM cell (200).
Furthermore, read word line (332) is connected on the drain node of switching transistors (334) of first read buffer and (340) of second read buffer to enable the abutment of drain diffusion region of switching transistors of adjacent cell. It is nothing but the drain diffusion region of switching transistor (340) of the SRAM cell (300) can be abutted with drain diffusion region of switching transistor (334) of adjacent SRAM cell (300) to increase area efficiency of SRAM array.
Likewise read-0 operation, read-l operation is carried out using second read buffer (338) of SRAM cell (300) by assuming storage node (322) as '1' and (324) as '0'.
Thus, the read buffer of the SRAM cell (300) of the present invention allows higher data stability; smaller access delay and active read power dissipation with improved area efficiency.
Fig. 4B is a circuit diagram that shows write-1 operation is carried out in SRAM cell (300) by assuming data condition at storage node (322) as '0' and (324) as T. To perform a write operation, the write wordline (316) is driven to VDD and read wordline (332) is discharged to ground. Bit line (326) is driven to VDD and bit-bar line (328) is discharged to ground. Storage node (324) initially holding '1' is pulled down through discharging path formed by pass transistor (320) and driver transistor (312). In turn, storage node (322) is charged towards ' 1' to complete the data flipping process. Likewise write-1 operation, write-0 operation is carried out by discharging bit line (326) and applying VDD on bit line (326).
It can be seen from the Fig. 4B that the write operation of the SRAM cell 300 is equivalent to that of commercial 6T cell (100), since SRAM cell (300) has virtually similar topology as that of the conventional 6T cell (100) during write operation. Hence, the SRAM cell (300) overcomes the limitations of poor write margin (WM) and larger write delay of SRAM cell (200) in near-Vy operating region.
Importantly, use of FinFET based LP configuration (high Vj devices) as an SRAM cell transistor, avoids need of VGND biasing scheme along with the assist circuitry to control the bit-line leakage and makes our cell design simpler and area efficient as compared to SRAM cell (200).

To evaluate the SRAM 10T cell (300) according to embodiment of the present invention, simulations are carried out in near-Vx operating region with VDD=0.6 V, given that the Vr of FinFET device is 0.4 V. For performance comparison, SRAM 10T P-P-N cell (200) is implemented using aforementioned FinFET technology parameters. Fig. 5 is an illustrative circuit schematic (500) for a FinFET based implementation of a 10T P-P-N SRAM cell. In the discussion below, Read-and-Write-Margin-Improved SRAM cell (300) according to an embodiment of the present invention is referred as the "RWM-Improved SRAM Cell".
Fig. 6 shows butterfly curves (600) along with measured read static noise margin (RSNM) values in near-Vr operating region for the RWM-Improved SRAM Cell and the 10T P-P-N cell (500). The RWM-Improved SRAM Cell offers higher RSNM as compared to the 10T P-P-N cell (500) as observed from Fig. 6. Two series connected pMOS transistors (PULI-PUL2 and PURI-PUR2) reduce the pull-up strength of the inverter pair in 10T P-P-N SRAM cell (500) and reduces the RSNM. It is also observed from the Fig. 6 that RWM-Improved SRAM Cell has near-ideal inverter characteristics with Vtrip point close to VDD/2, which is essential for robust read operation in near-Vr region. The simulation results of performance metrics related to data stability, delay and power dissipation are shown in Table 1.
TABLE 1
10T P-P-N Cell RWM-Improved
SRAM Cell
RSNM(mV) 199 213
HSNM(mV) 199 213
Write Margin (mV) 106 144
Read Delay (ps) 1171 984
Write Delay (ps) 425 350
Active read power 1.76 1.42
dissipation (|J.W)
Static Power (nW) 180 190
It can be observed from Table 1 that the write margin of RWM-Improved SRAM cell is higher than that of 10T P-P-N Cell (500), since the write path of the RWM-Improved SRAM Cell is smaller as compared to that of 10T P-P-N Cell (500). The read delay is smaller in RWM-Improved SRAM Cell as compared to 10T P-P-N Cell. During read-0 operation, bit line (326) has to discharge through single pass transistor (336) in RWM-Improved SRAM Cell, while it has to discharge through two transistors (PGL-PDL1) in the SRAM 10T P-P-N cell (500). The active read power dissipation of RWM-Improved SRAM Cell is smaller than 10T P-P-N SRAM cell due to smaller gate voltage of the pass transistor during read operation. Note that RWM-Improved SRAM cell controls bit-line leakage with the help of FinFET based LP configuration as an SRAM cell transistors in absence of VGDN biasing scheme. The static power dissipation reported in Table 1 includes bit-line leakage and is marginally higher in case of RWM-Improved SRAM cell as compared to 10T P-P-N SRAM Cell (500).

Embodiment of the present invention can be utilized in different types of battery-operated implantable medical devices like peace maker, hearing aids etc., and also in wireless low-power sensor networks.

We Claim-
1. A near-threshold 10T SRAM cell with high read and write margins comprising:
a pair of cross-coupled inverters, said cross-coupled inverters include a bit-side storage node and a bit-bar side storage node;
a write port coupled to the said pair of cross-coupled inverters. A said write port includes bit-side and bit-bar-side pass gate transistors. Gate node of the said bit-side and bit-bar-side pass transistors are connected to write word line. First source/drain of said bit-side pass gate transistor is connected to the bit-side storage node and the second source/drain of said bit-side pass gate transistor is connected to the bit-line. A first source/drain of bit-bar-side pass gate transistor is connected to the bit-bar-side storage node and second source/drain of bit-bar-side pass gate transistor is connected to bit-bar line;
a first read buffer includes switching transistor and pass gate transistor. A first source/drain node of said switching transistor is connected to read word line and second source/drain node of said switching transistor is connected to gate node of said pass gate transistor. The gate node of said switching transistor is connected to opposite side storage node. A first source/drain node of said pass gate transistor is connected to bit-line and second source/drain node of said pass gate transistor is connected to ground potential;
a second read buffer also includes switching transistor and pass gate transistor. A first source/drain node of said switching transistor is connected to read word line and second source/drain node of said switching transistor is connected to gate node of said pass gate transistor. The gate node of said switching transistor is connected to opposite storage node. A first source/drain node of said pass gate transistor is connected to bit-bar-line and second source/drain node of said pass gate transistor is connected to ground potential;
2. The SRAM cell of claim 1 enables the abutment of drain diffusion region of said switching transistors of adjacent SRAM cells.
3. The SRAM cell of claim 1, wherein the cell transistors are implemented using tri-gated Fin-type Field Effect Transistor (FinFET) devices.
4. The SRAM cell of claim 3, where the cell transistors are FinFET based LP configuration. These high VT devices are of short channel length.
5. The SRAM cell of claim 4, avoids need of VGND biasing scheme along with the assist circuitry and control the bit-line leakage with the help of high VT devices in cell transistors.
6. The SRAM cell of claim 5 offers reliable read and write operations at supply voltage near threshold voltage of cell transistors.