Description:FIELD OF INVENTION
The present disclosure relates to the field of computer engineering. More particularly, the present disclosure relates to a novel architecture for FPGA implementation of 5G-NR PDCCH chain.

BACKGROUND OF THE INVENTION
In the field of computer engineering, particularly in the realm of communications technology, advancements continue to enhance data processing and transmission capabilities. A critical aspect of modern telecommunications involves the efficient implementation of communication standards, such as the Fifth Generation New Radio (5G-NR) technology, which supports a multitude of features essential for today's high-speed wireless communication demands. Among these, the Physical Downlink Control Channel (PDCCH) plays a pivotal role by carrying crucial control information. Field-Programmable Gate Arrays (FPGAs) are increasingly utilized due to their reconfigurability and high processing capabilities, making them suitable for implementing complex communication algorithms. Effective FPGA architectures that can support and optimize the PDCCH in 5G-NR systems are thus crucial in leveraging the full advantages of 5G technology.

While existing solutions implement processing functions in the Physical Downlink Control Channel (PDCCH) chain, several limitations and inefficiencies remain apparent. Prior designs may not adequately optimize the use of resources such as Look-Up Tables (LUTs), Digital Signal Processors (DSPs), and registers, thereby increasing resource consumption. Further, these designs may lead to high latency and low throughput, hampering real-time communication requirements and contributing to substandard performance in the context of 5G-New Radio standards. The traditional models also fall short in terms of efficient rate matching, including a suboptimal alignment between the polar-encoded bits and the bits available for PDCCH transmission. Furthermore, the prior art might indicate a discrete [separate, individual] handling of Cyclic Redundancy Check (CRC) attachment and polar coding, leading to increased complexity and inflexibility. Lastly, there are observable constraints concerning user support and scalability, hampering the potential for wider application and adaptability in varied 5G networking environments.

With the technological advancements and growing needs of 5G-New Radio standards, there emerges an urgent need to address these limitations of the prior art. An efficient and optimized approach is necessary that can balance resource consumption, meet the stringent latency requirements, streamline the rate matching process, and offer integrated handling of CRC attachment and polar coding. Furthermore, considerable improvements can be made by enhancing the support for a larger number of users and ensuring scalability meets the demands of varied 5G networking environments. Thus, a new solution is required that overcomes the limitations of the former approaches and meets the evolving, more demanding standards of 5G networks.

SUMMARY
One or more of the problems of the conventional prior art may be overcome by various embodiments of the present disclosure.

In one aspect of the present disclosure, the invention provides an architecture for implementing a 5G-NR Physical Downlink Control Channel (PDCCH) transmitter chain on an FPGA. This encompasses various IPs like a sub-block interleaver (SBI) IP, SBI- bit selection (BS) interconnect IP, bit selection IP, golden sequence generator IP and scrambler IP, CRC attachment and polar coding IP, and modulation IP. This architecture is designed to achieve an iterative latency of 1.46 μs and a throughput of 1.2 Gbps.

In another aspect of the present disclosure, the architecture leverages a sub-block interleaver IP that uses a look-up table to store the interleaving pattern. Furthermore, parameters B, kmax, and a are computed to define the number of bits stored in each sub-block and the size of the data bus.

In another aspect of the present disclosure, the bit selection process of the architecture includes steps like shortening, puncturing, and repetition, where the SBI-BS interconnect IP emphasis is on a 108-bit data width to reduce processing complexity.

In another aspect of the present disclosure, the Golden sequence generator IP in architecture builds the scrambling sequence based the physical cell identity or a UE-specific scrambling identity and a cell RNTI, with a pseudo-random binary sequence of length 31.

In another aspect of the present disclosure, this architecture incorporates a modulation IP that maps 2 bits into a symbol using QPSK modulation, with grouping of 18 symbols into a single burst of 576 bits.

In another aspect of the present disclosure, the invention provides a method for implementing a hardware-efficient 5G-NR PDCCH transmitter chain on an FPGA. It includes steps such as dividing the encoded bits, performing bit selection and adjusting the data width, generating a scrambling sequence, attaching CRC and encoding bits, and modulating the scrambled bits.

In another aspect of the present disclosure, the method practiced uses a sub-block interleaver that stores interleaving patterns in a look-up table, performing the interleaving based on predefined parameters.

In another aspect of the present disclosure, the bit selection procedure in the method involves performing bit selection, optimizing resource usage with a data width of 108 bits while implementing shortening, puncturing, and the repetition step.

In yet another aspect of the present disclosure, the method of implementing a hardware-efficient 5G-NR PDCCH transmitter chain on an FPGA includes configuring CRC attachment and Polar coding using a polar configuration block and a parameter handler, which manages the code parameters and CRC initialization.

DETAILED DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, show certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed implementations. In the drawing,
Figure 1 illustrates Novel Architecture design for the hardware implementation of PDCCH transmitter chain in accordance with the present invention.
Figure 2 illustrates naive architecture for PDCCH implementation

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Various embodiments of the disclosure are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the disclosure. Thus, the following description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding of the disclosure. However, in certain instances, known details are not described in order to avoid obscuring the description.
References to one or an embodiment in the present disclosure can be references to the same embodiment or any embodiment; and, such references mean at least one of the embodiments.
Reference to "one embodiment", "an embodiment", “one aspect”, “some aspects”, “an aspect” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others.
The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Alternative language and synonyms may be used for any one or more of the terms discussed herein, and no special significance should be placed upon whether or not a term is elaborated or discussed herein. In some cases, synonyms for certain terms are provided.
A recital of one or more synonyms does not exclude the use of other synonyms.
The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only and is not intended to further limit the scope and meaning of the disclosure or of any example term. Likewise, the disclosure is not limited to various embodiments given in this specification. Without intent to limit the scope of the disclosure, examples of instruments, apparatus, methods and their related results according to the embodiments of the present disclosure are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the disclosure. Unless otherwise defined, technical and scientific terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the case of conflict, the present document, including definitions will control.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or can be learned by practice of the herein disclosed principles. The features and advantages of the disclosure can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the disclosure will become more fully apparent from the following description and appended claims or can be learned by the practice of the principles set forth herein.
The term “user” is referred as a person who is operating the system aka user equipment or a cellular mobile.
The term “RTL file” refers to Register Transfer Level file, a type of hardware description language (HDL) file used in digital circuit design.
The term “FPGA” refers to "Field-Programmable Gate Array", a type of programmable logic device that can be configured to implement digital circuits.
As mentioned before, there is a need for an efficient and optimized approach that is necessary that can balance resource consumption, meet the stringent latency requirements, streamline the rate matching process, and offer integrated handling of CRC attachment and polar coding. Furthermore, considerable improvements can be made by enhancing the support for a larger number of users and ensuring scalability meets the demands of varied 5G networking environments. Thus, a new solution is required that overcomes the limitations of the former approaches and meets the evolving, more demanding standards of 5G networks.
Abbreviations
FPGA - Field-Programmable Gate Array
5G-NR - Fifth Generation New Radio
PDCCH - Physical Downlink Control Channel
DCI - Downlink Control Information
LUT - Look-Up Table
DSP - Digital Signal Processor
CRC - Cyclic Redundancy Check
IP – Intellectual Property
SBI - Sub-Block Interleaver
SBI-BS Interconnect - Sub-Block Interleaver - Bit Selection Interconnect
UE – User Equipment
RNTI – Radio Network Temporary Identifier
QPSK – Quadrature Phase Shift Keying
RTL - Register Transfer Level
HDL - Hardware Description Language
DAC - Digital-to-Analog Converter
ORAN – Open Radio Access Network
DU - Distributed Unit
3GPP – Third Generation Partnership Project
OFDM – Orthogonal Frequency Division Modulation
PRBS - Pseudo-Random Binary Sequence
HLS - High-Level Synthesis
IDE - Integrated Development Environment

The rate matching procedure comprises the Sub-Block Interleaver (SBI) and bit selection operations. To optimize the bit selection process, the bit selection operation is divided into the SBI-BS interconnect and bit selection IPs. Accordingly, the rate matching procedure is implemented using three distinct IPs: the SBI IP, the SBI-BS interconnect IP, and the bit selection IP. This configuration is structured to achieve compliance with 5G frame boundaries while minimizing resource utilization. The following section details the hardware implementation of each IP

Despite notable advancements in the field, current systems for PDCCH processing in 5G-NR face several limitations such as high resource consumption, suboptimal rate matching, and increased complexity due to individual handling of CRC attachment and polar coding. These systems also lack efficient user support and scalability in diverse 5G networking environments, leading to a latency and throughput that does not meet the high-speed communication demands. Therefore, there is a clear and imminent need for a new invention which can overcome these limitations and meet the evolving demands of the 5G standard.

In an embodiment of the present invention, architecture is configured for the implementation of a 5G-NR Physical Downlink Control Channel (PDCCH) transmitter chain on a Field Programmable Gate Array (FPGA). Its structure includes a sub-block interleaver Intellectual Property (IP) which is specifically designed to perform sub-block interleaving of encoded bits. The encoded bits are divided into 32 separate sub-blocks that follow an interleaving pattern determined before use. This sub-block interleaver IP shows a resource consumption of 1334 Look-Up Tables (LUTs), 4 Digital Signal Processors (DSPs), and 1559 registers.

This embodiment is further optimized with the incorporation of a SBI-BS interconnect IP and bit selection IP to adjust the bit width from an input of 128 bits to an output of 108 bits and to carry out bit selection. The resource requirement stands in 1797 LUTs and 2203 registers. This carefully planned configuration results in a Golden sequence generator IP and a scrambler IP for the generation of a pseudo-random binary scrambling sequence. This arrangement also facilitates the scrambling of the payload bits of Downlink Control Information (DCI). The scrambler IP unit is recognized for its efficient resource consumption, utilizing 356 LUTs and 671 registers.

In the same manner, the architecture includes a CRC attachment and Polar coding IP incorporating the two elements into one unit. This combination operates with two functional blocks, namely a polar configuration block and a parameter handler. They retain the function to manage the parameters for the polar code and the CRC configuration.

Simultaneously, the design consists of a modulation IP, devised to map scrambled bits into symbols, keeping the Digital-to-Analog Converter (DAC) resolution into account. This modulation IP consumes 260 LUTs and 490 registers. The overall architecture is designed to achieve an iterative latency of 1.46 μs and a throughput of 1.2 Gbps. These outcomes are well within the standards of the 5G-NR frame requirements.

Further outlining the details of the architecture, the sub-block interleaver IP utilizes a look-up table to store the interleaving pattern. Parameters such as B, kmax, and a can be computed to define the number of bits stored in each sub-block and determine the size of the data bus.

The bit selection process includes shortening, puncturing, and repetition operations, with a separate SBI-BS interconnect IP adjusting the data width processing data in 108-bit widths to reduce complexity in subsequent PDCCH chain operations. Moreover, the physical attributes of the scrambling sequence are formed based on the physical layer cell identity or User Equipment (UE)-specific scrambling identity and cell RNTI. This sequence has a pseudo-random binary sequence of 31.

Moreover, the modulation IP maps 2 bits into a symbol leveraging Quadrature Phase Shift Keying (QPSK) modulation. Resultantly, 18 symbols are grouped into a single burst of 576 bits. The architecture reveals a method for implementing a hardware-efficient 5G-NR PDCCH transmitter chain on an FPGA efficiently by incorporating and closely integrating several parameters and technological elements.
The present invention relates to a novel, hardware-efficient architecture for implementing the Physical Downlink Control Channel (PDCCH) transmitter chain in 5G New Radio (5G-NR) systems, particularly leveraging Field-Programmable Gate Arrays (FPGAs). The disclosed architecture is designed to comply with the 3GPP standards, and the ORAN split 7.2.x for distributed unit (DU) designs, providing significant improvements in resource utilization, latency, and throughput over prior systems. The invention addresses the high-performance requirements of 5G-NR frames by optimizing several functional blocks involved in PDCCH processing.

The disclosed architecture of the PDCCH transmitter chain is structured into distinct functional blocks, each implemented in a hardware-efficient manner. These functional blocks include a sub-block interleaver, SBI-BS interconnect IP, Bit selection IP, Golden sequence generator, scrambler, CRC attachment and Polar coding IP, and a modulation IP. The architecture enables the efficient processing of Downlink Control Information (DCI), achieving an iterative latency of 1.46 μs and a throughput of 1.2 Gbps, which is below the duration of an OFDM symbol for any numerology in 5G-NR.

The sub-block interleaving procedure is a key component in the rate matching process, ensuring that the output of the polar encoder aligns with the number of bits available for PDCCH transmission. The sub-block interleaver IP divides the encoded bits into 32 sub-blocks, each containing N/32 bits, where N is the number of encoded bits. These sub-blocks are interleaved according to a predefined pattern stored in a look-up table (LUT). The hardware implementation of the sub-block interleaver is optimized to consume 1334 LUTs, 4 DSPs, and 1559 registers, making it suitable for real-time processing in 5G-NR systems. The interleaving pattern ensures that bits are scattered across sub-blocks to improve error resilience during transmission.

The architecture includes a two-step bit selection process comprising of SBI-BS interconnect IP and Bit selection IP. These IP blocks handle the bit selection process and ensure the alignment of bits with the required frame size. The SBI-BS interconnect IP adjusts the data width from 128 bits at the input to 108 bits at the output, optimizing the data path for subsequent processing. The Bit Selction IP performs the final bit selection, including shortening, puncturing, and repetition, based on the frame requirements of the PDCCH. They consume 1797 LUTs and 2203 registers, ensuring low latency and efficient resource utilization. This ensures that the precise number of bits required for transmission is selected, thereby reducing computational complexity.

The scrambling of the payload bits in the DCI is performed using a golden sequence, which is a pseudo-random binary sequence (PRBS). The golden sequence is generated based on the physical layer cell identity or a UE-specific scrambling identity in conjunction with the UE-specific cell RNTI. The Golden sequence generator IP and scrambler IP are implemented as two distinct functional blocks optimized for hardware efficiency. The golden sequence generator consumes 626 LUTs and 531 registers, while the scrambler consumes 356 LUTs and 671 registers. These implementations provide a highly efficient scrambling process in terms of both latency and resource usage.

An innovative aspect of the present architecture is the integration of the CRC attachment and Polar coding into a single IP. This integrated implementation reduces the system's complexity while maintaining compliance with 5G-NR standards. Two additional functional blocks are introduced to manage the configuration of the Polar coding process: the polar configuration block calculates the appropriate register values for feeding into the polar encoder, and the parameter handler configures both the core parameters and the code-specific parameters for the Polar IP. This integrated IP allows for the flexible use of off-the-shelf CRC and Polar coding IPs, ensuring scalability and reduced resource consumption, particularly in terms of LUTs and registers.

After scrambling, the scrambled bits are mapped into symbols using a modulation scheme. The architecture implements Quadrature Phase Shift Keying (QPSK) modulation, mapping 2 bits into a symbol. The modulation process is further optimized to ensure that the bits are mapped to symbols while considering the resolution of the Digital-to-Analog Converter (DAC). The modulation IP consumes 260 LUTs and 490 registers, and the output is structured to handle 18 symbols in a single burst, each representing 576 bits. This configuration allows for efficient symbol processing, thereby reducing latency and improving throughput.

The architecture is designed to meet the stringent latency and throughput requirements of 5G-NR. Specifically, it achieves an iterative latency of 1.46 μs and a throughput of 1.2 Gbps, ensuring that the DCI for one user is processed in a time significantly less than the duration of an OFDM symbol for any numerology in 5G-NR. The architecture can support 45/2^μ users for ∆f = 2^μ × 15 KHz subcarrier spacing, where μ ∈ {0, 1, 2, 3, 4}, with the duration of the OFDM symbol being T = 66.7/2^μ μs. This scalability enables the architecture to support more users when the PDCCH is allocated across multiple OFDM symbols.

The present invention provides a novel, hardware-efficient architecture for implementing the PDCCH transmitter chain in 5G-NR systems. By optimizing the rate matching, scrambling, CRC attachment, Polar coding, and modulation processes, the invention achieves significant improvements in latency, throughput, and resource utilization. The architecture is flexible, allowing for the integration of off-the-shelf IPs, and is designed to meet the real-time processing demands of 5G-NR frames, making it a highly effective solution for next-generation communication systems.
Figure 1 illustrates a Novel Architecture design for the hardware implementation of the PDCCH transmitter chain in accordance with the present invention. The block diagram shows the key components of the PDCCH transmitter chain, including the sub-block interleaver, SBI-BS interconnect IP, bit selection IP, golden sequence generator, scrambler, polar encoder, and modulation IP. The figure highlights how these components work together to process the DCI and meet the stringent latency and throughput requirements of 5G-NR, showcasing the architecture's efficiency in terms of resource utilization and performance.

These figures collectively provide a detailed visual representation of the novel architecture and its implementation, ensuring compliance with 5G standards while optimizing hardware performance.
The present invention discloses an architecture for implementing a 5G New Radio (5G-NR) Physical Downlink Control Channel (PDCCH) transmitter chain on a Field Programmable Gate Array (FPGA). The architecture comprises a Sub-Block Interleaver (SBI) (IP) configured to perform sub-block interleaving of encoded bits, consuming 1334 Look-Up Tables (LUTs), 4 Digital Signal Processors (DSPs), and 1559 registers, wherein the encoded bits are divided into 32 sub-blocks interleaved based on a predefined pattern. A data bus configuration accommodates the requirements of different PDCCH procedures, including a 128-bit width for polar encoding and sub-block interleaving, and a 108-bit width for subsequent procedures. This flexible data bus design enhances the processing efficiency by aligning data width with the respective procedural requirements in the 5G-NR PDCCH chain.
The SBI IP is configured to interleave polar-encoded bits to ensure that information bits are aligned with the most reliable encoded bits during the bit selection procedure. According to 3GPP specifications, the SBI operation involves recurrent multiplication and modulus functions, which, if implemented directly in hardware, would lead to high resource consumption and increased latency. To address this, an optimized algorithm is proposed, utilizing an array of size 32 to store and interleave sub-blocks of the encoded bits. The SBI IP is further configured to process bursts of 128 bits per cycle, matching the 128-bit width of the input and output data buses.
Step 1: Establishment of Input and Output Ports
• Dedicated input and output ports are established to facilitate the flow of data into and out of the SBI IP. These ports provide the necessary physical connections for receiving and transmitting data bursts within the hardware module.
Step 2: Loading the Interleaving Pattern
• The interleaving pattern P[n] is pre-stored in a look-up table within the hardware module. This stored pattern defines the arrangement of bits in each sub-block, enabling an efficient hardware-based interleaving process without recalculating the pattern dynamically.
Step 3: Configuration Parameter Setup
• Configuration parameters, such as the number of bits per sub-block and the total bit width of data bursts, are set up. These parameters align the system’s operation with the data structure, ensuring compatibility with the system’s bus and data processing requirements.
Step 4: Initializing a Storage Array
• A hardware storage array, var[32], is initialized with a fixed size. This array temporarily holds the data from each sub-block according to the interleaving pattern before it is transmitted to the output.
Step 5: Calculation of Data Parameters
• Three essential parameters are calculated:
o B determines the number of bits per sub-block.
o k_max is set to match the 128-bit data bus size for efficient data handling.
o a represents the number of 128-bit bursts processed, aligning data handling with the bus width.
• These parameters optimize the hardware’s data handling for resource-efficient operation.
Step 6: Data Acquisition in Input Storage
• 128-bit data bursts are read from the input port and stored temporarily. This input storage serves as the initial holding space for data before the interleaving operation, ensuring smooth, clock-synchronized data acquisition.
Step 7: Organization of Data Bits Using Interleaving Pattern
• Data bits are organized across the storage array var based on the interleaving pattern P[n]:
o Each sub-block of data is stored according to pre-defined positions within var, using P[n] to determine the optimal bit distribution.
• This arrangement ensures that data bits are optimally spread across sub-blocks, enhancing error resilience in downstream processing.
Step 8: Transfer of Interleaved Data to Output
• The interleaved data stored in var is sequentially transferred to the output port. This transfer follows the designated pattern, ensuring that the data leaves the module in the correct order for further processing in subsequent hardware stages.
Step 9: Final Output of Interleaved Data
• The interleaved data is fully outputted from the SBI IP through the output port, completing the interleaving operation. The data is now arranged and ready for efficient downstream processing, ensuring that the hardware module meets latency and throughput requirements.

The steps 1-9 outlined are crucial for achieving hardware efficiency and resource optimization within the SBI IP of the 5G-NR PDCCH framework. By structuring data operations around fixed parameters and using pre-stored interleaving patterns, the method ensures minimal resource utilization on the FPGA. This efficient approach reduces power consumption and component strain, which is essential in 5G applications that demand rapid and reliable data processing. Additionally, the organized sequence of data acquisition, interleaving, and output contributes to low-latency processing, ensuring that 128-bit data bursts are handled efficiently. This helps achieve the targeted iterative latency of 1.46 µs and throughput of 1.2 Gbps, meeting the stringent real-time requirements of 5G-NR networks.
Another important aspect of this approach is its contribution to data transmission reliability. The interleaving pattern enhances error resilience by arranging bits in a way that protects the most reliable ones during transmission, thereby mitigating channel interference and noise. This resilience is critical in 5G, where reliable data delivery is fundamental to maintaining seamless communication. Furthermore, the method’s adherence to 5G-NR standards allows for scalability and adaptability to various configurations, making the architecture compatible with future advancements in 5G technology. This structured handling of data into sub-blocks and 128-bit bursts also facilitates predictable data flow, ensuring precise timing and synchronization across the 5G-NR PDCCH chain. Such predictability reduces complexity in downstream processing, creating a robust and easy-to-maintain design.

To implement the SBI-BS interconnect IP for transferring data in optimized bursts, the steps are as follows:
1. First, identify the input and output data ports necessary for the transfer.
2. Read the configuration data that guides the operation of the interconnect.
3. Calculate the parameter that represents the number of 108-bit bursts required for the output, based on the total number of bits in the transaction.
4. Take the first 128-bit data input and write the initial 108 bits directly to the output port, reserving the remaining bits in a temporary storage for later use.
5. Store the remaining bits from the initial burst in a temporary storage location.
6. Begin a loop to handle the remaining bursts of data for the entire transaction.
7. For each burst, check if it is the last in the transaction.
8. If it is the last burst, transfer the contents of the temporary storage directly to the output port.
9. If it is not the last burst, read the next set of bits from the input, combining them with the previously stored bits.
10. Write this combined set of bits to the output port for continuous data transfer.
11. Update the temporary storage with the remaining bits from the new input for use in the next iteration.
12. Repeat the process until all data bursts are processed and output.
In this implementation, the 128-bit input data is split into efficient 108-bit bursts. The SBI-BS interconnect IP ensures seamless and organized data output by using temporary storage to handle any overflow from each 128-bit input burst, thus optimizing the transfer sequence.
The significance of this optimized SBI-BS interconnect IP lies in its efficient handling of data to meet specific output requirements while minimizing resource usage. By effectively organizing data into 108-bit segments, it aligns with 5G frame requirements, enhancing the accuracy and speed of data handling within the system. Additionally, this method reduces latency by allowing data to be transferred in precise bursts without unnecessary delays, ensuring high performance for real-time applications. Finally, the IP’s design supports scalability and adaptability within various configurations of 5G infrastructure, providing an efficient solution for large-scale data operations. This approach leverages hardware capabilities to manage data flow efficiently, ensuring that the system meets stringent performance demands in modern communication standards.
To implement the bit selection IP, the following steps to be followed,
1. Set up input and output interfaces: This step establishes the channels through which data will enter and exit the system, ensuring a smooth data flow within the bit selection module.
2. Load configuration details: Here, the module retrieves essential information that dictates the mode of operation. This configuration determines whether the module will perform data shortening, puncturing, or repetition based on the data requirements.
3. Calculate segment count and range: A calculation is performed to determine the number of output segments and the bit range for the selection process. This prepares the system for the appropriate data handling based on the mode of operation.
4. Initialize a temporary data storage: A temporary storage array is set up to hold segments of data during processing, particularly in scenarios where repetition is required. This ensures efficient access and manipulation of data.
5. Determine the operation mode: The system evaluates conditions to decide if data shortening or repetition is needed. If either condition is met, the module will proceed with one of these operations.
6. Execute shortening or repetition:
7. For each segment, the data is retrieved, written to the output, and stored temporarily if required. The process is repeated for all segments, with the last segment handled carefully to ensure the correct length, either by appending or truncating data as necessary.
8. Execute puncturing: If the conditions for shortening or repetition are not met, the module proceeds with puncturing.
9. An initial data segment is stored, and for each cycle, additional data is appended and adjusted to meet the required length. Unneeded bits are discarded to maintain data precision and integrity.

Here, this optimized bit selection process enhances data handling efficiency within the system, specifically tailored for high-performance environments where quick data processing is essential. By dynamically managing data shortening, puncturing, and repetition, the system minimizes unnecessary processing and resource usage, making it ideal for applications that demand real-time response.

This approach allows the bit selection module to adapt seamlessly to various data requirements, optimizing data flow and ensuring compatibility across different system configurations. The method's efficiency is further underscored by its ability to maintain low latency and high throughput, even in complex communication systems. Additionally, this structured approach integrates effectively with other processing modules, supporting synchronized, efficient data handling throughout the entire implementation.

The optimized interleaving process in the SBI IP reduces computational complexity by avoiding repetitive operations, instead utilizing a look-up table and efficient bit placement in a fixed array structure. This approach lessens the demand on processing elements, thereby improving overall performance. Moreover, the focus on hardware configurations and structural arrangements over software-like algorithms allows the method to leverage FPGA’s parallel processing capabilities, delivering real-time performance suited to high-data-volume scenarios in 5G networks. By emphasizing hardware-oriented steps, the method ensures compliance with patent regulations, addressing technical challenges in a manner that goes beyond mere algorithms. This hardware-focused solution effectively combines low latency, high throughput, scalability, and error resilience, providing a comprehensive approach to implementing a high-performance PDCCH transmitter chain in a 5G environment.
Further, an SBI-BS interconnect IP and bit selection IPs, which separately handle bit selection operations. The SBI-BS interconnect adjusts the data width from 128 bits at the input to 108 bits at the output, optimizing processing for later stages. The Bit Selection IP perform bit selection procedure. They consume 1797 LUTs and 2203 registers. A Golden Sequence Generator IP and a Scrambler IP are provided for generating a pseudo-random binary scrambling sequence and scrambling the payload bits of Downlink Control Information (DCI), wherein the scrambler consumes 356 LUTs and 671 registers.
The architecture further comprises a CRC attachment and Polar Coding IP, integrating CRC attachment and Polar coding into a single unit, wherein two functional blocks, namely a polar configuration block and a parameter handler, manage parameters for the polar code and CRC configuration. A modulation IP is configured to map scrambled bits into symbols, utilizing Quadrature Phase Shift Keying (QPSK) modulation by considering the Digital-to-Analog Converter (DAC) resolution, consuming 260 LUTs and 490 registers. The overall architecture is designed to achieve an iterative latency of 1.46 microseconds (µs), optimize hardware resource utilization to 1.98% on the RFSoC ZCU111 evaluation board, support a high throughput of 1.2 Gbps, and achieve a power efficiency of 10 Gbps/W at a frequency of 100 MHz, thereby meeting 5G-NR frame requirements.
In another aspect, a method for implementing the 5G-NR PDCCH transmitter chain on an FPGA is disclosed, comprising the steps of dividing encoded bits into a plurality of 32 sub-blocks and performing interleaving using the SBI IP, wherein the interleaving pattern is stored in a look-up table to reduce latency and resource consumption. Bit selection procedure is then performed, where the data width is adjusted from 128 bits to 108 bits by SBI-BS interconnect IP and bit selection is performed by bit selection IP. Further steps include generating a scrambling sequence using a Golden Sequence Generator IP, scrambling the payload bits of DCI, attaching CRC, and encoding the bits using Polar Coding. Modulation of scrambled bits into symbols is achieved using QPSK modulation, with symbols grouped into bursts of 576 bits to improve transmission efficiency.
A comprehensive three-tier testing protocol ensures compliance with 3GPP standards, involving individual IP testing in Vivado High-Level Synthesis (HLS), standalone testing of exported IPs in an Integrated Development Environment (IDE), and end-to-end testing of the integrated PDCCH transmitter chain in the IDE to assess latency, resource usage, throughput, power consumption, and power efficiency. The method further supports multiplexing of DCI for up to 20 users in one OFDM symbol and up to 40 users in two OFDM symbols at a subcarrier spacing of 30 KHz, demonstrating significant improvements in latency, resource utilization, throughput, and power efficiency compared to existing solutions
Figure 2 illustrates PDCCH Naïve Architecture, The PDCCH Naïve Architecture represents a straightforward and unoptimized implementation of the Physical Downlink Control Channel (PDCCH) in 5G systems. It uses separate, standalone blocks for critical functions like CRC attachment and Polar coding. Each operation is performed independently, resulting in a sequential and linear flow. While this approach ensures functional correctness, it lacks integration and resource-sharing, leading to higher latency, greater resource consumption, and lower efficiency. The rate matching and scrambling processes are implemented with limited flexibility, and data bus adjustments are not dynamically optimized for different stages.

This architecture serves as a baseline model, often used for educational purposes or initial prototyping, to verify the correctness of PDCCH functionalities. However, it struggles to meet the high-performance demands of 5G, such as low latency and high throughput, due to its lack of modularity and integration. The naïve implementation handles bits sequentially in various processes like rate matching, scrambling, and modulation, leading to high latency. Its resource-heavy design limits scalability, making it less suitable for large-scale or real-time 5G applications.
The proposed PDCCH Novel Architecture introduces significant enhancements over the baseline PDCCH Naive Architecture for implementing the Physical Downlink Control Channel (PDCCH) in 5G systems. The Novel Architecture employs a carefully optimized data bus design to accommodate varying requirements of sub-blocks, allowing efficient data handling for Polar encoding (128 bits) and subsequent procedures like bit selection (108 bits). This modular and integrated approach innovates rate matching procedure using Sub-Block Interleaver (SBI), SBI-BS interconnect, and optimized bit selection Intellectual Properties (IPs), resulting in a substantial reduction in computational overhead, latency, and resource utilization.

In contrast, the PDCCH Naive Architecture represents a linear implementation of 3GPP-specified procedures with separate functional blocks, including CRC attachment and Polar coding without inter-block optimization. This approach lacks the flexibility and scalability of the Novel Architecture, relying on fixed-width data buses and independent blocks for each processing stage. Consequently, it demonstrates significantly higher end-to-end latency and resource usage, with limited throughput capabilities that fall short of modern 5G requirements.

The Novel Architecture's use of integrated IPs such as the Golden Sequence Generator and Scrambler further streamline processing, ensuring a 98.54% reduction in latency and a 98.66% increase in throughput compared to the Naive Architecture. The resource utilization for essential components like flip-flops and Look-Up Tables (LUTs) is also reduced by 29.38% and 25.90%, respectively. While there is a marginal 20% increase in DSP usage, this trade-off enables Novel Architecture to achieve higher processing efficiency and significant improvements in power efficiency, delivering 10 Gbps/W versus the Naive Architecture’s 0.066 Gbps/W.

The end-to-end comparison of the architecture highlights the Novel Architecture's ability to support higher data rates and lower latency, meeting 5G's stringent frame requirements. The optimized design achieves a throughput of 1.2 Gbps with a latency of just 1.46 µs, whereas the Naive Architecture is limited to 0.016 Gbps with a latency of 103 µs. Additionally, power consumption is halved, with the Novel Architecture operating at 0.12 W compared to 0.24 W for the Naive version.

Overall, Novel Architecture is a significant leap forward in hardware efficiency, scalability, and performance for PDCCH implementation in 5G systems. Its modular and optimized approach addresses the critical limitations of Naive Architecture, making it a superior choice for high-performance communication systems.

The following Table 1 represents the latency comparison between the Naive and Novel architectures for various sub-blocks in the PDCCH chain, demonstrating a significant reduction in latency (up to 98.54%) achieved by the Novel Architecture

Table 1: Latency comparison of the naive implementation and proposed implementation for the PDCCH sub-blocks in Figure 1
IP SBI Bit Selection Golden Sequence Scrambler QAM Modulation End-to-End Latency
Latency (Naive) 103 µs 35.45 µs 51.74 µs 0.37 µs 17.6 µs 103 µs
Latency (Optimized) 0.91 µs 0.19 µs + 60 ns = 0.25 µs 0.81 µs 0.18 µs 0.5 µs 1.46 µs
Reduction in Latency 99.11% 99.29% 98.43% 51.35% 97.15% 98.54%

The following Table 2 showcases the hardware resource utilization comparison, highlighting reductions in BRAM usage (100%), flip-flops (29.38%), and LUTs (25.90%) in the Novel Architecture, with a slight increase (20%) in DSP usage to support optimized processing.
Table 2: Resource utilization comparison of the naive (denoted by ‘N’) and proposed (denoted by ‘P’) implementations for the PDCCH sub-blocks in Figure 1
IP BRAM 18K DSP48E Flip Flop LUT
SBI (Naive) 0 1 1563 15706
SBI (Proposed) 0 5 1809 4203
Bit Selection (Naive) 3 1 2006 2721
Bit Selection (Proposed) 0 0 1200 4621
Golden Sequence (Naive) 3 1 905 898
Golden Sequence (Proposed) 0 1 285 1362
Scrambler (Naive) 0 1 26 241
Scrambler (Proposed) 0 0 5 173
Modulation (Naive) 0 1 336 2618
Modulation (Proposed) 0 0 116 6079
Overall Naive 6 5 4836 22184
Overall Proposed 0 6 3415 16438
% Reduction/Increment 100% ↓ 20% ↑ 29.38% ↓ 25.90% ↓
IP BRAM 18K DSP48E Flip Flop LUT
The following Table 3 provides an end-to-end comparison of latency, throughput, resource utilization, power consumption, and power efficiency, showing the Novel Architecture's superiority with a 98.54% reduction in latency, a 98.66% increase in throughput, and a 50% reduction in power consumption, leading to a 99.34% improvement in power efficiency.
Table 3: End-To-End Comparison of Latency
Metric Optimized (Novel) Naive Improvement
Latency 1.46 µs 103 µs 98.54% ↓
Throughput 1.2 Gbps 0.016 Gbps 98.66% ↑
Resource Utilization 30705 36504 15.88% ↓
Power Consumption 0.12 W 0.24 W 50% ↓
Power Efficiency (PE) 10 Gbps/W 0.066 Gbps/W 99.34% ↑

From the above, the proposed PDCCH Novel Architecture demonstrates significant advancements over the Naive Architecture by integrating optimized modular designs, advanced rate matching procedures, and resource-efficient implementations, achieving superior latency, throughput, and power efficiency metrics. These enhancements align with 5G-NR requirements, providing a scalable and high-performance solution while addressing the inherent limitations of Naive Architecture. The optimized architecture underscores its technical superiority and innovative design, fulfilling the stringent demands of modern communication systems.  
, C , Claims:1. An architecture for implementing a 5G-NR Physical Downlink Control Channel (PDCCH) transmitter chain on an FPGA, comprising:
a sub-block interleaver IP configured to perform sub-block interleaving of encoded bits based on predefined parameters, including sub-block size (B), maximum bit capacity (kmax), and data width (a), consuming 1334 LUTs, 4 DSPs, and 1559 registers, where the encoded bits are divided into 32 sub-blocks for interleaving according to a predefined pattern stored in a look-up table;
a data bus configuration designed to accommodate the varying requirements of different PDCCH procedures, including a 128-bit width for polar encoding and sub-block interleaving, and a 108-bit width for subsequent procedures;
an SBI-BS interconnect IP and a bit selection IP configured to handle bit selection, wherein the SBI-BS interconnect IP adjusts data width from 128 bits at the input to 108 bits at the output for optimal processing, enabling compliance with 5G frame boundaries while minimizing resource utilization, and the bit selection IP performs bit selection operations, including shortening, puncturing, and repetition, consuming 1797 LUTs and 2203 registers;
a Golden sequence generator IP and a scrambler IP for generating a pseudo-random binary scrambling sequence and scrambling the payload bits of Downlink Control Information (DCI), wherein the scrambler consumes 356 LUTs and 671 registers, and the Golden sequence generator consumes 626 LUTs and 531 registers;
a CRC attachment and Polar coding IP integrating CRC attachment and Polar coding into a single unit, wherein two functional blocks, a polar configuration block and a parameter handler, manage parameters for the polar code and CRC initialization; and
a modulation IP configured to map scrambled bits into symbols using Quadrature Phase Shift Keying (QPSK) modulation, grouping 18 symbols into bursts of 576 bits while considering the Digital-to-Analog Converter (DAC) resolution, consuming 260 LUTs and 490 registers;
wherein the architecture achieves an iterative latency of 1.46 μs, optimizes hardware resource utilization with 1.98% FPGA usage on the RFSoC ZCU111 evaluation board, supports high throughput of 1.2 Gbps, and achieves power efficiency of 10 Gbps/W at 100 MHz, meeting the 5G-NR frame requirements.
2. The architecture as claimed in claim 1, wherein the architecture is prototyped with 3GPP-compliant procedures, including polar configuration, sub-block interleaving (SBI), SBI-BS interconnect, bit selection, scrambling, Golden sequence generation, and Quadrature Phase Shift Keying (QPSK) modulation.
3. The architecture as claimed in claim 1, wherein the data bus configuration allows processing in integer multiples of 128 bits for polar encoding and SBI, while subsequent procedures in the PDCCH chain process 108 bits per clock cycle to handle data efficiently and reduce processing complexity.
4. The architecture as claimed in claim 1, wherein the bit selection process includes shortening, puncturing, and repetition operations, with a separate SBI-BS interconnect IP adjusting the data width for efficient handling of data bursts and sequential processing.
5. The architecture as claimed in claim 1, wherein a comprehensive three-tier testing protocol ensures 3GPP compliance, including individual IP testing in Vivado HLS, standalone testing of exported IPs in an Integrated Development Environment (IDE), and integrated end-to-end testing of the PDCCH chain in the IDE to evaluate latency, resource usage, throughput, power consumption, and power efficiency.
6. The architecture as claimed in claim 1, wherein the performance results demonstrate improvements in latency, resource utilization, throughput, and power efficiency compared to existing solutions, supporting multiplexing of DCI for up to 20 users with one OFDM symbol or up to 40 users with two OFDM symbols at a subcarrier spacing of 30 KHz.
7. A method for implementing a 5G-NR Physical Downlink Control Channel (PDCCH) transmitter chain on an FPGA, the method comprising:
dividing encoded bits into 32 sub-blocks and performing interleaving using a Sub-Block Interleaver (SBI) IP, wherein the interleaving pattern is pre-stored in a look-up table, and the SBI IP is configured to interleave the bits based on parameters including sub-block size (B), maximum bit capacity (kmax), and data width (a);
establishing input and output data ports to facilitate data flow, loading the interleaving pattern, setting up configuration parameters, initializing a storage array for holding sub-block data, and calculating essential data parameters for efficient hardware data handling.
8. The method as claimed in claim 7, further comprising performing bit selection and adjusting the data width from 128 bits to 108 bits using a bit selection IP and an SBI-BS interconnect IP, wherein the SBI-BS interconnect IP interfaces with the output of the SBI IP, adjusting data width, and the bit selection IP performs bit selection operations, including shortening, puncturing, and repetition, to optimize resource utilization and reduce complexity in subsequent PDCCH chain operations.
9. The method as claimed in claim 7, further comprising generating a scrambling sequence using a Golden Sequence Generator IP based on a physical layer cell identity or a User Equipment (UE)-specific scrambling identity, along with a Radio Network Temporary Identifier (RNTI), and scrambling payload bits of Downlink Control Information (DCI) with a Scrambler IP configured to apply the generated pseudo-random sequence.
10. The method as claimed in claim 7, further comprising attaching a Cyclic Redundancy Check (CRC) and encoding the bits using Polar Coding, wherein the CRC attachment and Polar coding are integrated into a single IP configured by a polar configuration block and a parameter handler, both configured to manage the polar code and CRC initialization in accordance with control signals.
11. The method as claimed in claim 7, further comprising modulating the scrambled bits into symbols using Quadrature Phase Shift Keying (QPSK) modulation, wherein each 2 bits are mapped into a symbol and grouped into bursts of 576 bits to improve transmission efficiency.
12. The method as claimed in claim 7, further comprising optimizing iterative latency and hardware resource utilization to meet 5G frame timing requirements, wherein the PDCCH transmitter chain achieves a latency of 1.46 μs, a throughput of 1.2 Gbps, and a power efficiency of 10 Gbps/W at 100 MHz on the FPGA platform with a resource utilization of 1.98%.
13. The method as claimed in claim 7, further comprising performing a three-tier testing protocol for 3GPP compliance, including:
testing each IP, including the Sub-Block Interleaver, SBI-BS interconnect, Bit Selection, Golden Sequence Generator, Scrambler, and Modulation IPs, using Vivado High-Level Synthesis (HLS) tools to verify functionality;
conducting standalone testing of each IP in an Integrated Development Environment (IDE);
evaluating latency, throughput, and resource consumption;
performing integrated end-to-end testing of the PDCCH transmitter chain in the IDE to assess cumulative latency, resource utilization, throughput, power efficiency, and 5G frame compliance.
14. The method as claimed in claim 7, wherein the iterative latency of 1.46 μs enables the PDCCH transmitter chain to dynamically support multiplexing of Downlink Control Information (DCI) to support multiple users across various configurations of Orthogonal Frequency Division Multiplexing (OFDM) symbols, with the flexibility to adapt to different subcarrier spacings as specified by 5G frame requirements