Description:[001] The invention, in general, relates to the technology field of integrated circuits, designs, system and method. More particularly, the present invention relates to a Novel Design of FGMOS Based XOR/XNOR Logic Cell for ultra–Low Power Low Voltage Applications.
BACKGROUND OF THE INVENTION
[002] The following description provides the information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[003] XOR/XNOR cell is an essential block in numerous applications such as full adder, arithmetic logic unit (ALU), multipliers, phase lock loop (PLL), calculators, comparator, phase detector, graphical processing unit (GPU) and many more. Various logic styles such as CMOS, pass transistor logic (PTL), complementary pass-transistor logic (CPL), transmission gate (TG) and hybrid logic style are practiced for the designing of XOR/XNOR cell to enhance the circuit design metrics. These approaches come under the conventional design methodologies. When channel length reaches the nanometre regime, conventional design approaches fail. After a certain point, the miniaturisation of device dimensions can lead to several significant difficulties and issues with circuit design. The main issues with deep sub-micron/nano CMOS technology include increased leakage currents, short channel and parasitic effects, increased transistor parameter variability, and reliability.
[004] Therefore, this led to exploration of different advanced technologies having more scaling capabilities along with improved performance. There are many non-conventional techniques are available in literature like bulk-driven (BD), floating-gate (FGMOS) technology, silicon nanowire transistors, single electron transistor (SET), FinFet and carbon nanotube field effect transistors (CNTFET). Among these technologies, FGMOS technology is quite famous because of its threshold tuning and multiple input features. FGMOS is advantageous to use as an active building block for applications involving digital signal processing because of its multiple input features. These techniques have proven very powerful to reduce the power requirement of the circuit without degrading the performance of the circuit.
[005] Accordingly, on the basis of aforesaid facts, there remains a need in the prior art to provide a Novel Design of FGMOS Based XOR/XNOR Logic Cell for ultra–Low Power Low Voltage Applications, therefore, it would be useful and desirable to have a system, method, and interface to meet the above-mentioned needs.
SUMMARY OF THE PRESENT INVENTION
[006] In view of the foregoing disadvantages inherent in the known types of conventional methods and techniques, are now present in the prior art, the present invention provides a Novel Design of FGMOS Based XOR/XNOR Logic Cell for ultra–Low Power Low Voltage Applications, which has all the advantages of the prior art and none of the disadvantages.
[007] The novel design of an XOR/XNOR cell using FGMOS (Floating-Gate MOS) is motivated by several factors and aimed to address specific problems of traditional CMOS technology. Traditional XOR/XNOR cells in digital circuit design involve complex combinations of transistors, leading to increased circuit complexity. By utilising the special characteristics of FGMOS transistors, the revolutionary design for FGMOS intends to reduce the complexity of the circuit construction. Modern electrical equipment must carefully consider their power consumption. In comparison to conventional implementations, the application of FGMOS technology in XOR/XNOR cell design has the potential to reduce power consumption. This innovative method takes advantage of FGMOS devices' strengths to reduce power dissipation, making it appropriate for low-power applications.
[008] A number of digital systems, including arithmetic units and error detection circuits, rely on the fundamental XOR/XNOR operations. The unique design aims to improve the performance of these procedures by utilising FGMOS technology. In order to conduct XOR/XNOR operations more quickly and accurately, FGMOS devices offer higher linearity and enhanced voltage transfer properties. Compact and effective circuit designs are becoming important as demand for smaller, more integrated electronic devices rises. Better integration and miniaturisation are possible with the design of an XOR/XNOR cell made with FGMOS technology. The FGMOS-based cell is more space-efficient and paves the path for smaller, more portable electronic gadgets thanks to its lower size and simplified construction.
[009] The proposed design of XOR/XNOR logic cell is depicted in Figure.1. It consists of two NMOS pass transistors, one NMOS, one PMOS and one p-type FGMOS transistor. The inputs of FGMOS are capacitively coupled using capacitor C1 and C2. Eq. 1 can be used to determine the voltage at the FGMOS input.

Comparing the suggested XOR/XNOR logic cell implementation to the traditional CMOS-based design, much less transistors are needed. The performance of several circuits, including adders, comparators, parity checkers, multipliers, and phase detectors based on XOR/XNOR logic cell, can be significantly improved as a result of its widespread use.
[010] In this respect, before explaining at least one object of the invention in detail, it is to be understood that the invention is not limited in its application to the details of set of rules and to the arrangements of the various models set forth in the following description or illustrated in the drawings. The invention is capable of other objects and of being practiced and carried out in various ways, according to the need of that industry. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting.
[011] These together with other objects of the invention, along with the various features of novelty which characterize the invention, are pointed out with particularity in the disclosure. For a better understanding of the invention, its operating advantages and the specific objects attained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated preferred embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[012] The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein:
[013] FIG. 1, demonstrates a Circuit schematic of proposed design, in accordance with an embodiment of the present invention.
[014] FIG. 2, illustrates a schematic representation of HSPICE simulation results for FGMOS-based XOR/XNOR logic cell, in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[015] While the present invention is described herein by way of example using embodiments and illustrative drawings, those skilled in the art will recognize that the invention is not limited to the embodiments of drawing or drawings described and are not intended to represent the scale of the various components. Further, some components that may form a part of the invention may not be illustrated in certain figures, for ease of illustration, and such omissions do not limit the embodiments outlined in any way. It should be understood that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims. As used throughout this description, the word "may" is used in a permissive sense (i.e. meaning having the potential to), rather than the mandatory sense, (i.e. meaning must). Further, the words "a" or "an" mean "at least one” and the word “plurality” means “one or more” unless otherwise mentioned. Furthermore, the terminology and phraseology used herein is solely used for descriptive purposes and should not be construed as limiting in scope. Language such as "including," "comprising," "having," "containing," or "involving," and variations thereof, is intended to be broad and encompass the subject matter listed thereafter, equivalents, and additional subject matter not recited, and is not intended to exclude other additives, components, integers or steps. Likewise, the term "comprising" is considered synonymous with the terms "including" or "containing" for applicable legal purposes. Any discussion of documents, acts, materials, devices, articles and the like is included in the specification solely for the purpose of providing a context for the present invention. It is not suggested or represented that any or all of these matters form part of the prior art base or are common general knowledge in the field relevant to the present invention.
[016] In this disclosure, whenever a composition or an element or a group of elements is preceded with the transitional phrase “comprising”, it is understood that we also contemplate the same composition, element or group of elements with transitional phrases “consisting of”, “consisting”, “selected from the group of consisting of, “including”, or “is” preceding the recitation of the composition, element or group of elements and vice versa.
[017] The present invention is described hereinafter by various embodiments with reference to the accompanying drawings, wherein reference numerals used in the accompanying drawing correspond to the like elements throughout the description. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiment set forth herein. Rather, the embodiment is provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the following detailed description, numeric values and ranges are provided for various aspects of the implementations described. These values and ranges are to be treated as examples only and are not intended to limit the scope of the claims. In addition, a number of materials are identified as suitable for various facets of the implementations. These materials are to be treated as exemplary and are not intended to limit the scope of the invention.
[018] In accordance with an embodiment for the present invention, the working of the proposed “FGMOS-XOR/XNOR” logic cell for the four possible input logic combinations (00, 01, 10, and 11). The pass transistors MN1 and MN2 are both in the ON state for the "11" input, allowing the logic inputs to flow through to the output node. Equation (1) is used to compute the floating gate (FG) voltage of FGMOS. The output at the XNOR node is equal to logic "1" since the FGMOS transistor will be in the off state for this positive voltage (VFG). Both of the pass transistors MN1 and MN be in the off state for the input logic combination "00".
[019] The present invention pertains to an analysis of the resistance of welded parts by the electrical resistance process as disclosed in figure.1, the present invention comprising of applying input signals to the input interface, utilizing the control circuit to selectively set and reset the charges on the floating gates of the FGMOS transistors to execute XOR and XNOR logic functions, and obtaining XOR and XNOR logic results at the output interface, suitable for ultra-low power low voltage applications. The control circuit employs a charge-sharing technique to selectively set and reset the charges on the floating gates of the FGMOS transistors to achieve XOR and XNOR logic operations. The FGMOS-based logic cell further comprising a power management unit for adjusting the voltage supply to maintain ultra-low power consumption, making it suitable for low voltage applications.
[020] In accordance with an embodiment for the present invention, On the other hand, the FGMOS transistor in the ON state since VFG=0. As a result of the XNOR node being connected to Vdd in this instance, the output node voltage changes to "1". As a result, the circuit proposed in figure.1, successfully implements the XNOR gate's Boolean statement. The parallel pairing of pass transistors MN1 and MN2 enables the logic "0" to pass through to the XNOR node when one of the inputs is at logic "1" and the other is at logic "0." In this scenario, the value of VFG is positive enough to OFF the FGMOS transistor. Consequently, the XNOR node maintain logic "0". To achieve XOR output, a static CMOS inverter is used in this design.
[021] In accordance with an embodiment for the present invention, Using HSPICE software and a 0.7 V supply voltage, the proposed FGMOS-based XOR/XNOR logic cell simulated at the 22nm technology node. The simulation waveforms for the XOR and XNOR logic cell's four possible input configurations (00, 01, 10, and 11) are shown in Figure.2. It is noted that the full output voltage swing is not attained at the XNOR node when the input is in the logic "11" state. This restriction results from the NMOS pass transistor's inadequacy as the pullup device. The same observation is depicted in Figure 2, where a weak logic "1" is obtained as the output at XNOR node for the input combination '11'. In order to produce a full swing output at the XOR node, a static CMOS inverter is used in the XOR/XNOR logic cell. The static CMOS inverter arrangement circumvents the restriction of generating a full output voltage swing for the input logic "11", unlike the XNOR logic stated above. When using a static CMOS inverter, the output voltage can be brought to the appropriate high and low voltage levels, ensuring reliable signal transmission and better circuit performance.
[022] In accordance with an embodiment for the present invention, to evaluate the circuit's performance, several design parameters are calculated based on the simulation results, including the “propagation delay (tp), power requirement (pwr), PDP (power-delay product), and EDP (energy-delay product)”. Table. I present the simulation results. These results imply that the proposed design of an XOR/XNOR logic cell based on FGMOS yields very excellent results for all design parameters. The XOR/XNOR logic cell's transistor count and power are reduced as a result of the inclusion of FGMOS.

[023] The stated XOR/XNOR logic cell's simulation results are contrasted with a number of recently published XOR/XNOR designs. Table II compares the proposed design to these current designs in a comparable manner. Table II analysis reveals that, when compared to the other designs, the proposed FGMOS-based XOR/XNOR logic cell exhibits the least propagation delay. Additionally, the power consumption of the reported design is remarkably low—it is only 4.0652 nW. When compared to the various XOR/XNOR cells tabulated in Table II, the reported design also shows a notable improvement in terms of power-delay product (PDP) and energy-delay product (EDP).

Based on the observations from Table II, it is notable that Uma's design [9] stands out as the most efficient in terms of power consumption. In this particular design, the author has implemented XOR logic exclusively, resulting in a reduced number of transistors being required. Uma's design is extremely power-efficient due to the decrease in transistor count, which immediately lowers power requirements. XOR and XNOR logic can be implemented using the proposed arrangement, but with a little increase in power consumption. It is crucial to remember, nevertheless, that the proposed design outperforms the other designs taken into account in the research in terms of speed. The proposed design performs better overall in terms of speed and efficiency than the other designs, despite the modest increase in power usage. Even with a modest trade-off in power consumption, this makes it an appealing option for applications where high speed and varied logic capabilities are desired.
[024] In accordance with an embodiment for the present invention, the novel design of FGMOS-based XOR/XNOR logic cell makes use of Floating Gate MOS (FGMOS) technology, which provides distinctive benefits like reduced transistor count and increased power efficiency. The proposed approach ensures a full swing output at the XOR node, enhancing circuit performance and ensuring reliable signal transmission, in contrast to FGMOS-based XOR design. Comparing the presented design to existing XOR/XNOR gate designs, propagation time is significantly reduced, resulting in speedier operation. Meticulous optimisation and cutting-edge design approaches are used to achieve this. The suggested design provides versatility and flexibility in a variety of circuit applications, meeting the demand for both XOR and XNOR logic capabilities. The simulation results show that in terms of Power-Delay Product (PDP) and Energy-Delay Product (EDP), the suggested design of the FGMOS-based XOR/XNOR logic cell performs better than alternative XOR/XNOR gate designs.
[025] Furthermore, the present invention provides the proposed design which presents an innovative approach to address the drawbacks and enhance existing solutions for XOR and XNOR gates using FGMOS technology. The proposed design of FGMOS-based XOR/XNOR logic cell is simulated using HSPICE software at 22 nm channel length. This cutting-edge FGMOS-based XOR/XNOR logic cell design offers very little delay (12.739 ps) and uses a small amount of power (4.0652nW). The proposed design provides a strong substitute that addresses the drawbacks of earlier approaches and adds improved functionality for implementing XOR and XNOR logic. Future circuit designs look promise because to its creative methodology, significant speed increases, and optimised power consumption.
[026] FGMOS transistors, each equipped with a floating gate. FGMOS transistors are known for their ability to retain a charge on the floating gate, making them suitable for use in memory and logic circuits. The XOR/XNOR logic cell incorporates a sophisticated control circuit responsible for selectively manipulating the charges stored on the floating gates of the FGMOS transistors. This control circuit is programmed to implement both XOR and XNOR logic functions efficiently. An input interface allows the XOR/XNOR logic cell to receive external input signals. These input signals are essential for the logic cell to process and perform logical operations. The output interface is responsible for delivering the results of the XOR and XNOR logic operations. This interface provides the logical output based on the inputs received. The XOR/XNOR logic cell is optimized for ultra-low power and low-voltage applications. To achieve this, it is equipped with voltage supplies designed to support these requirements while ensuring energy efficiency.
[027] The control circuit skilfully manages the charges on the floating gates of the FGMOS transistors, selectively setting and resetting them according to the logic operations being performed. This process is carried out through a charge-sharing technique, ensuring efficiency in both XOR and XNOR logic operations. The XOR/XNOR logic cell is meticulously designed to operate at ultra-low power and low voltage levels, ensuring minimal energy consumption. This feature makes it ideal for battery-powered devices and other applications with strict power constraints. The XOR/XNOR logic cell is highly adaptable and can be seamlessly integrated into integrated circuits (ICs) or semiconductor chips. This integration enhances its utility in a wide range of applications where ultra-low power and low-voltage operation are paramount.
[028] There is an ever-growing demand for energy-efficient and low-power logic cells. These cells play a crucial role in various applications, including portable electronics, IoT devices, and other battery-powered systems. This detailed description delves into a novel design of an XOR/XNOR logic cell based on Floating Gate Metal-Oxide-Semiconductor (FGMOS) transistors, specifically tailored for ultra-low power and low-voltage scenarios. The novel design of an FGMOS-based XOR/XNOR logic cell offers a promising solution for ultra-low power and low-voltage applications. Its efficiency, charge manipulation capabilities, and seamless integration into ICs and semiconductor chips make it a valuable addition to the field of integrated circuit design. This detailed description provides insight into the components and operation of this logic cell, highlighting its potential to revolutionize low-power logic in various electronic systems.
[029] It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-discussed embodiments may be used in combination with each other. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description.
[030] The benefits and advantages which may be provided by the present invention have been described above with regard to specific embodiments. These benefits and advantages, and any elements or limitations that may cause them to occur or to become more pronounced are not to be construed as critical, required, or essential features of any or all of the embodiments.
[031] While the present invention has been described with reference to particular embodiments, it should be understood that the embodiments are illustrative and that the scope of the invention is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described above are possible. It is contemplated that these variations, modifications, additions and improvements fall within the scope of the invention.
, Claims:

1. A novel FGMOS-based XOR/XNOR logic cell for ultra-low power low voltage
applications, comprising:

a.    
A plurality of
FGMOS transistors, each having a floating gate;

b.    
A control
circuit for selectively controlling the charges on the floating gates of the
FGMOS transistors to implement XOR and XNOR logic functions;

c.    
An input
interface for receiving input signals;

d.    
An output interface
for providing XOR and XNOR logic results; and

e.    
A voltage supplies
suitable for ultra-low power low voltage applications.

2. The FGMOS-based logic
cell as claimed in claim 1, wherein the control circuit employs a
charge-sharing technique to selectively set and reset the charges on the
floating gates of the FGMOS transistors to achieve XOR and XNOR logic
operations.

3. The FGMOS-based logic
cell as claimed in claim 1, further comprising a power management unit for
adjusting the voltage supply to maintain ultra-low power consumption, making it
suitable for low voltage applications.

4. The FGMOS-based logic
cell as claimed in claim 1, wherein the FGMOS transistors are implemented with
reduced sub-threshold slopes to enable operation at ultra-low power and low
voltage levels.

5. The FGMOS-based logic
cell as claimed in claim 1, integrated into an integrated circuit (IC) or
semiconductor chip suitable for applications in which ultra-low power and low
voltage operation is essential.

6. A method for implementing
XOR and XNOR logic operations in ultra-low power low voltage applications using
the novel FGMOS-based logic cell as described in claim 1, comprising the steps
of:

a.    
Applying input
signals to the input interface;

b.    
Utilizing the
control circuit to selectively set and reset the charges on the floating gates
of the FGMOS transistors to execute XOR and XNOR logic functions; and

c.    
Obtaining XOR
and XNOR logic results at the output interface, suitable for ultra-low power
low voltage applications.