The CMFB circuit averages both differential output voltages to produce a common mode
@ voltage VCM. The voltage VCM is then compared to a desired reference common-mode
voltage VCMR. A difference between VCM and VCMR is amplified and this error
voltage is used to change the common mode bias current. If the common-mode voltage
VCM is continuously compared with a constant reference voltage VCMR, then the
common mode feedback circuit is referred as a continuous time common mode feedback
circuit.
FIGURE 1 illustrates a conventional continuous time common mode feedback circuit
100. The circuit 100 includes four identical transistors 102, 104, 106, 108 and two
transistors 110 and 112. The common mode feedback circuit 100 averages two
differential signals VCMP and VCMM that are supplied by differential outputs OUTP
and OUTM of a main differential amplifier and compares the average to the reference
common mode voltage VCMR by using the four identical transistors 102, 104, 106 and
108 configured into two differential pairs.
Currents through the transistors 102, 104, 106 and 108 are given by the following
equations:
Where IDPO is the current through the transistor 102, IDPl is the current through the
transistor 104, IDP2 is the current through the transistor 106, IDP3 is the current through
the transistor 108 and IB is the current flowing to the transistors 102,104,106 and 108.
The current IDPO equals IDP2 and IDPl equals IDP3. Currents through the transistors
110 and 112 are equal to IB. Now if the differential signals VCMP and VCMM are
CONTINUOUS TIME COMMON MODE FEEDBACK CIRCUIT
Field of the Invention
The present invention relates to common mode feedback circuit and more specifically to
a low voltage continuous time common mode feedback circuit, for low voltage
operational amplifiers, providing a good linearity, a wide bandwidth and a low systematic
offset.
Background of the Invention
The market and the need to develop efficient portable electronic equipment have pushed
the industry to produce circuit designs with very low voltage (LV) power supply and also
often constrained to low power (LP) consumption. The basic problem with using
conventional analog differential and/or operational amplifiers in fine-line CMOS
technology is that the threshold voltage and drain source saturation voltage do not scale
down at the same rate as the supply voltage.
An operational amplifier, the most omnipresent analog system building block, has had to
adapt in order to function in today's low voltage, high noise environment. Therefore,
fully differential design principles have been applied to the operational amplifiers.
However, when a differential amplifier is in a feedback configuration, a high differential
gain of a fully differential amplifier stabilizes differential-mode signals within the
amplifier, but common-mode signals can float. An extra circuitry, called a common mode
feedback (CMFB) circuit, is required to increase a common mode loop gain of the
amplifier so that the common-mode signals are stabilized. The CMFB circuit implements
a negative feedback loop that must be compensated properly to minimize loop settling
time and to maintain stability. Often, designing the CMFB circuit is more challenging
than the actual operational amplifier's design due to the difficulty in properly
compensating the CMFB circuit.
averaged with VCM which is greater than VCMR, currents through the transistors 102
and 108, IDPO and IDP3 will decrease causing currents IDPl and IDP2 through
transistors 104 and 106 to increase. The increased current in the diode connected
transistor 110 causes a voltage VCNTRL to increase. The increase in the voltage
VCNTRL is applied to the gate of the transistors which are part of the operational
amplifier output stage current sink. The current being sunk into the drain of those
transistors will increase, causing a reduction in the voltage of nodes VCMP and VCMM,
thus reducing the common mode output voltage VCM. The same analysis can be used to
describe the behavior of the CMFB circuit when the differential signals VCMP and
VCMM are averaged with VCM smaller than VCMR.
However, this conventional method cannot be used in low voltage power supply
environment without severely limiting an output voltage swing (VCMP - VCMM) of the
operational amplifier and the non-linear behavior of the differential pairs of the circuit
100.
Some other conventional common mode feedback schemes are also used. In one method,
the common mode voltage VCM is periodically refreshed to the common mode reference
voltage VCMR, This circuit is well suited for low voltage applications to increase the
output voltage swing. However, as the circuit is based on switched capacitor technique,
additional switching noise is introduced to output signals.
Another conventional common mode feedback scheme is designed with resistors. The
amplifiers have problems of resistor tolerances and the large value resistors degrade the
performance of the amplifiers by limiting the voltage swing, thereby forcing operation at
higher supply voltages where the limited voltage swing is not a disadvantage.
Therefore, there is a need of a novel continuous time common mode feedback circuit for
low voltage operational amplifiers for providing a good linearity, a wide bandwidth and a
low systematic offset.
I ~ mode feedback module, for low voltage operational amplifiers, having a good linearity, a
wide bandwidth and a low systematic offset.
To achieve the aforementioned objective, the present invention provides a low voltage
continuous time common mode feedback module comprising:
an initializing module receiving a first differential input voltage
(VCMP) and a second differential input voltage (VCMM) for providing a
direct current (DC) bias; and
a controlling module receiving the first differential input voltage
(VCMP) and the second differential input voltage (VCMM) for
controlling a common mode voltage.
Further the present invention provides an operational amplifier comprising:
one or more differential amplifier stages for generating differential
output voltages; and
a low voltage continuous time common mode feedback module
operatively coupled to the one or more differential amplifier stages for
receiving a first differential input voltage (VCMP) and a second
differential input voltage (VCMM) to provide a common mode feedback
voltage.
Further the present invention provides a method for generating a common mode control
voltage in a low voltage continuous time common mode feedback module comprising:
initializing a controlling module and an initializing module by a supply
voltage and a ground voltage;
applying a first differential voltage at a bulk terminal of a second transistor
and at a gate terminal of an eighth transistor;
applying a second differential voltage at a bulk terminal of a third
transistor and at a gate terminal of a ninth transistor;
applying a common mode reference voltage at a bulk terminal of a fourth
transistor and at a gate terminal of a tenth transistor;
applying a bias current at gate terminals of a first transistor and a seventh
transistor;
applying an input terminal voltage at gate terminals of said second
transistor, said third transistor and said fourth transistor; and
generating the common mode control voltage.
Brief Description of Drawings
The aforementioned aspects and other features of the present invention will be explained
in the following description, taken in conjunction with the accompanying drawings,
wherein:
FIGURE 1 illustrates a circuit diagram of a conventional common mode feed back
circuit.
FIGURE 2 illustrates a block diagram of a common mode feedback module according to
the present invention.
FIGURE 3 illustrates a circuit diagram of a common mode feed back module according
to the present invention.
FIGURE 4 illustrates a block diagram of an operational amplifier according to the
present invention.
FIGURE 5 illustrates a schematic circuit diagram of an operational amplifier according
to the present invention.
FIGURE 6 illustrates a flow diagram of a method for generating a common mode control
voltage according to the present invention.
Detailed description of the invention
The preferred embodiments of the present invention will be described in detail with
reference to the accompanying drawings. However, the present invention is not limited to
the preferred embodiments. The present invention can be modified in various forms. The
preferred embodiments of the present invention are only provided to explain more clearly
the present invention to the ordinarily skilled in the art of the present invention. In the
accompanying drawings, like reference numerals are used to indicate like components.
FIGURE 2 illustrates a block diagram of a low voltage continuous time common mode
feed back (CMFB) module 200 according to the present invention. The common mode
feedback module 200 includes a controlling module 202 and an initializing module 204.
The controlling module 202 and the initializing module 204 receive a first differential
input voltage VCMP and a second differentidl input voltage VCMM for generating a
common mode control voltage VCNTRL.
FIGURE 3 illustrates a circuit diagram of a low voltage continuous time common mode
feed back (CMFB) module 300 according to an embodiment of the present invention. The
I ~ CMFB module 300 includes a common mode detector and an amplifier for computing
and amplifying a difference of a common mode reference voltage VCM and a common
mode voltage of inputs VCMP and VCMM.
The CMFB module 300 includes a controlling module 202 and an initializing module
204. The controlling module 202 and the initializing module 204 are parallel CMFB
loops. The controlling module 202 is a main CMFB loop and the initializing module 204
is an auxiliary CMFB loop. Both loops work at the same time. The controlling module
202 and the initializing module 204 receives a first differential input voltage VCMP, a
second differential input voltage VCMM, supplied by differential outputs OUTP and
OUTM of a main differential amplifier (illustrated in FIGURE 3). Both CMFB
amplifiers 202 and 204 are low gain amplifiers in order to provide operation as linear as
possible over the entire differential output operating range, OUTP to OUTM, of the
main differential amplifier.
The controlling module 202 includes a first transistor 306, a second transistor 308, a third
transistor 310, a fourth transistor 312, a fifth transistor 314 and a sixth transistor 316.
The first transistor 306 provides a bias current IPBIAS to the controlling module 202. A
source terminal and a bulk terminal of the first transistor 306 are connected to a supply
voltage AVDD, a drain terminal is connected to a first node N1 and a gate terminal
receives the bias current IPBIAS. The second transistor 308 receives the first differential
input voltage VCMP. The second transistor 308 has a source terminal connected to the
first node N1, a bulk terminal receiving the first differential input voltage VCMP, a drain
terminal connected to a second node N2 and a gate terminal connected to an input
terminal voltage V1. The third transistor 310 has a source terminal connected to the first
node N1, a bulk terminal receiving the second differential input voltage VCMM, a drain
terminal connected to the second node N2 and a gate tenninal connected to the input
terminal voltage V1. The fourth transistor 312 has a source terminal connected to the first
node N1, a bulk terminal receiving the common mode reference voltage VCM, a drain
terminal connected to an output node N5 and a gate terminal connected to the input
terminal voltage V1. The fifth transistor 314 controls a flow of current through the
second transistor 308 and the third transistor 310. A source terminal and a bulk terminal
of the fifth transistor 314 is connected to a ground voltage AGND, a drain terminal is
connected to the second node N2 and a gate terminal is connected to the drain terminal
and to a sixth node N6. The sixth transistor 316 provides a common mode control voltage
VCNTRL. A source terminal and a bulk terminal of the sixth transistor 316 are
connected to the ground voltage AGND, a drain terminal is connected to the output node
N5, a gate terminal is connected to the gate terminal of the fifth transistor 314 through the
sixth node N6.
The initializing module 204 includes a seventh transistor 318, an eighth transistor 320, a
ninth transistor 322, a tenth transistor 324, an eleventh transistor 326 and a twelfth
transistor 328.
The seventh transistor 318 provides the bias current IPBIAS to the initializing module
204. The seventh transistor 318 has a source terminal and a bulk terminal connected to
the supply voltage AVDD, a drain terminal connected to a third node N3 and a gate
terminal receiving the bias current IPBIAS. The eighth transistor 320 has a source
terminal connected to the third node N3, a bulk terminal connected to the supply voltage
AVDD, a drain terminal connected to a fourth node N4 and a gate terminal receives the
first differential input voltage VCMP. The ninth transistor 322 has a source terminal
connected to the third node N3, a bulk terminal connected to the supply voltage AVDD, a
drain terminal connected to the fourth node N4 and a gate terminal receives the second
differential input voltage VCMM. The tenth transistor 324 has a source terminal
connected to the third node N3, a bulk terminal connected to the supply voltage AVDD, a
drain terminal connected to the output node N5 and a gate terminal receives the common
mode reference voltage VCM. The eleventh transistor 326 controls a flow of current
through the eighth transistor 320 and ninth transistor 322. A source terminal and a bulk
terminal of the eleventh transistor 326 is connected to the ground voltage AGND, a drain
terminal is connected to the fourth node N4 and a gate terminal is connected to the drain
terminal and to a seventh node N7. The twelfth transistor 328 provides the common mode
I ~ control voltage VCNTRL, having a source terminal and a bulk terminal connected to the
I ~ ground voltage AGND, a drain terminal connected to the output node N5 and a gate
terminal connected to the gate terminal of the eleventh transistor 326 through the seventh
node N7.
Thus, the differential inputs VCMP, VCMM of the controlling module 202 are shorted
to the differential inputs VCMP, VCMM of the initializing module 204. An output
VCNTRL of the controlling module 202 is shorted to an output VCNTRL of the
initializing module 204.
FIGURE 4 illustrates a block diagram an operational amplifier (OPAMP) utilizing a low
voltage continuous time common mode feedback module according to the present
invention. The operational amplifier 400 includes one or more stages of differential
amplifier 402 and a common-mode feedback module 200. The one or more stages of
differential amplifier 402 are generating differential output voltages. The common-mode
feedback module 200 is connected to the one or more stages of differential amplifier 402
to receive a first differential input voltage VCMP and a second differential input voltage
VCMM for providing a common mode control voltage VCNTRL.
FIGURE 5 illustrates a schematic circuit diagram of an operational amplifier 500
according to the present invention. The operational amplifier 500 can be a folded cascode
operational amplifier device.
The operational amplifier 500 includes a first active element 502, a second active element
504, a third active element 506, a fourth active element 508, a fifth active element 510, a
sixth active element 512, a seventh active element 514, an eighth active element 516, a
ninth active element 518, a tenth active element 520, an eleventh active element 522 and
a continuous time common mode feed back (CMFB) module 200.
The first active element 502, receiving a voltage VPCAS, has a source terminal
connected to the supply voltage AMID, a drain terminal connected to a first port M1 and
a gate terminal connected to a gate terminal connected to a second port M2. The second
active element 504 has a source terminal connected to the supply voltage AVDD, a drain
terminal connected to a third port M3 and a gate terminal is connected to the gate
terminal of the first active element 502 through the second port M2. The third active
element 506 has a source terminal connected to a fourth port M4, a drain terminal
connected to the first port M1 and a gate terminal receiving a first input signal INP. The
fourth active element 508 has a source terminal connected to the fourth port M4, a drain
terminal connected to the third port M3 and a gate terminal receiving a second input
signal INM. A source terminal of the fifth active element 510 is connected to the ground
voltage AGND, a drain terminal connected to the fourth port M4 and a gate terminal
receiving a bias control signal IBIAS. The sixth active element 512 has a source terminal
connected to the first port MI, a drain terminal connected to a first output port OUTM
and a gate terminal receiving a positive bias voltage VPBIAS. The seventh active
element 514 has a source terminal connected to the third port M3, a drain terminal
connected to a second output port OUTP and a gate terminal receiving said positive bias
voltage VPBIAS. The eighth active element 516 has a source terminal connected to a
fifth port M5, a drain terminal connected to the first output port OUTM and a gate
terminal receiving a negative bias voltage VNBLAS. The ninth active element 518 has a
source terminal connected to a sixth port M6, a drain terminal connected to the second
output port OUTP and a gate terminal receiving the negative bias voltage VNBIAS. The
tenth active element 520 has a source terminal connected to the ground voltage AGND, a
drain terminal connected to the source terminal of said eighth active element 516 through
the fifth port M5 and a gate terminal connected to a seventh port M7. The eleventh active
element 522 has a source terminal connected to the ground voltage AGND, a drain
terminal connected to the source terminal of said ninth active element 518 through the
sixth port M6 and a gate terminal connected to a seventh port M7. The continuous time
common mode feedback module 200 is connected between the first output port OUTM,
the second output port OUTP and gate terminals of the tenth active element 520 and the
eleventh active element 522 through the seventh port M7.
@ The two active elements 506 and 508 forms a differential pair input stage. The active
element 510 establishes a current into the input branch of the operational amplifier 500.
The active elements 502 and 504 divert extra current into an output branch and serves as
an active load for the input stage as well. The active elements 512, 514 and 5116, 518
serve as load for the output branch of the operational amplifier 500.
Since the operational amplifier 500 is a fully differential operational amplifier, a common
mode feedback circuit will be required to set the common mode voltage of the differential
outputs. The common mode feedback module 200 is used in the operational amplifier 500
to control the common mode voltage of the operational amplifier's outputs.
In one embodiment, when the operational amplifier 500 is in a steady state condition, the
CMFB module 300 will also be in a steady state condition and current through the fifih
transistor 314 and the sixth transistor 316 of the controlling module 202 and through the
eleventh transistor 326 and the twelfth transistor 328 of the initializing module 204 of the
CMFB module 300 are matched according to their geometric ratios.
If the common mode of inputs of the CMFB module 300, i.e., (VCMP+VCMM)/2 is
equal to the common mode reference voltage VCM, then the common mode control
voltage VCNTRL will be such that it mirrors currents through the twelfth transistor 328
of the initializing module 204 to the tenth active element 520 and the eleventh active
element 522 of the operational amplifier 500 in their geometric ratios to force common
mode of outputs of the operational amplifier 500, i.e., (OUTP+OUTM)/2 will be equal
to the VCM. The fifth transistor 314 and the sixth transistor 316 of the controlling
module 202 and the eleventh transistor 326 and the twelfth transistor 328 of the
initializing module 204 have geometric ratio 2:l. The transistors 308, 310, 312 of the
controlling module 202 have equal geometric ratios and the transistors 320,322,324 of
the initializing module 204 also have equal geometric ratios. Due to their geometric ratios
the current through the transistor 314 of the controlling module 202 and through the
transistor 326 of the initializing module 204 will be 21. The currents through the
transistors 316 of the controlling module 202 and 328 of the initializing module 204 will
@ be I. So the transistors 306 of the controlling module 202 and 318 of the initializing
module 204 will be biased such that the current through them is 31. So in a steady state
condition, current through the transistors 308,310,312,320,322 and 324 will be I.
Currents through the transistors 306 and 318 have no dependency on the differential input
voltages VCMP, VCMM.
If the common mode input voltage of the CMFB module 300, i.e., (VCMP+VCMM)n is
not equal to VCM, then the current through the transistors 316 and 328 will be different
from the current through the transistors 314 and 326 respectively.
This change in current is due to the variation in a threshold voltage with the common
mode voltage. The threshold voltage reduces for a forward biasing of a bulk-source
junction. Therefore, the common mode control voltage VCNTRL changes according to
the currents in the transistors 316, 328, 314 and 326 that correct the output common
mode voltage of the main differential amplifier 500. The sixth transistor 316 and the
twelfth transistor 328 serves as active load for producing the common mode control
voltage VCNTRL by sinking and sourcing extra currents, so as to perform common
mode feedback operation.
If the common mode voltage of the input terminals of 300 is greater than VCM, then the
current through the transistors 308 and 310 is decreased due to more reverse biasing of
the source-bulk junction and the current through the transistors 320 and 322 is decreased
due to the reduced gate to source voltages for these transistors. Due to the reduction in
the currents through the transistors 308,310, 320 and 322, current through the transistors
312 and 324 is increased and as a result the output voltage VCNTRL of 300 increases.
This increased voltage which is mirrored to the main differential amplifier 500 through
the active elements 520 and 522 increases the current through the active elements 520
and 522 and thereby the output node voltages (common mode voltage) of the main
differential amplifier 500 are decreased. Similarly, a decrease in the common mode
@ voltage is restored by the CMFB module 300.
For the system to work properly, the bulk driven the controlling module 202 should not
have any forward bias junction (drain-bulk or source-bulk). If the source-bulk junction of
transistors 308 and 310 are not forward biased, then the drain-bulk junction will also not
be forward biased because the drain terminal voltages of these transistors will be lower
than their source terminal voltages. To ensure this, the first differential input voltage
VCMP and the second differential input voltage VCMM should not go lower than the
input terminal voltage V1 of the CMFB module 300.
If the common mode voltage of the operational amplifier 500 goes near to the ground
voltage, then the source bulk junction will be forward bias and there will be no control on
a gmb (transconductance of bulk driven MOSFETs) and the controlling module 202 will
not work accordingly.
Therefore, for the proper working of the controlling module 202, an extra or auxiliary
common mode feedback loop, i.e., the initializing module 204 is added to the CMFB
module 300. So, when the common mode voltage of the operational amplifier 500 goes
near to the ground voltage AGND, the initializing module 204 works and raises the
common mode voltage to the extent from where the controlling module 202 starts
working. After raising the output common mode voltage to some extent, the initializing
module 204 stops working because of the swing problem. The controlling module 202
cannot work for large values of the common mode voltage. So, the CMFB module 300
can work for a large swing of the operational amplifier's outputs. The initializing module
204 is designed with a gain as low as possible to avoid any compensation.
FIGURE 6 illustrates a flow diagram of a method for generating a common mode control
voltage according to the present invention. At step 602, a controlling module and an
initializing module are initialized by a supply voltage and a ground voltage. At step 604,
a first differential voltage is applied at a bulk terminal of a second transistor and at a gate
terminal of an eighth transistor. At step 606, a second differential voltage is applied at a
@ bulk terminal of a third transistor and at a gate terminal of a ninth transistor. At step 608,
a common mode reference voltage is applied at a bulk terminal of a fourth transistor and
at a gate terminal of a tenth transistor. At step 610, a bias current is applied at gate
terminals of a first transistor and a seventh transistor. At step 612, an input terminal
voltage is applied at gate terminals of the second transistor, the third transistor and the
fourth transistor. At step 614, the common mode control voltage is generated.
I ~ The present invention offers several advantages. First, the depletion characteristic allows
zero, positive and even small negative values of the input common mode voltage to
achieve desired currents. This will lead to larger input common mode ranges that could
not otherwise be achieved at low power supply voltages. Second, there is no need of a
compensation network for phase margin of CMFB loop, as the CMFB loop is of low
gain.
Although the disclosure of circuit and method has been described in connection with the
embodiment of the present invention illustrated in the accompanying drawings, it is not
limited thereto. It will be apparent to those skilled in the art that various substitutions,
I ~ modifications and changes may be made thereto without departing from the scope and
spirit of the disclosure.

1. A low voltage continuous time common mode feedback module comprising:
an initializing module receiving a first differential input voltage (VCMP)
and a second differential input voltage (VCMM) for providing a direct current (DC)
bias ; and
a controlling module receiving the first differential input voltage (VCMP)
and the second differential input voltage (VCMM) for controlling a cominon mode
voltage.
2. The module as claimed in claim 1, wherein said controlling module comprises;
a first transistor having a gate terminal for providing a bias current (IPBIAS)
to the controlling module, a source terminal and a bulk terminal connected to a
supply voltage (AVDD) and a drain terminal connected to a first node (Nl);
a second transistor for receiving the first differential input voltage (VCMP),
having a source terminal connected to said first node (Nl), a bulk terminal
receiving said first differential input voltage (VCMP), a drain terminal connected to
a second node (N2) and a gate terminal connected to an input terminal voltage (Vl);
a third transistor for receiving the second differential input voltage
(VCMM), having a source terminal connected to said first node (Nl), a bulk
terminal receiving said second differential input voltage (VCMM), a drain terminal
connected to said second node (N2) and a gate terminal connected to said input
terminal voltage (V 1);
6 a fourth transistor for receiving a common mode reference voltage (VCM),
having a source terminal connected to said first node (Nl), a bulk terminal
receiving said common mode reference voltage (VCM), a drain terminal connected
to an output node (N5) and a gate terminal connected to said input terminal voltage
(V 1 );
a fifth transistor for controlling a flow of current through said second and
third transistors, said transistor having a source terminal and a bulk terminal
connected to a ground voltage (AGND), a drain terminal connected to said second
node (N2) and a gate terminal connected to a sixth node (N6); and
a sixth transistor for providing a common mode control voltage (VCNTRL),
having a source terminal and a bulk terminal connected to said ground voltage
(AGND), a drain terminal connected to said output node (NS), and a gate terminal
connected to the gate terminal of said fifth transistor through said sixth node (N6).
3. The module as claimed in claim 1, wherein said initializing module comprises:
a seventh transistor for providing said bias current (IPBIAS) to the
initializing module, said transistor having a source terminal and a bulk terminal
connected to said supply voltage, a drain terminal connected to a third node (N3)
and a gate terminal receiving said bias current;
an eighth transistor for receiving said first differential input voltage
(VCMP), said eight transistor having a source terminal connected to said third node
(N3), a bulk terminal connected to said supply voltage (AVDD), a drain terminal
connected to a fourth node (N4) and a gate terminal receiving said iirst differential
input voltage (VCMP);
a ninth transistor for receiving said second differential input voltage
(VCMM), said ninth transistor having a source terminal connected to said third
0 node (N3), a bulk terminal connected to said supply voltage, a drain terminal
connected to said fourth node (N4) and a gate terminal receiving said second
differential input voltage (VCMM);
a tenth transistor for receiving said common mode reference voltage (VCM),
said transistor having a source terminal connected to said third node (N3), a bulk
terminal connected to said supply voltage (AVDD), a drain terminal connected to
said output node (N5) and a gate terminal receiving said common mode reference
voltage (VCM);
an eleventh transistor for controlling a flow of current through said eighth
transistor and said ninth transistor, said transistor having a source terminal and a
bulk terminal connected to said ground voltage (AGND), a drain terminal
connected to said fourth node (N4) and a gate terminal connected to a seventh node
(N7); and
a twelfth transistor for providing said common mode control voltage, said
transistor having a source terminal and a bulk terminal connected to said ground
voltage (AGND), a drain terminal connected to said output node (N5), and a gate
terminal connected to the gate terminal of said eleventh transistor through said
seventh node (N7).
4. The module as claimed in claim 2, wherein said transistors comprises nchannel
metal oxide semiconductor (NMOS) transistors and p-channel metal oxide
semiconductor (PMOS) transistors.
5. The module as claimed in claim 3, wherein said transistors comprises nchannel
metal oxide semiconductor (NMOS) transistors and p-channel metal oxide
semiconductor (PMOS) transistors.
6. An operational amplifier comprising:
one or more differential amplifier stages for generating differential output
voltages; and
a low voltage continuous time common mode feedback module operatively
coupled to the one or more differential amplifier stages for receiving a first
differential input voltage (VCMP) and a second differential input voltage (VCMM)
to provide a common mode feedback voltage.
7. A method for generating a common mode control voltage in a continuous time
common mode feedback module comprising:
initializing a controlling module and an initializing module by a supply
voltage and a ground voltage;
applying a first differential voltage at a bulk terminal of a second transistor
and at a gate terminal of an eighth transistor;
applying a second differential voltage at a bulk terminal of a third transistor
and at a gate terminal of a ninth transistor;
applying a common mode reference voltage at a bulk terminal of a fourth
transistor and at a gate terminal of a tenth transistor;
applying a bias current at gate terminals of a first transistor and a seventh
transistor;
applying an input terminal voltage at gate terminals of said second
transistor, said third transistor and said fourth transistor; and
generating the common mode control voltage.
19
8. A low voltage continuous time common mode feedback module substantially as
herein described with reference to and as illustrated in the accompanying
drawings.
9, A method for generating a common mode control voltage in a continuous time
common mode feedback module substantially as herein described with reference
to and as illustrated in the accompanying drawings.