Abstract: With increasing interest in wearable sensors and electronics, there is an immense need for thin-film electrical energy storage devices. Herewith, we are reporting a novel device architecture, and fabrication process that is conceptually scalable to any size. It"s a new design geometry for thin film Supercapacitors, fabricated using reactive sputtering over an altered FTO plate (fluorine doped tin oxide) followed by spin coating. The device can be fabricated by varying the layered thickness parameters over any non-conducting surface making them promising power sources for small-scale flexible microelectronic energy storage systems (e.g., next-generation smart phones and sensors). The device architecture forms a four layered stacked design on a non¬conducting substrate, which consist of a layer of active material (TiAIC and CuAIN) formed with difference between high and low resistance regions,with a thickness ranging from nanometers to micrometers scale. Their unique configurations with varying high and low resistance regions over the same surface with thin and uniform thicknesses not only guarantee fast electrochemical responses during charge/discharge processes but also allow them to operate at both higher and lower voltages. The new device geometry can be applied to both miniaturized and large-scale devices.
In this invention, new design geometry for thin film Supercapacitor has been developed, which is fabricated using reactive sputtering over altered FTO plate followed by spin coating. Using this architecture, the device can be fabricated by varying the layered thickness parameters over any non-conducting surface making them promising power sources for small-scale flexible microelectronic energy storage systems (e.g., next-generation smart phones and sensors). The device architecture forms a four-layer stacked design on a non-conducting substrate, which consist of a layer of active material with a thickness ranging from nanometers to micrometers scale, (any active material of choice can be used). Their unique configurations with varying high and low resistance regions over the same surface with thin and uniform thicknesses not only guarantee fast electrochemical responses during charge/discharge processes but also allow to operate at both higher and lower voltages.
LIST OF PREFERRED AND OPTIONAL FEATURES
1. The new device geometry can be used to both miniaturized and large-scale devices.
2. Any active material of choice and combination of electrolyte can be used depending on the required application.
3. Can fabricate device over any non-conducting surface.
BRIEF DESCRIPTION OF THE DRAWING
Figure: 1 Photographic view of supercapacitor device.
Figure: 2 Schematic representation of the developed stacked layer device.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[01] The proposed architecture can be used to create a supercapacitor device even on a non-conducting surface. To
make it strong and adhesive we have coated a thin film of active material using sputtering technique over an altered fluorine doped tin oxide (FTO) glass plate. Commercially purchased FTO plate (fluorine doped tin oxide) was altered in order to generate a conductivity/resistance difference before sputtering the active layer over it. [05] Electrolyte layer and conducting layer for secondary contact was developed using spin coating technique with partial masking. Stacked layers can be developed in any possible method (sputtering/spray pyrolysis/spin coating) but care should be taken in order to avoid short circuit. The active material coating is split into two different regions with varying conductivity/ resistance that will play the vital role in the electrolyte layer coatings maintaining a
moderate resistance in order to aid the electron flow.
[10] Secondary contact layer is developed in order to collect the electrons from the electrolyte layer. While connecting for electrical contacts, one terminal should be connected from the lower resistance region of the active ! material directly whereas another one should be from the secondary contact layer in order to complete the circuit. The promising results of stacked electrodes through cyclic voltammetry (CV) technique at high (lOV/s) and low (0.1 V/s) scan rates show an areal capacitance of 1.8 and 7.4 mF cm-2 respectively. It achieved an areal capacitance of 1.138 mF cm-2 through galvanostatic charge discharge (GCD) at 0.1mA applied current.
| # | Name | Date |
|---|---|---|
| 1 | 202041034792-FER.pdf | 2021-10-18 |
| 1 | 202041034792-Form9_Early Publication_13-08-2020.pdf | 2020-08-13 |
| 2 | 202041034792-Form18_Examination Request_13-08-2020.pdf | 2020-08-13 |
| 2 | 202041034792-Abstract_As Filed_13-08-2020.pdf | 2020-08-13 |
| 3 | 202041034792-Form-5_As Filed_13-08-2020.pdf | 2020-08-13 |
| 3 | 202041034792-Claims_As Filed_13-08-2020.pdf | 2020-08-13 |
| 4 | 202041034792-Form-3_As Filed_13-08-2020.pdf | 2020-08-13 |
| 4 | 202041034792-Correspondence_As Filed_13-08-2020.pdf | 2020-08-13 |
| 5 | 202041034792-Description Complete_As Filed_13-08-2020.pdf | 2020-08-13 |
| 5 | 202041034792-Form-1_As Filed_13-08-2020.pdf | 2020-08-13 |
| 6 | 202041034792-Drawing_As Filed_13-08-2020.pdf | 2020-08-13 |
| 6 | 202041034792-Form 2(Title Page)Complete_13-08-2020.pdf | 2020-08-13 |
| 7 | 202041034792-Drawing_As Filed_13-08-2020.pdf | 2020-08-13 |
| 7 | 202041034792-Form 2(Title Page)Complete_13-08-2020.pdf | 2020-08-13 |
| 8 | 202041034792-Description Complete_As Filed_13-08-2020.pdf | 2020-08-13 |
| 8 | 202041034792-Form-1_As Filed_13-08-2020.pdf | 2020-08-13 |
| 9 | 202041034792-Correspondence_As Filed_13-08-2020.pdf | 2020-08-13 |
| 9 | 202041034792-Form-3_As Filed_13-08-2020.pdf | 2020-08-13 |
| 10 | 202041034792-Form-5_As Filed_13-08-2020.pdf | 2020-08-13 |
| 10 | 202041034792-Claims_As Filed_13-08-2020.pdf | 2020-08-13 |
| 11 | 202041034792-Form18_Examination Request_13-08-2020.pdf | 2020-08-13 |
| 11 | 202041034792-Abstract_As Filed_13-08-2020.pdf | 2020-08-13 |
| 12 | 202041034792-Form9_Early Publication_13-08-2020.pdf | 2020-08-13 |
| 12 | 202041034792-FER.pdf | 2021-10-18 |
| 1 | SS16E_24-02-2021.pdf |