POLY - SILICON AMOLED SELF-BIASED CASCODE PIXEL CIRCUIT WITH HIGHLY LINEAR TRANSFER CHARACTERISTICS
Field of the invention
The present invention relates to a poly-silicon AMOLED pixel circuit with highly linear transfer characteristics. More particularly, the present invention relates to a novel poly-silicon AMOLED pixel circuit with highly linear transfer characteristics wherein the KINK effect is reduced by use of a self-biased cascode structure.
Background of the invention
Organic light emitting diode (OLED) displays are being increasingly viewed as the flat panel technology of the future due to their several advantages including wide viewing angle, fast response time, thin size and low cost [C.W. Tang and S. Van Slyke, "Organic Electroluminescen Diodes", Appl. Phys. Lett., Vol. 51, pp. 913, 1987; Yasunori Kijima, Nobutoshi Asai, Noriyuki Kishii, and Shinichiro Tamura, "RGB Luminescence from Passive-Matrix organic LED's" IEE Trans. Electron Devices, Vol. 44, pp. 1222, Aug. 1997; T. Tohma "Recent prograss in Development of organic Electroluminescent Display Devices," in Int. Display Research conference (IDRC) Dig. Tech. Papers, 1997, F 1.1.]. These displays can be built either as passive matrix panels consisting of only OLEDs or active matrix panels (AMOLED) in which the OLED is integrated with thin film transistors (TFT) in a suitable manner. Passive matrix displays are simpler and cheaper but they suffer form several problems, which limit their range of applicability to low information content displays [A. Hunze, M. Scheffel, J. Birnstock, J. Blassing, A Kanitz, W. Rogler, G. Wittmann, A. Winnacker, S. Rajoelson, H. Hartmann, "Passive Matrix Displays Based on the New Red Emitting Dopant RedATDBstors", SID 2002, pp. 1186, 2002; Y. Sakaguchi, H. Tada, T. Tanaka, E. Kitazume, K. Mori, S. Kawashima, J. Suzuki, "Color Passive-Matrix Organic LED Display using Three Emitters", SID 2002, pp. 1182, 2002; S. Xiong, B. Guo, C. Wu, Y. Chen, Y. Hao, z. Zhou, H. Yang, " A Novel Design of Sub-frame and Current Driving Method for PM-LED", SID 2002, pp. 1174, 2002].
Although active matrix displays are more complex and expensive, they have superior characteristics and are necessary for high resolution applications. AMOLED displays can be built by integrating either amorphous Silicon TFTs [Y. He, R. Hattori and J. Kanicki, "Improved A-Si:H TFT Pixel Electrode Circuits for Active Matrix Organic Light Emitting Display", IEEE Tran. Electron Dev., Vol. 48 p. 1322 (2001); S.K. Bhowmick, B. Mazhari, "An improved four TFT circuit for Active Matrix Organic Light Diode display", SID 2002, pp. 6006, 2002; Y. Hong and J. Kanicki, "Novel poly-si TFT pixel electrode circuits and current programmed Active Matrix driving methods for AMOLED", SID 2002, pp. 618, 2002] or Poly-silicon TFTs [; S. W. B. Tarn, Y. Matsueda, H. Maeda, M. Kimura, T. Shimoda and P. Migliorato, "Poly-Si Driving Circuits for Organic EL Displays", Conf. 4925A, Electronic Imaging 2001, San Jose California U.S.A. Y. C. Lin, H.P. D. Shieh and F. Yang, "Current driving pixel circuities for Active Matrix Organic Light Emtting Diode display", SID 2002, pp. 610, 2002] with the light emitting diode. Poly-Silicon is preferred because of its higher current driving capability as a result of better carrier mobility. A pixel circuit can be voltage or current driven depending on the nature of applied input signal. The current driven pixel circuit is preferred because the light output in an OLED varies linearly with the drive current.
The central problem in the design of current driven pixel circuit is to ensure that the OLED is driven with a specified input current not only during the time when the OLED is addressed but during the rest of the frame period as well when the OLED is not being addressed. There are two important factors, which cause the OLED current to deviate from the input current. The first is the large variation in TFT threshold voltage and the second is the Kink effect in the Poly-Silicon TFT characteristics. The first problem can be significantly reduced by using pixel circuits, which belong to the class of switched-current memory circuits [12], an example of which is shown in figure 1. In the addressing phase (φ is high), the input programming current flows through TFT4 and also charges the capacitor Cs to a suitable value of gate voltage required for the flow of this current. Because the gate
voltage tracks the threshold voltage of TFT4, the effect of variation of threshold voltage is practically cancelled in this circuit. During the non-addressing phase (φ is low), the gate voltage on the capacitor tends to maintain the same current through TFT4 and OLED. Beside insensitivity to threshold voltage variation, another important characteristic that these current-programmed AMOLED pixel circuits must exhibit is small mismatch between the output current during the non-addressing phase and the input programming current. Ideally the relationship between the two currents should be linear over a large range of input current so as to obtain a large number of gray levels. Data for Figure 2
(Table Removed)
However, the Kink effect in the characteristics of Poly-Silicon TFT makes the characteristic highly nonlinear as explained in the next section. In this work a new pixel circuit is proposed which is able to achieve highly linear transfer characteristics by reducing the impact of kink effect in the TFT through use of a cascode structure.
US Patent 6,351,327 discloses a liquid crystal pixel current sensing technique that increases LC (Liquid Crystal)-based micro display contrast fidelity. The invention disclosure provides for a spatial light modulator which has an electro-optical material (such as a liquid crystal layer) between an array of pixel electrodes and a common electrode (such as an indium tin oxide (ITO) layer). An amplifier biases the common electrode of the spatial light modulator and outputs a differential current proportional to the electro-optical material current. The output is used to determine delay of a light source to compensate for switching delay of the modulator. For one embodiment, the amplifier has a common-source push-pull output stage and current mirrors. For another embodiment, the output stage is a cascode common-source push-pull output stage. Because the current sensor does not perform current-to-voltage conversion, it does not alter the impedance between the pixel driver and the pixel electrode. Also, it is claimed that the technique can be used to measure the current through the entire active display area.
Large area electronic devices usually consist of one- or two-dimensional arrays of thin-film circuit elements (often referred to as pixels). These pixels might contain, for example, liquid-crystal light valves for a display, or photodiodes for an optical scan array, or nibs for a print array. In each case the physical size of the array is determined by the application, and is much larger than a conventional silicon integrated circuit. The arrays are therefore built on large area substrates, usually of glass or quartz. The pixel arrays also require driving and interface circuitry, and in most cases this circuitry must be analog rather than digital, that is it must be capable of delivering or sensing a range of input signals. Suitable analog circuitry can be built using well-known switched capacitor techniques in conventional silicon integrated circuits (ICs). These ICs must then be mounted on or adjacent to the large area
substrate containing the pixel array, and a large number of electrical connections must be made between the two. The cost of the peripheral drive and interface chips, their mounting and their electrical connection to the large area device can constitute a significant proportion of the overall cost of a system containing a large area device. If the ICs and connections can be eliminated or greatly reduced by integrating suitable circuitry on the large area substrate, then the system cost can be reduced and its reliability improved.
Thus, it is desirable to integrate drive circuitry with the pixel elements on a common substrate (e.g., glass or quartz). A number of circuits have been integrated with LAE displays using polysilicon and amorphous silicon thin film technologies. However, these have been purely digital circuits, or, where analog drive is needed, have used a simple pass transistor to deliver the analog signal to the array with the state of the pass transistor being controlled by digital circuitry.
It has been recognized that polysiHcon thin film technology may enable the integration of drive circuitry on a substrate with a pixel array. However, due to the inferior performance of polysilicon thin film transistors (TFTs) when compared with conventional single crystal silicon MOS field effect transistors (MOSFETs), it has been thought that the fabrication of true analog circuits using polysilicon thin film technologies is not possible.
PolysiHcon TFTs are inferior to conventional siHcon MOSFETs in several ways. First, the electrical drive current available from a polysiHcon TFT is much lower than that of a similar-sized MOSFET. This limitation also appHes to digital circuits, but is more severe under the bias conditions typically employed in analog amplifiers. Second, the saturation characteristics of polysilicon TFTs are poor, with a low output impedance caused by the so-called "kink" effect which arises from channel avalanche multipHcation and which is made worse by the presence of trap states in the device channel. This low output impedance is much more important for analog circuits than digital since it can limit the voltage gain available from an amplifier. Third, polysilicon TFTs are known to suffer from relatively high off-state leakage currents compared
with MOSFETs. In analog applications, it is often necessary to store charge on a capacitor, and any charge lost due to TFT leakage will cause an error in the analog signal. Digital circuits, on the other hand, are much less susceptible to leakage; even in a dynamic design, where charge is also stored on a capacitive node, the total charge loss must exceed some threshold value before any signal error will arise, and this threshold is normally much larger than the acceptable charge loss in an analog circuit. Fourth, polysilicon TFTs exhibit much higher electrical noise then MOSFETs, a problem which is again much more important in analog applications than digital.
Single crystal thin-film technologies, also referred to as silicon-on-insulator technologies, such as silicon-on-saphire (SOS), separation by implanted oxygen (SIMOX) or zone-melt recrystallization (ZMR), also suffer some of the limitations discussed above, notably the kink effect (although it is not so severe in single crystal SOI MOSFETs as in polysilicon TFTs) and increased leakage. These technologies are not commonly used for analog applications, in part for these reasons. Several references recognize that it would be desirable to use TFTs to form integrated drivers for LAE devices such as liquid crystal displays. These references disclose polysilicon treatments which improve some of the characteristics of TFTs, however, even the improved polysilicon TFTs do not approach single crystal transistors in operating characteristics. None of the references disclose switched capacitor analog circuits constructed using polysilicon thin film technology. Objects of the invention
The main object of the invention is to provide a modified poly-silicon pixel circuit which is able to achieve highly linear transfer characteristics by reducing the kink effect in TFT through use of a self-biased cascode structure. Summary of the invention
Accordingly the present invention provides a polysilicon pixel circuit comprising at least one pixel, said pixel comprising:
a light element having an anode and a cathode, where said anode of the said light element is coupled to power line;
a first transistor having a gate, a source and a drain , where the said gate is coupled to a first select line;
a second transistor having a gate, a source and a drain, where said drain of said first transistor is coupled to said source of said second transistor, where said gate of said first transistor is coupled to said gate of said second transistor, where said drain of said second transistor is coupled to input data line;
a third transistor having a gate, a source and a drain, where said drain of said first transistor is coupled to said source of said third transistor, where said gate of said third transistor is coupled to third select line, where said drain of said third transistor is coupled to said cathode of said light element.
a fourth transistor having a gate, a source and a drain, where said source of said third transistor is coupled to said drain of said fourth transistor, where said gate of said fourth transistor is coupled to said source of said first transistor;
a fifth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said drain of said fifth transistor, where said source of said fifth transistor is coupled to ground line;
a sixth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said source of said sixth transistor, where said gate of said sixth transistor is coupled to second select line, where said gate of said fifth transistor is connected to said drain of said sixth transistor;
a first capacitor having a first and second terminals, where said gate of said fourth transistor is coupled to said first terminal of the said first capacitor, where said source of said fifth transistor is coupled to said second terminal of the said first capacitor;
a second capacitor having a first and second terminals, where said gate of said fifth transistor is coupled to said first terminal of the said second capacitor, where said source of said fifth transistor is coupled to said second terminal of the said second capacitor
In one embodiment of the invention, the light element is an organic light emitting diode (OLED).
In another embodiment of the invention, the transistors are thin film transistors constructed from poly-silicon.
In another embodiment of the invention, pixel structure comprises six N-type thin film transistors Ti (610), T2 (620), T3 (630), T4 (640), T5 (650) and T6 (660) and two capacitors Ci (605), C2 (606) and an OLED (light element) (601), a first select line Si (681) being connected to gate of transistor 620, a second select line S2 (682) being connected to gate of transistor 660, and a third select line S3 (683) being connected to gate of transistor 630, an input data current line IDATA (690) being connected to drain of transistor 620, a Vdd power supply line (691) being connected to anode of OLED 601, a ground reference line GND (692) being connected to source of transistor 650.
In another embodiment of the invention, the select lines 681, 682 and 683 are common to all pixels in a row of matrix display.
In another embodiment of the invention, the gates of transistor 610 and transistor 620 are connected together, and wherein the drain of transistor 610, source of transistor 620 and source of transistor 630 are all connected together.
In another embodiment of the invention, the source of transistor 610 is connected to gate of transistor 640, and the source of transistor 640, source of transistor 660 and drain of transistor 650 are all connected together and wherein the drain of transistor 660 is connected to gate of transistor 650.
In another embodiment of the invention, one end of capacitor 605 is connected to source of transistor 610 and the other end is connected to source of transistor 650 and wherein one end of capacitor 606 is connected to gate of transistor 650 and the other end is connected to source of transistor 650.
In another embodiment of the invention, the anode of OLED 601 is connected to Vdd line 691 and cathode of OLED 601 is connected to drain of transistor 630.
In another embodiment of the invention, the operation of the pixel circuit structure is biphasic - addressing and non-addressing, wherein in the first phase, select lines Si (681) and S2 (682) are connected at time to to a positive voltage eg +14Volts to switch on transistors 610, 620 and 660, select line 683 is connected to OVolts, the input data current (690) line being simultaneously supplied with the desired data current, and wherein the power line Vdd (691) is permanently connected to a large positive voltage e.g. 18Volts.
In another embodiment of the invention, the input data current charges capacitance Ci (605) and capacitance C2 (606) and turns on transistors 640 and 650, whereby the magnitudes of gate voltages of transistors 640 and 650 adjust themselves in accordance with the threshold voltage of transistors and the data current.
In another embodiment of the invention, wherein at the beginning of non-addressing phase (ti), select line 683 is connected to positive voltage, which switches on transistor 630 and causes a current to flow through the OLED 601.
In another embodiment of the invention, the self-biased cascode connection represented by transistor 640 and a sub-structure consisting of transistors 660 and 650 and capacitor 606 sharply reduces the impact of kink as a result of negative feedback. Brief description of the accompanying drawings
Fig. 1 depicts a schematic diagram of a prior art current programmed active matrix OLED pixel structure.
Fig. 2 depicts a typical non-linearity in the input drive current vs. OLED current transfer characteristics for pixel structure shown in Fig. 1. Non-linearity is defined as the percentage deviation of OLED current from the input drive current.
Fig. 3 shows a typical current vs. voltage characteristics of poly-silicon thin film transistor. It illustrates the presence of Kink in the output characteristics of the transistor.
Fig. 4 shows a schematic diagram of a Cascode structure.
Fig. 5 shows the schematic diagram of a modified pixel structure in which the drive transistor T4 in Fig. 1 is replaced by a Cascode structure which is a combination of transistors T4 and T5.
Fig. 6 depicts a schematic diagram of an active matrix OLED pixel structure of the present invention.
Fig. 7 depicts the timing diagram for active matrix pixel structure of Fig. 6
Fig. 8 shows a typical OLED current vs. input drive current for the pixel circuit structure shown in Fig. 6
Fig. 9 depicts a typical non-linearity in the input drive current vs. OLED current transfer characteristics for pixel structure shown in Fig. 6. Non-linearity is again defined as the percentage deviation of OLED current from the input drive current. Detailed description of the invention
The present invention provides a novel polysilicon pixel circuit which is able to achieve highly linear transfer characteristics by reducing the Kink effect in TFT through use of a cascode structure. Simulation results have shown that drive currents as high as 20µA can be achieved with non-linearity under ± 1%.
The present invention will now be described with reference to the accompanying drawings, which are illustrative and should not be construed as limiting the scope of the invention in any manner.
It is well known that when the kink effect is absent, current in saturation mode of operation is almost independent of drain-to-source voltage. This makes the design of pixel circuit relatively simpler because it has to be ensured that only gate-to source voltage remains same in both addressing and non-addressing periods. The drain-to-source voltages can be widely different as long as they are larger than the saturation voltage. The presence of a kink in I-V characteristics impacts on manufacture difficult because of the necessity of keeping both gate and drain voltages constant.

Figure 1 is a representation of a prior art current programmed active matrix OLED pixel structure - circuit simulated with AIMSPICE simulator using the poly-silicon TFT model (Level-16 ASIA) in order to illustrate the impact of Kink effect on the transfer characteristics of the pixel, and with prior art parameters used in earlier studies [Y. Hong and J. Kanicki, "Novel poly-si TFT pixel electrode circuits and current programmed Active Matrix driving methods for AMOLED", SID 2002, pp. 618, 2002]. A supply voltage of 14V, Cs= 2pF, n-type TFT sizes of 10µm and OLED model consisting of a nonlinear current source in parallel with a capacitor was chosen such that the I-V characteristics predicted by it matched well with state-of the-art experimentally reported data. This structure suffers from several disadvantages. For example, the structure is sensitive to kink effect in transistor characteristics causing the OLED current to deviate from the input data current. This effect is further described in Figure 2.
Figure 2 shows the non linearity [(Iout-Idata)Iout) *100] in transfer characteristics. It can be seen that the non-linearity is very large at Idata= lµA and steadily decreases as the current increase. By changing the TFT sizes, the non-linearity can be reduced at µA but only at the expenses of increased non-linearity at 20µA. To reduce the non-linearity over the entire range of input current, kink effect in TFT must be reduced. Figure 3 shows the IDS to VDS characteristics of a poly silicon TFT.
The impact of Kink effect can be looked upon as an increase in output conductance of the transistor. A well known technique for reducing the output conductance is through use of Cascode structure shown in Figure 4. In Figure 4, source of transistor T4 is connected to drain of transistor T5. Transistor T5 requires a bias voltage value depending on the current that is required to flow through it. By replacing TFT4 in Figure 1 by a cascode transistor shown in Figure 4 a modified pixel circuit (500) as shown in Figure 5 is obtained which theoretically should have a more linear transfer characteristic which has the potential to overcome the impact of kink effect in poly-silicon TFT.
Referring now to Fig. 5, a pixel structure consists five N-type thin film transistors Ti (510), T2 (520), T3 (530), T4 (540) and T5 (550) and one capacitor Ci (505) and an OLED (light element) (501). A select line Si (581) is connected to gate of transistor 520. A second select line S2 (582) is connected to gate of transistor 650. A third select line S3 (583) is connected to gate of transistor 530. An input data current line IDATA (590) is connected to drain of transistor 520. A Vdd power supply line (591) is connected to Anode of OLED 501. A ground reference line GND (592) is connected to source of transistor 550.
The gates of transistor 510 and transistor 520 are connected together. The drain of transistor 510 , source of transistor 520 and source of transistor 530 are all connected together. The source of transistor 510 is connected to gate of transistor 540. The source of transistor 540 and drain of transistor 550 are connected together. One end of capacitor 505 is connected to source of transistor 510 and the other end is connected to source of transistor 550.
The anode of OLED 501 is connected to Vdd line 591 and cathode of OLED 501 is connected to drain of transistor 530.
The drawback of pixel structure 500 is that voltage applied to select line 582 depends on the current flowing through transistor T5. Since different currents flow in different pixels of a row of matrix display, a separate connection corresponding to select line 582 of each pixel of the display panel has to be externally brought out. The resulting large number of electrodes in the display panel makes this pixel structure impractical. The aim of the present invention is to overcome this disadvantage by internally generating the voltage required at select line 582 from the supplied input data current.
The circuit of Figure 5 is impractical since an external bias voltage for TFT5 is required which for proper operation has to be tuned in accordance with the input programming current. The present invention resides in the realisation that the above problem can be overcome by generating the gate bias of TFT5 using the input programming current itself as illustrated in Figure 6. During the addressing phase
TFT6 is switched ON so that input programming current charge up the capacitor CS2 to a bias voltage that is appropriate for the input current to flow. During the addressing phase itself, after a certain time, TFT6 is switched In Figure 5. Clock cpiis in phase with clock (p but kept ON for only a part of the period during which cp is ON.
Fig. 6 depicts a schematic diagram of an active matrix OLED pixel structure 600 of the present invention. In the present embodiment, the active matrix OLED pixel structure is implemented using poly-silicon thin film transistors (TFT). However, it is understood that the present invention can be implemented using other types of transistors as well.
In Figure 6, the pixel structure 600 provides a current drive to the OLED which is equal to the input data current in the presence of threshold voltage non-uniformity and kink effect in poly-silicon TFT. In other words, it is desirable to maintain OLED current equal to input data current to ensure the integrity of the displayed image.
Referring to Fig. 6, a pixel structure consists six N-type thin film transistors Ti (610), T2 (620), T3 (630), T4 (640), T5 (650) and T6 (660) and two capacitors Ci (605), C2 (606) and an OLED (light element) (601). A select line Si (681) is connected to gate of transistor 620. A second select line S2 (682) is connected to gate of transistor 660. A third select line S3 (683) is connected to gate of transistor 630. An input data current line IDATA (690) is connected to drain of transistor 620. A Vdd power supply line (691) is connected to Anode of OLED 601. A ground reference line GND (692) is connected to source of transistor 650. It is to be noted that select lines 681, 682 and 683 are common to all pixels in a row of matrix display.
The gates of transistor 610 and transistor 620 are connected together. The drain of transistor 610, source of transistor 620 and source of transistor 630 are all connected together. The source of transistor 610 is connected to gate of transistor 640. The source of transistor 640, source of transistor 660 and drain of transistor 650
are all connected together. The drain of transistor 660 is connected to gate of transistor 650.
One end of capacitor 605 is connected to source of transistor 610 and the other end is connected to source of transistor 650. One end of capacitor 606 is connected to gate of transistor 650 and the other end is connected to source of transistor 650. The anode of OLED 601 is connected to Vdd line 691 and cathode of OLED 601 is connected to drain of transistor 630.
The operation of pixel circuit structure can be divided into two phases; addressing and non-addressing (Fig. 7). In the first phase of operation called addressing phase, select lines Si (681) and S2 (682) are connected at time to to a positive voltage eg +14Volts to switch on transistors 610, 620 and 660. Select line 683 is connected to OVolts. Simultaneously, the input data current (690) line is supplied with the desired data current.. The power line Vdd (691) is permanently connected to a large positive voltage e.g. 18Volts. The input data current charges capacitance Ci (605) and capacitance C2 (606) and turns on transistors 640 and 650. The magnitudes of gate voltages of transistors 640 and 650 adjust themselves in accordance with the threshold voltage of transistors and the data current. After a short period (ti-to) e.g. 15µs, the select line S2 (682) is returned back to OVolts as shown in Fig. 7. This turns OFF the transistor 660. Select line Si (681) is maintained at a positive voltage during this process so as to allow gate voltage of transistor 640 to adjust itself to new circuit configuration with transistor 660 in OFF state. Thus, select line 682 is activated for only a part of addressing phase. At the end of addressing phase (t2) e.g. of time duration 35µs , select line 681 is returned to zero volts and simultaneously, the input data current is switched OFF. This marks the beginning of non-addressing phase of a much larger duration e.g. 20ms.
At the beginning of non-addressing phase (t2), select line 683 is connected to positive voltage e.g. +13V, which switches on transistor 630 and causes a current to flow through the OLED 601. The charges stored on capacitors 605 and 606 during addressing phase provide necessary gate voltage drive for transistors 640 and 650 to
remain conducting in the non-addressing phase. Since charges on these capacitors were developed in response to input data current, the current through transistors 640 and 650 tends to remain equal to data current in non-addressing phase despite variations in threshold voltage of the transistors either in time or spatially across the display panel. The drain voltage of transistor 640 is in general different in addressing and non-addressing phases. As a result of kink effect, which makes current in a transistor dependent on drain voltage (Fig. 3), the current through transistor 640 (and hence OLED) tends to deviate from the input data current in non-addressing phase. The self-biased cascode connection represented by transistor 640 and a sub-structure consisting of transistors 660 and 650 and capacitor 606 sharply reduces the impact of kink as a result of negative feedback. The operation of negative feedback can be summari2ed as follows: an increase in current through transistor 640 due to kink effect would require an increased current to flow through series connected transistor 650 as well. Since the gate voltage of transistor 650 is at a fixed voltage maintained by capacitor 606, the drain voltage of transistor 650 must increase by a large amount to allow increased current to flow. This results in increase in source voltage of transistor 640 by the same amount. Since the gate voltage of transistor 640 is at a fixed voltage maintained by capacitor 605, the gate-source voltage of transistor 640 decreases. This tends to decrease current through transistor 640 thus completing the negative feedback loop.
The design of cascode pixel circuit was carried out for a current range of 1-20 |iA at a supply voltage of 14V. The level of clock voltage was 0 →14V. the optimum TFT sizes obtained were (W/L)4 = 36µm/22µm, (W/L)3 = (W/L)5 = 36µm/10µm and (W/L)2 = (W/L)i = 10µm / 10µm. The programming period was taken to be ~40µs. To allow for both the capacitors to charge to their required voltage, a pre-charge current pulse was used. Figure 8 shows the results obtained from simulations with AIMSPICE simulator using the poly-silicon TFT model (Level- 16 ASIA2). It can be seen that the match between input and output current is excellent over the entire current range for this pixel circuit (i.e < +10%). The 6-TFT pixel circuit of the
invention provides very good linearity in the transfer characteristic of the pixel circuit by employing a self biased cascode structure. It is shown that nonlinearity under +1% can be obtained over a large current range. The data for Figures 8 and 9 are given below:
Data for Figure 8 and 9
(Table Removed)
Although the present invention is described using N-type transistors, it should be understood that the present invention can be implemented using P-type transistors, where the relevant voltages are reversed.

We claim:
1. A polysilicon pixel circuit comprising at least one pixel, said pixel comprising:
a light element having an anode and a cathode, where said anode of the said light element is coupled to power line;
a first transistor having a gate, a source and a drain , where the said gate is coupled to a first select line;
a second transistor having a gate, a source and a drain, where said drain of said first transistor is coupled to said source of said second transistor, where said gate of said first transistor is coupled to said gate of said second transistor, where said drain of said second transistor is coupled to input data line;
a third transistor having a gate, a source and a drain, where said drain of said first transistor is coupled to said source of said third transistor, where said gate of said third transistor is coupled to third select line, where said drain of said third transistor is coupled to said cathode of said light element.
a fourth transistor having a gate, a source and a drain, where said source of said third transistor is coupled to said drain of said fourth transistor, where said gate of said fourth transistor is coupled to said source of said first transistor;
a fifth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said drain of said fifth transistor, where said source of said fifth transistor is coupled to ground line;
a sixth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said source of said sixth transistor, where said gate of said sixth transistor is coupled to second select line, where said gate of said fifth transistor is connected to said drain of said sixth transistor;
a first capacitor having a first and second terminals, where said gate of said fourth transistor is coupled to said first terminal of the said first capacitor, where said source of said fifth transistor is coupled to said second terminal of the said first capacitor;
a second capacitor having a first and second terminals, where said gate of said fifth transistor is coupled to said first terminal of the said second capacitor, where said source of said fifth transistor is coupled to said second terminal of the said second capacitor
2. A circuit as claimed in claim 1, wherein said Ught element is an organic Ught emitting diode (OLED).
3. A circuit as claimed in claim 1, wherein said transistors are thin film transistors constructed from poly-siUcon.
4. A circuit as claimed in claim 1, wherein the pixel structure comprises six N-type thin film transistors Ti (610), T2 (620), T3 (630), T4 (640), T5 (650) and T6 (660) and two capacitors C1 (605), C2 (606) and an OLED (light element) (601), a first select line Si (681) being connected to gate of transistor 620, a second select line S2 (682) being connected to gate of transistor 660, and a third select line S3 (683) being connected to gate of transistor 630, an input data current line IDATA (690) being connected to drain of transistor 620, a Vdd power supply line (691) being connected to anode of OLED 601, a ground reference line GND (692) being connected to source of transistor 650.
5. A circuit as claimed in claim 4, wherein the select lines 681, 682 and 683 are common to all pixels in a row of matrix display.
6. A circuit as claimed in claim 4 or 5, wherein the gates of transistor 610 and transistor 620 are connected together, and wherein the drain of transistor 610, source of transistor 620 and source of transistor 630 are all connected together.
7. A circuit as claimed in claim 4 or 5, wherein the source of transistor 610 is connected to gate of transistor 640, and the source of transistor 640, source of transistor 660 and drain of transistor 650 are all connected together and wherein the drain of transistor 660 is connected to gate of transistor 650.
8. A circuit as claimed in claim 4 to 7, wherein one end of capacitor 605 is connected to source of transistor 610 and the other end is connected to source of
transistor 650 and wherein one end of capacitor 606 is connected to gate of transistor 650 and the other end is connected to source of transistor 650.
9. A circuit as claimed in claim 4 to 8, wherein the anode of OLED 601 is connected to Vdd line 691 and cathode of OLED 601 is connected to drain of transistor 630.
10. A circuit as claimed in any preceding claim, wherein the operation of the pixel circuit structure is biphasic - addressing and non-addressing, wherein in the first phase, select lines Si (681) and S2 (682) are connected at time to to a positive voltage eg +14Volts to switch on transistors 610, 620 and 660, select line 683 is connected to OVolts, the input data current (690) line being simultaneously supplied with the desired data current, and wherein the power line Vdd (691) is permanently connected to a large positive voltage e.g. 18Volts.
11. A circuit as claimed in any preceding claim wherein the input data current charges capacitance Ci (605) and capacitance C2 (606) and turns on transistors 640 and 650, whereby the magnitudes of gate voltages of transistors 640 and 650 adjust themselves in accordance with the threshold voltage of transistors and the data current.
12. A circuit as claimed in any preceding claim wherein the at the beginning of non-addressing phase (t2), select line 683 is connected to positive voltage, which switches on transistor 630 and causes a current to flow through the OLED 601.
13. A circuit as claimed in any preceding claim wherein the self-biased cascode connection represented by transistor 640 and a sub-structure consisting of transistors 660 and 650 and capacitor 606 sharply reduces the impact of kink as a result of negative feedback.
14. A polysilicon pixel circuit substantially as described hereinbefore and with reference to the foregoing accompanying drawings.