Abstract: A process for selective thinning of emitter on uniformly doped c-Si wafers by using printed grid lines as a self-mask, comprising:- making PV cell industrially starting from wafer, chemical texturisation, diffusion, edge isolation, PSG removal on c-Si solar cells; depositing grid lines on the electrical contacts by screen printing, avoiding ARC at this point; single side plasma etching of the PV cells using SF6 and O in a suitable ratio on the unmasked area; optimizing the operating parameters of plasma power, time of etching, gas ratios for texturing the non-printed area.
FIELD OF THE INVENTION
The present invention relates to a process for selective thinning of emitter on uniformly doped c-Si wafers by using printed grid lines as a self-mask, which improves electrical performance of selectively etched c-Si solar cell obtained by controlling plasma process parameters.
BACKGROUND OF THE INVENTION
Selective doping of emitter is one of the crucial steps for developing high efficiency Si solar cells. Heavily doped regions are required below the printed grid lines to reduce contact resistance. Shallow emitter is required in the area which is exposed to sunlight to enhance Voc and Isc. This selective requirement can be met by using special pastes and chemicals and reactive ion etching. A few relevant patents are described below:
In patent no. US 8293568 B2 Rubin et al. disclosed a selective emitter with low temperature etch back and passivation process. It involves formation of silicon oxide layer electrochemically on selective area upto dead zone. The mask is removed and the first oxide layer until considerably all of the first silicon oxide layer is removed. A second silicon oxide layer is then electrochemically formed on the front side such that the layer has sufficient thickness to passivate the front side. In this above method two most difficult tasks are involved. Step 1) forming silicon oxide layer upto dead zone and step 2) removal of first oxide layer substantively. This approach is different from what is explained in the present application.
In patent no. US 5871591 and 6091021 Ruby et al. described self-aligned selective-emitter PV cells by plasma-etch back process. Heavily doped mc-Si wafers were etched in RIE after deposition of passivated layers of SiO2 on industrially diffused wafers. In this process metallized grids of the PV cells are used to mask heavily doped emitter regions to allow selective etching. After PSG removal wafers have been passivated followed by printing of metal contacts. The wafers exposed to RIE for etch back process without
depositing anti-reflection coating (ARC). After the emitter is etched, silicon nitride is deposited by plasma-enhanced chemical vapor deposition (PECVD), to create an antireflection coating. The solar cell is then annealed in a forming gas. Above approach is applied on mc-Si wafers where orientation of planes are in various direction. After the emitter etches, anti-reflection coating is deposited on mc-Si solar cell. This patent is similar to the patent in this application excepting that c-Si solar cells are used instead of mc-Si. The plasma etching also has been done without any oxide layer.
In U.S. Pat. Nos. 6,552,414 and 6,825,104, Horzel et al. Define a PV cell with two selectively diffused regions using different doping levels. First screen printing process is adopted to deposit a solid based dopant source onto a substrate. In a special atmosphere diffusion of the dopant atoms creates two areas one with high dopant concentration area under the dopant source and a low dopant concentration area on the rest of the solar cell’s front side. A second screen printing deposits a metallization pattern that precisely aligned the screen printers on the fingers and bus bars with to make high dopant concentration areas under it. However, with these methods, it is very difficult to ensure apposite reproducibility of the properties of the emitter, especially the thickness of the selective shallow emitter region.
OBJECTS OF THE INVENTION:
It is therefore an object of the invention to propose a process for selective thinning of emitter on uniformly doped c-Si wafers by using printed grid lines as a self-mask.
Another object of the invention is to propose a process for selective thinning of emitter on uniformly doped c-Si wafers by using printed grid lines as a self-mask, which improves VOC and ISC leading to gain in cell efficiency.
SUMMARY OF THE INVENTION
Diffused, printed c-Si solar cells have been selected with sheet resistance of the diffused emitter as 40-45 Ω/□. Initial efficiency of the cell has been measured. The cells
have been placed on an ss carrier which can accommodate 15 pieces. The carrier is pushed into the plasma chamber and etching process has been optimised. Plasma of SF6:O2 first oxidises the Si surface and the Fluorine atoms etch the SiO2. The printed metal lines act as mask and the emitter is etched selectively. The emitter is etched resulting in an increase of sheet resistance of emitter to about 70-80 Ω/□. After depositing AR coating of SiN, the cells are measured again. A gain of about 0.4% absolute is achieved in cell efficiency.
BREIF DESCRIPTON OF THE INVENTION
Figure 1 PECVD chamber arrangement for selective etching of emitter of c-Si solar cells.
DETAILED DESCRIPTION OF THE INVENTION:
Diffused, printed c-Si solar cells of 156mm x 156mm size have been selected where the sheet resistance of the diffused emitter is 40-45 Ω/□. Initial efficiency of the cell has been measured using a standard IV tester under AM 1.5 spectrum with 100 mW/cm2 intensity. The cells have been placed on an ss carrier which can accommodate 15 pieces of 156mm x 156mm size. The carrier is pushed into the plasma chamber and etching process has been attempted by varying various process parameters such as process pressure, etching time, ratios of process gases SF6 and O2. The process gases are fed into the plasma chamber using a shower head for uniform distribution of process gases as shown in Fig 1. Plasma of SF6:O2 first oxidises the Si surface and the Fluorine atoms etch the SiO2. The printed metal lines act as mask and the emitter is left un-etched below the printed lines leaving the emitter deep. The bare portion of the Si wafer is exposed to plasma and the emitter is etched resulting in an increase of sheet resistance of emitter to about 70-80 Ω/□. The etched wafers are taken out of the plasma chamber and anti reflection coating of SiN is deposited using a PECVD system. These cells are measured again for cell efficiency. A gain of about 0.4% absolute is achieved in cell efficiency.
USE OF INVENTION:
Reduction of emitter thickness selectively on single side of c-Si solar cell using plasma etching is a preferred method as other in other methods one has to handle a number of chemicals and precise alignment of screen printing is required. Thinning of emitter improves the minority carrier lifetime which results in higher open circuit voltage (Voc) and higher short circuit current (Isc) leading to gain in cell efficiency.
WE CLAIM
1. A process for selective thinning of emitter on uniformly doped c-Si wafers by
using printed grid lines as a self-mask, comprising:-
- making PV cell industrially starting from wafer, chemical texturisation, diffusion, edge isolation, PSG removal on c-Si solar cells;
- depositing grid lines on the electrical contacts by screen printing, avoiding ARC at this point;
- single side plasma etching of the PV cells using SF6 and O in a suitable ratio on the unmasked area;
- optimizing the operating parameters of plasma power, time of etching, gas ratios for texturing the non-printed area.
2. The method as claimed in claim 1, wherein Ag grid lines are not affected by selective thinning on the un-printed exposed areas.
3. The method as claimed in claim 1, wherein the printed electrical gridlines shield the wafers from getting selectively etched under it at the front part of the emitter region.
4. The method as claimed in any of the preceding claims, wherein the selective thinning of emitter increases sheet resistance to 70-80 Ω/□ in the exposed
textured area and 40-50 Ω/□ in under the grid lines which in turn reduces recombination at emitter and reduces contract resistance.
5. The method as claimed in claim 1, wherein ARC is deposited by using carriers for masking the grid lines in PECVD, thereby eliminating further printing and allowing easy soldering to other wafers to make a module.
6. The process as claimed in claim 5, comprising the step of depositing ARC on said surface increases efficiency to 0.4%.
7. The method as claimed in claim 5, comprising the step of depositing ARC on said surface increases efficiency to 0.4%.
8. The method as claimed in claim 1, which eliminates the step of screen printing and use of expensive wet chemicals.
| # | Name | Date |
|---|---|---|
| 1 | Power of Attorney [24-10-2016(online)].pdf | 2016-10-24 |
| 2 | Form 5 [24-10-2016(online)].pdf | 2016-10-24 |
| 3 | Form 3 [24-10-2016(online)].pdf | 2016-10-24 |
| 4 | Form 20 [24-10-2016(online)].pdf | 2016-10-24 |
| 5 | Drawing [24-10-2016(online)].pdf | 2016-10-24 |
| 6 | Description(Complete) [24-10-2016(online)].pdf | 2016-10-24 |
| 7 | Form 18 [31-10-2016(online)].pdf | 2016-10-31 |
| 8 | 201631036247-FER.pdf | 2020-01-02 |
| 9 | 201631036247-AbandonedLetter.pdf | 2024-07-12 |
| 1 | 201631036247table1_25-09-2019.pdf |