This invention relates to a programmable logic device including bi-directional shift register.
Background of the invention:
Conventional FPGAs consist of re-programmable Lookup tables which are used to implement functions of 'n' input, where 'n' depends on the Lookup Table size and the addressing scheme involved. Such a Lookup Table can normally implement 2^2^n logic functions. A logic function may or may not use all the inputs to the Lookup Table. A few of the logic functions that may be accommodated in the Lookup Table include AND, NAND, OR, NOR, XOR, XNOR and mixed combinations of these functions. It may also be desired to implement a shift register functionality within the logic element (Lookup Table) in order to maximize the flexibility of the Lookup Table.
In US patent no. 5,889,413 the Xilinx Inc. have defined a scheme for the Lookup Tables to be used as shift registers. The key elements that enable shift operation are a pass transistor/CMOS transmission gate and an inverter, which connect the latches in the Lookup Table structure. Although such an arrangement enables shift operation within the Lookup Table, it does so only in one direction. It does not have any provision for shifting the data bits in both the directions. This limits its usage to applications involving uni-directional shift operations. This prior art foils to accommodate applications involving bidirectional shift operations.
The object and summary of the invention:
The object of this invention is to provide programmable logic device including bi-directional shift register.
To achieve the said objective this invention provides a programmable logic
device comprising:
programmable interconnect structure,
a plurality of configurable logic elements including data latches interconnected by said interconnect structure, at least one of said configurable logic elements being configurable as both a shift register and a look up table, wherein said shift register comprising:
• first means for configuring said data latches either as series
connected inverters during shift operation or as data latches
after each shift operation,
• second means for selecting direction of shift, and
• third means for supplying data to the input of said shift
register as determined by direction of shifting for enabling
bi-directional operation.
The said first means are a first and second set of switches connected between the inverters of each said latch and between each latch and each subsequent latch in the selected direction of shifting in the shift register chain, the arrangement being such that the first set of switches connect the inverters as latches during normal operation, while during shift operation the second set of switches connect one inverter of each latch to an inverter of the subsequent latch for transfer of data.
The said switches are transmission gates.
The said second and third means are logic gates.
The said logic gates are pass transistors.
The said pass transistors are MOS transistors.
The programmable logic device further comprises control logic for controlling shifting when the configurable logic element is configured as a bi-direction shift register.
The said control logic comprising a user clock terminal for controlling shifting of data between plurality of said data latches.
The programmable logic device further comprises second control logic for controlling the configuration of logic elements as a bi-directional shift register.
The said second control logic comprising:
a first coupling means for coupling a data input terminal to either the first data latch or to the last data latch depending on the selected direction of shifting,
a second coupling means for coupling a data output terminal to the output of any of said data latches.
The said second coupling means are a plurality of selection means for selecting one or more of the output of said data latches as the final output.
The said selection means is a decoder.
The said logic devices are interconnected together to realize bi-directional shift register of length greater than the size of a single programmable device.
The said device includes look-up table.
Brief description of the drawings:
The invention will now be explained with reference to the accompanying drawings:
Fig. 1 shows the programmable logic device with bi-directional shift register, according to this invention using simple gates.
Figure 2 shows the programmable logic device with bi-directional shift register using transmission gates.
Figure 3 shows the block diagram of the programmable logic device for bidirectional shift register operation
Figure 4 shows sample wave-forms for a single down-shift sequence.
Detailed description of the drawings:
Referring to the drawings, figure 1 illustrates a preferred embodiment of the proposed architecture for the logic block. The read -write terminals and associated circuitry are not shown, and are well known to those skilled in the art.
Referring to figure 1, inverter pairs 7-8, 9-10, 11-12, 13-14 are a part of the Logic block structure that consists of many such inverter pairs extending in both directions. Thus, the inverter pair can be visualized as part of an inverter stack connected by pass transistors. When this Logic Block is used as a RAM or as a Lookup table without any shifting ability, LI & L2 pins are permanently pulled up and SI & S2 pins are permanently pulled down. The inverter pairs 7-8, 9-10, and others behave like latches as the feedback paths are closed. The inverter pairs mentioned through out this description are those inverter pairs, which are
usgd to latch data. In other words, the inverter pairs are those two inverters, which are connected by pass transistors having gate signals as LI an L2. The inverter pairs are carefully designed to minimize the static power dissipation in the inverters due to Vt drop of the NMOS pass transistors. The inverter pairs at the top and bottom of this stack may receive or output data bits depending on the mode of operation. Another embodiment is possible in which the pass transistors are replaced by CMOS transmission gates (figure 2). During configuration or RAM mode, the inverter latch pairs may be fed data from nodes la, Ib, etc. While using the logic block as a RAM, Lookup table or a shift register (explained later), the data may be read from the inverter pairs from nodes Ib, 2b, etc.
The data word on the address decoder for the lookup table determines the length of the shift register. The shift register length that can be implemented within a single lookup table is limited by the number of inverter pairs in the logic block. When the logic block is to be used as a shift register, a mechanism is described by which data in the lookup table, which is made of inverter pair latches, will shift into adjacent inverter pair latches when a shift signal, normally a clock, is applied. This shift signal is applied to a control logic block (figure 3) which generates the appropriate signals for data-shift. As will be seen, the control logic block can be designed in many ways by those skilled in the art. The inputs to the control logic block are the clock signal, the Shift enable signal and the up/down signal. A single shift operation is executed on applying the clock signal, provided the shift enable signal is at the correct level (high or low, depending on design). The shift enable signal initiates the shift mode operation of the lookup table. Further, an up/down signal determines the direction of data-shift. As will be appreciated by those skilled in the art, signals to the control logic block can be changed in real time, i.e. the post configuration period. This implies that a logic block can be used as an LUT, an up-shift register or a down shift register
evjsn after configuration. Thus, complex functionality involving dynamic operations may be implemented. Another advantage offered by the present invention is the simplification of the placement & routing tools. The input to output direction constraint while placement of a shift register is eliminated. This is so because of the availability of the data input port of the shift register on either side of the look up table.
In order to realize shift registers of length greater than the Lookup table size, the invention also provides an array of such programmable blocks, interconnected through an interconnection, which may be programmable. The interconnection would link all such programmable blocks so as to form a chain of inverter pairs. For a better understanding of the present invention, and to show how the same may be carried into effect is described below:
Referring to fig. 1, a programmable logic block comprises of a plurality of inverters and pass transistors inter-connected as shown. This programmable logic block basically consists of 'n' latches, where n stands for the number of bits that can be stored in the programmable logic block. The latches are formed by inverter pairs and connecting pass transistors. Data is written into the latches through an addressing scheme and read in a similar manner. Any addressing scheme may be used, which is well known to all skilled in the art, and is not shown here. Data is directly written into the latches normally during configuration, RAM write mode operation, or shift operation. Data is read from the latches normally during RAM read mode operation, lookup table operation or shift operation. During configuration, RAM mode, lookup table operations, data is normally read/written depending on the word on the address line. In shift mode write operation, data is written either into the topmost latch in the stack or into the bottom most latch in the stack. Data is read through the addressing scheme for the look up table during shift mode read operation.

The following best describes the operation of the proposed logic block as a shift register:
1. Depending on the operation desired, latches in the logic block may or
may-not be configured during configuration.
2. The word on the address line determines the length of the shift register.
The word may be static or dynamic depending on the type of application.
The input latch (at the top or bottom) and the latch which is addressed
define the boundaries of the shift register and the shift register length is
the total number of latches between the input latch (at the top or bottom)
and the latch which is addressed, with both the afore-mentioned boundary
latches included.
3. The shift operation may be visualized as a FIFO(First In First Out)
operation with the input latch (at the top or bottom) as the input port and
the LUT output as the output port.
4. The shift operation is executed only if there is a clock input and a shift
enable signal to the control block. The control block generates the
necessary waveforms for the shift operation, depending on the up/down
shift signal.
5. Waveforms displayed in figure 5 delineate a single down-shift sequence
operation for the shift register type look up table in figures 1 & 2.
Consider a single down-shift operation. Referring to figs. 1 & 2, it implies that data stored in the latch formed by inverters 7 & 8 has to be shifted into the latch formed by inverters 9 & 10. A clock signal (with shift enable active) initiates the shifting process.
Now, referring to figure 4, LI & L2 are pulled down with the arrival of the clock signal. This follows the going high of SI. SI is kept high till the adjacent
inverter (inverter 10) below the present one (inverter 9) stabilizes it's output. Once data is passed on to the inverter below, SI goes low and L2 goes high. LI goes high after the data has well settled into inverter 10.
The control logic block generates LI, L2, SI, S2, and Writepulse. During configuration the control block ensures that all LI, L2 are high, all SI, S2 are low & the pass transistors (for data) at the top & bottom of the inverter stack are off. Thus, a novel logic block structure with bi-directional shifting capability is described.

We Claim:
1. A programmable logic device comprising:
programmable interconnect structure,
a plurality of configurable logic elements including data latches interconnected by said interconnect structure, at least one of said configurable logic elements being configurable as both a shift register and a look up table, wherein said shift register comprising:
• first means for configuring said data latches either as series
connected inverters during shift operation or as data latches
after each shift operation,
• second means for selecting direction of shift, and
• third means for supplying data to the input of said shift
register as determined by direction of shifting for enabling
bi-directional operation.

2. The programmable logic device as claimed in claim 1 wherein said first
means are a first and second set of switches connected between the
inverters of each said latch and between each latch and each subsequent
latch in the selected direction of shifting in the shift register chain, the
arrangement being such that the first set of switches connect the inverters
as latches during normal operation, while during shift operation the
second set of switches connect one inverter of each latch to an inverter of
the subsequent latch for transfer of data.
3. The programmable logic device as claimed in claim 2 wherein said
switches are transmission gates.
4. The programmable logic device as claimed in claim 1 wherein said
second and third means are logic gates.
5. The programmable logic device as claimed in claim 4 wherein said logic
gates are pass transistors.
6. The programmable logic device as claimed in claim 5 wherein said pass
transistors are MOS transistors.
7. The programmable logic device as claimed in claim 1 further comprising
control logic for controlling shifting when the configurable logic element
is configured as a bi-direction shift register.
8. The programmable logic device as claimed in claim 7 wherein said
control logic comprising a user clock terminal for controlling shifting of
data between plurality of said data latches.
9. The programmable logic device as claimed in claim 1 further comprising
second control logic for controlling the configuration of logic elements as
a bi-directional shift register.
10. The programmable logic device as claimed in claim 9 wherein said
second control logic comprising:
a first coupling means for coupling a data input terminal to either the first data latch or to the last data latch depending on the selected direction of shifting,
a second coupling means for coupling a data output terminal to the output of any of said data latches.
11. The programmable logic device as claimed in claim 10 wherein said
second coupling means are a plurality of selection means for selecting
one or more of the output of said data latches as the final output.
12. The programmable logic device as claimed in claim 11 wherein said
selection means is a decoder.
13. The programmable logic device as claimed in claim 1 wherein said logic
devices are interconnected together to realize bi-directional shift register
of length greater than the size of a single programmable device.
14. The programmable logic device as claimed in claim 1 wherein said
device includes look-up table.
15. The programmable logic device substantially as herein described with
reference to the accompanying drawings