Abstract: ABSTRACT A PROTECTED OR-LOGIC DEVICE The invention provides a protected OR-logic device. The device includes a substrate, a plurality of resistors formed on the substrate, at least one diode mounted in series combination with each of the resistors formed, a plurality of channels created from the resistor-diode series combination and an cavity for housing the created channels to obtain the protected OR-logic device. Each channel includes at least one input and at least one output.
Claims:We claim:
1. A protected OR-logic device comprising:
a substrate;
a plurality of resistors formed on the substrate;
at least one diode mounted in series combination with each of the resistors formed;
a plurality of channels created from the resistor-diode series combination, wherein each channel comprises of at least one input and at least one output; and
a cavity for housing the created channels to obtain the protected OR-logic device.
2. The device according to Claim 1, wherein the substrate is at least one conducting material selected from a list comprising of an Alumina, an Aluminium Nitride and a Beryllia.
3. The device according to Claim 1, wherein the resistors are formed using atleast one technique selected from a list comprising of an imprinting, a 3-D printing, a screen printing, a thick film printing and an etching.
4. The device according to Claim 1, wherein the resistors can be in a series combination, a parallel combination or a combination thereof.
5. The device according to Claim 1, wherein the diodes are mounted using at least one technique selected from a list comprising of a surface mount, a flush mount, a stud mount, an epoxy mount and a solder mount.
6. The device according to Claim 1, wherein the diodes can be in a series combination, a parallel combination or a combination thereof.
7. The device according to Claim 1, wherein the channels are created using at least one technology selected from a list comprising of a thick film technology and a PCB technology.
8. The device according to Claim 1, wherein the channel configuration can be a common cathode configuration, a common anode configuration or a combination thereof.
9. The device according to Claim 1, wherein the channels are cavity is a hermetically sealed package.
10. The device according to Claim 1, wherein the protected OR-logic device is a Hybrid Micro Circuit device.
Bangalore NARENDRA BHATTA HL
31 December 2016 (INTELLOCOPIA IP SERVICES)
AGENT FOR APPLICANT
, Description:A PROTECTED OR-LOGIC DEVICE
FIELD OF INVENTION
The invention generally relates to the field of Hybrid Micro Circuits and particularly to a protected OR-logic device.
BACKGROUND
OR-logic is an integral part of an electronic circuitry. A primary function of the OR-logic is to add the input signals. One system known in the art provides an OR-ing protection circuit. The OR-ing protection circuit includes discrete active components and passive components assembled on a Printed Circuit Board, hereinafter referred to as PCB. The assembled components constitute a single channel. Generally, several such single channels are distributed at different regions of the PCB. Each of these channel are capable of providing one output. It is difficult to add up the signals generated at each of the channel. Further, regulating the functioning of the distributed ORing protection circuit is difficult. Additionally, the assembled components occupy more space and make the PCB bulkier. Moreover, the system requires a separate package for every channel, which eventually increases the space on PCB. Hence there is a need for an integrated ORing circuit that is capable of adding up signals efficiently.
BRIEF DESCRIPTION OF DRAWINGS
So that the manner in which the recited features of the invention can be understood in detail, some of the embodiments are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG.1 shows a schematic representation of a plurality of resistors formed on the substrate, according to an embodiment of the invention.
FIG.2 shows a schematic representation of a plurality of diodes mounted in combination with the resistors, according to an embodiment of the invention.
FIG.3 shows a schematic representation of a plurality of channel created from the resistor-diode combination, according to an embodiment of the invention.
FIG.4 shows an exploded view of the protected OR-logic device, according to an embodiment of the invention.
SUMMARY OF THE INVENTION
One aspect of the invention provides a protected OR-logic device. The device includes a substrate, a plurality of resistors formed on the substrate, at least one diode mounted in series combination with each of the resistors formed, a plurality of channels created from the resistor-diode series combination and an cavity for housing the created channels to obtain the protected OR-logic device. Each channel includes at least one input and at least one output.
DETAILED DESCRIPTION OF THE INVENTION
Various embodiments of the invention provide a protected OR-logic device. The device includes a substrate, a plurality of resistors formed on the substrate, at least one diode mounted in series combination with each of the resistors formed, a plurality of channels created from the resistor-diode series combination and an cavity for housing the created channels to obtain the protected OR-logic device. The device described herein briefly shall be explained in detail.
FIG.1 shows a schematic representation of a plurality of resistors 2 formed on the substrate 1, according to an embodiment of the invention. The protected OR-logic device includes a substrate. The substrate described herein is a conducting material. Example of conducting material includes but is not limited to an alumina, an aluminium nitride and a beryllia. A plurality of resistors is formed on the substrate. The resistors are formed using a technique that includes but is not limited to an imprinting, a 3-D printing, a screen printing, a thick film printing and an etching. The resistors formed can be a single resistor or a combination of resistors. Further, the combination of the resistors can be a series combination, a parallel combination or a combination thereof. Upon formation of the resistors 2 on the substrate, a plurality of diodes 3 is mounted on the substrate.
FIG.2 shows a schematic representation of the plurality of diodes 3 mounted in combination with the resistors 2, according to an embodiment of the invention. Each of the diodes 3 is mounted using a technique that includes but is not limited to a surface mount, a flush mount, a stud mount, an epoxy mount, a solder mount or a combination thereof. Further, each of the diodes 3 can be in a series combination, a parallel combination or a combination thereof. A plurality of channels is created from the resistor-diode series combinations. Each channel has at least one input and at least one output. In one example of the invention, the channels are created using a thick film technology. Alternatively, the channels can be created using a PCB technology.
FIG.3 shows a schematic representation of a channel created from the resistor-diode combination, according to an embodiment of the invention. In one specific example of the invention, a channel constitutes two resistor diode combinations with the diodes in a common cathode configuration. Further, the channel has two inputs and a single output. Alternatively, the channels can be formed with a common anode configuration. A plurality of channels, each formed in a manner as described herein above, is created. In one example of the invention, six channels are created. Each channel has at least one input and at least one output. Further, the plurality of channels formed can have all the channels in a common cathode configuration, a common anode configuration or a combination thereof.
FIG.4 shows an exploded view of the protected OR-logic device, according to an embodiment of the invention. Subsequent to the creation of the channels, the channels are enclosed in an cavity 4 to obtain the protected OR logic device. The cavity 4 is a hermetically sealed package. The cavity 4 is provided with a plurality of contact pins 5 on either side of the cavity, for establishing electrical connection. Each of the contact pins can be selected for input and drawing an output. The selection of the input and the output determines the net output of the device, in terms of signal. For example, in a six channel OR logic device, it is desirable to have six outputs with six pairs of input, wherein each pair of input corresponds to an output.
Thus, the invention provides a protected OR-logic device with reduced mass, volume and dimension. The protected OR-logic device offers high reliability in extreme environmental conditions. Further, the device has ability of ORing signals with inbuilt protection. The invention finds its application in high speed switching applications. The protected OR logic device described herein is a Hybrid Micro Circuit device.
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.
| # | Name | Date |
|---|---|---|
| 1 | PROOF OF RIGHT [31-12-2016(online)].pdf | 2016-12-31 |
| 2 | Power of Attorney [31-12-2016(online)].pdf | 2016-12-31 |
| 3 | Form 5 [31-12-2016(online)].pdf | 2016-12-31 |
| 4 | Form 3 [31-12-2016(online)].pdf | 2016-12-31 |
| 5 | Drawing [31-12-2016(online)].pdf | 2016-12-31 |
| 6 | Description(Complete) [31-12-2016(online)].pdf_384.pdf | 2016-12-31 |
| 7 | Description(Complete) [31-12-2016(online)].pdf | 2016-12-31 |
| 8 | Form 9 [15-03-2017(online)].pdf | 2017-03-15 |
| 9 | Form 18 [15-03-2017(online)].pdf | 2017-03-15 |
| 10 | 201641045196-FER.pdf | 2019-12-23 |
| 11 | 201641045196-Retyped Pages under Rule 14(1) [23-06-2020(online)].pdf | 2020-06-23 |
| 12 | 201641045196-OTHERS [23-06-2020(online)].pdf | 2020-06-23 |
| 13 | 201641045196-FER_SER_REPLY [23-06-2020(online)].pdf | 2020-06-23 |
| 14 | 201641045196-DRAWING [23-06-2020(online)].pdf | 2020-06-23 |
| 15 | 201641045196-COMPLETE SPECIFICATION [23-06-2020(online)].pdf | 2020-06-23 |
| 16 | 201641045196-2. Marked Copy under Rule 14(2) [23-06-2020(online)].pdf | 2020-06-23 |
| 17 | 201641045196-PatentCertificate02-11-2023.pdf | 2023-11-02 |
| 18 | 201641045196-IntimationOfGrant02-11-2023.pdf | 2023-11-02 |
| 19 | 201641045196-FORM FOR SMALL ENTITY [15-11-2023(online)].pdf | 2023-11-15 |
| 20 | 201641045196-EVIDENCE FOR REGISTRATION UNDER SSI [15-11-2023(online)].pdf | 2023-11-15 |
| 21 | 201641045196-POA [11-03-2025(online)].pdf | 2025-03-11 |
| 22 | 201641045196-FORM-26 [11-03-2025(online)].pdf | 2025-03-11 |
| 23 | 201641045196-FORM 13 [11-03-2025(online)].pdf | 2025-03-11 |
| 1 | 2019-12-1815-41-07_18-12-2019.pdf |