This invention relates to a real time matched complementary speed control system By
way of example but without implying any • limitation thereto, the speed control device may be used with a draw frame, such as described in copending patent application no. 535/DEL/95. However, it is to be understood that the speed control device may also be used for controlling the speed of any other slave unit
The draw frame of copending patent application no. 535/DEL/95 comprises.
(a) a pre-draw zone having a plurality of set of rollers-and wherein, each set of
rollers comprising a pair of rollers.
(b) a draw zone having a plurality of pair of rollers and wherein each pair of
rollers rotates at a speed different to the pairs of rollers in said draw zone.
(c) A convergence zone and draw zone for converging of the predrafted slivers
(d) Motive means for driving said rollers. A controller is provided for controlling
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the speed of said rollers.
An object of this invention is to propose a device to control the speed of a slave units.
According to this invention there is provided a real time matched complementary speed
control system comprising plurality of dc motors (Mi, M2, ) with one motor
provided for each of said slave unit, wherein speed of each motor is controlled by
controller circuits (COi, CCh ) having a dc-dc chopper power circuit and an
interface circuit wherein said interface circuit comprises a digital to analog converter which converts digital signal from micro-computer to analog signal applied to a comparator, a triangular reference signal also being fed to comparator by a function generator and output of the said comparator being applied to an opto-isolator providing isolation between said interface circuit and chopper circuit, wherein further said chopper circuit comprises a motor (M) having a free wheeling diode (DO across it, resistance Riz connected to transistor Qi, second transistor Q2 having a snubber circuit consisting of capacitor C& in series with a resister Ru and a Diode Di across the said transistor wherein the system of the present invention is characterized in that a single micro-controller is
connected to each of said controllers (COi, CCh ) which provides signals to the
said controllers after processing the speed reference and feed back signals where the speed references are obtained from the background processor (PC) which derives the speed of individual motor by a pattern blending algorithm and speed feed back signals obtained from the speed sensing means for each of the said motors.
In accordance with this invention the speed control device comprises a control circuit for each of the slave units the control circuit being connected to a central processing unit. A sensor is provided for each motor so as to sense the speed of each motor, said sensors being connected to a central processing unit. The central processing unit is connected to a computer.
The dc chopper control circuit provides variable dc voltage to the armature circuit of the
separately excited dc motor, which operates with constant field excitation. The chopper
circuit uses power bipolar junction transistor, which is operated in common emitter mode.
The interface circuit
provides a current (voltage) drive in the base (gate) circuit of the chopper transistor (Power WOSPET or I GET). the base input to the chopper transistor is provided toy a comparator circuit with a current isolator interface. The comparator can generate the chopper duty ratio by comparing a reference triangle wave-form generated by a triangle wave generator circuit with the processed speed error signal obtained frow the tnicro*computer stage*
Further objects ana advantages of thia invention vill be more apparent from the ensuing description 'when read in conjunction with the accompanying drawings and wherein:
Fig. 1 shows a block diegra* of the speed control device of the present invention)
Fig, 2 shows the chopper circuit! and
Fig. 3 shove the interface circuit.
Referring to the drawings. the slave units as by way of example coaprlsea rollere Rl to R4. Roller R1 is drawn by a first tnotor Ml. roller R2 by a second notor m2 roller R3 by a third motor M3 and roller R4 by a fourth notor m4.
moter ml,m2,M3 and M4 are ac motors whlch are individually controlled by a control circuit having a controller Co with a dc-dc chopper power circuit as shown in Fig.2. The speed of tnotors Ml to M is controlled by controller Col to Co4
respectively which receives signal from a central processing unit, such as a microcomputer MO. The micro-computer MC provides the actuating signal to the drive motor by processing the speed feedback signal from sensors and the reference command obtained from a personal computer PC connected as background processor to the microcomputer.
Each of the controller circuits Col to Co4 has a chopper circuit of Fig.3 and a inteface circuit of fig. 3
The chopper circuit of Fig.3 comprises said motor having a free wheeling diode DI across it. The motor has a fixed excitation field winding (not shown), the average voltage across
said motor is controlled to regulate the speed of said motor. Thus, for higher speeds we
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require higher voltages Resistor R]2 is connected to the base of transistor Q], a signal being applied to resistor Rn from an opto-isolator OP, such an opto-isolator OP is required as chopper circuit of Fig.2 operates at 220V and carries 5 amps, whereas, the interface circuit of Fig 3 operates at a low voltage at 5V and carries a current in the value of milliamps. Thus, opto-isolator OP provides a physical isolation between the chopper circuit of Fig. 3 and the interface of Fig 3.
The copper circuit of Fig.3 further comprises a second transistor Q2 having a snubber circuit consisting of a capacitor C6 in series with a resistor R14, and a diode D2 across said resistor. Transistor has a discharging resistor R13.
When no input current is present at resistor R12, the voltage across said motor is low or 0. When a high pulse is given to provide a sufficient base current to transistor Ql, the voltage across transistor Q2 reduces to saturation voltage. Thus, from a high initial voltage across transistor Q2, it goes down to saturation voltage, which is low so that the entire voltage appears across said motor.
The signal to the chopper circuit of Fig.2 is derived from the interface circuit of Fig.3. The interface circuit comprises a digital analogue converter DAC, which converts a digital signal from the micro computer MC to an analog signal A applied to a comparator CT. The reference signal to comparator CT is fed from a function generator FG. The output of comparator CT is applied to opt-isolator OP.

WE CLAIM;
1 A real time matched complementary speed control system comprising:-
(i) plurality of dp motors (M1, M2, .) with one motor provided for
each of said slave unit, wherein speed of each motor is controlled by
controller circuits (CO1, CO2 ) having a dc-dc chopper power
circuit and an interface circuit wherein said interface circuit comprises a digital to analog converter which converts digital signal from microcomputer to analog signal applied to a comparator, a triangular reference signal also being fed to comparator by a function generator and output of the said comparator being applied to an opto-isolator providing isolation between-said interface circuit and chopper circuit, wherein further said chopper circuit comprises a motor (M) having a free wheeling diode (D1) across it, resistance Riz connected to transistor Q1, second transistor Q2 having a snubber circuit consisting of capacitor C6 in series with a resister R14 and a Diode D2 across the said transistor wherein the system of the present invention is characterized in that a single micro-controller is connected to each of
said controllers (CO1, CO2 ) which provides signals to the said
controllers after processing the speed reference and feed back signals where the speed references are obtained from the background
processor (PC) which derives the speed of individual motor by a pattern blending algorithm and speed feed back signals obtained from the speed sensing means for each of the said motors.
2. A real time matched complementary speed control system substantially as herein described and illustrated