A Reconfigurable And Scalable Multi Core Analogcomputing Chip

Abstract: A RECONFIGURABLE AND SCALABLE MULTI-CORE ANALOG COMPUTING CHIP ARCHITECTURE AND A SYSTEM THEREOF ABSTRACT Present disclosure discloses a multi-core reconfigurable analog computing chip architecture and a system thereof. The multi-core reconfigurable analog computing chip architecture comprises a plurality of Generalized Margin Propagation (GMP) based computational cores electrically connected with each other to form a multi-core reconfigurable analog computing chip. Each of the plurality of GMP-based computational cores comprises an interconnected matrix of computational tiles. Each computational tile comprises of a Shape-based Analog Compute (S-AC) unit electrically connected to an associated S-AC based Digital to Analog Converter (DAC). Each row in the interconnected matrix of computational tiles is electrically 15 connectable to an individual input current source or a common input current source, and each column in the interconnected matrix of computational tiles is electrically connectable to an associated output transistor unit to implement GMP mapped mathematical operation. Fig. 1a

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