DESC:A ROBUST CMOS MILLER OPAMP WITH 5 MV OUTPUT OFFSET VOLTAGE

FIELD OF THE INVENTION
The present invention relates to Miller operational amplifiers (OpAmps) and in particular to a CMOS Miller OpAmps which are robust and more immune to EMI disturbances.
BACKGROUND
Nowadays, the electronic gadgets or devices are widely used for various purposes including communication, entertainment, measurement etc. such electronic devices are available in compact size, and due to which, high density of the components are mounted on printed circuit boards being used in the devices. The compact electronic devices generally face failures caused by EMI disturbances. Therefore, designing highly EMI-immune integrated circuits has become a key challenge. Most of the electronic devices includes CMOS operational amplifiers (OpAmps) in their circuits, however, such OpAmps are particularly sensitive to EMI disturbances. When an EMI component gets injected in an input signal, it introduces a DC offset voltage at the output.

The prior art CMOS operational amplifiers are implemented with different solutions in order to overcome the effects of EMI disturbances along with the input signal. These solutions try to overcome the aforesaid problem by using filtering, cancellation, source-buffering or replication at the input of a CMOS operational amplifier. The prior art also presents a cross-coupled differential pair that achieves better EMI immunity when compared to a conventional differential amplifier. However, such differential circuit is prone to mismatch when the AC drain currents are subtracted.

In order to overcome the above problems, an RC low-pass filter may be placed in front of the differential amplifier of the CMOS OpAmp so that an out of band EMI can be attenuated. However, the disadvantage of such technique is that the common-mode and differential-mode input voltages are attenuated at the input pair of the CMOS OpAmp. The RC low pass filter further adds an additional pole that drastically degrades the unity gain frequency (UGF) and the stability.

Therefore, a modified operational amplifier is required that provides high immunity to the EMI disturbances, so as to reduce the output offset voltage over a wide range of operating frequencies. Thus, an improved OpAmp is required that renders reduced output offset voltage with a better unity gain frequency (UGF) and stability.
OBJECTIVE OF THE INVENTION
The objective of the invention is to design a CMOS Miller operational amplifier with high immunity to EMI disturbances, therefore providing reduced output offset voltage over a wide range of frequencies.

Another objective of the invention is to design a CMOS Miller operational amplifier with reduced output offset voltage over a wide range of frequencies with higher stability.
SUMMARY
In an implementation a high EMI immunity CMOS miller operational amplifier (100) is disclosed. The system comprises two CMOS differential circuits (110, 120) comprising a first CMOS differential circuit (110) and a second CMOS differential circuit (120) with an inverting input and a non-inverting input, wherein an output node of the first differential CMOS circuit(110) is connected to the outer differential circuit (120). Further system comprises at least one low pass filter (130) connected between the first CMOS differential circuit (110) and the second CMOS differential circuit (120). The amplifier further comprises a back-biasing circuit (140) connected to the inverting input and the non-inverting input of the second CMOS differential circuit (120). The system further comprises a current source connected with a plurality of transistors, wherein the plurality of transistors are connected to the first CMOS differential circuit (110), the second CMOS differential circuit (120) the back-biasing circuit (140). The amplifier further comprises a series RC circuit connected at an output node of the outer differential circuit (120).
BRIEF DESCRIPTION OF DRAWINGS
Figure 1 illustrates one of the exemplary embodiment of the proposed Miller operational amplifier in the form of a detailed circuit level diagram (hereinafter referred as a Miller OpAmp).
Figure 2 illustrates CMOS Miller OpAmp comparison with the conventional Miller OpAmp.
Figure 3 illustrates a graph plotted through a simulation using a Spectre simulator in accordance with the present disclosure.
Figure 4 illustrates a Modified replica of the Miller OpAmp in accordance with the present disclosure.
Figure 5 illustrates a comparison of the modified replica Miller OpAmp with a conventional Miller OpAmp.
Figure 6 illustrates the comparison of output offset voltage for an EMI signal of 900 mVpp.
Figure 7 illustrates a circuit diagram of the source buffered Miller OpAmp with source degeneration resistance.
Figure 8 illustrates a comparative table between Source-buffered Miller OpAamp and a conventional Miller OpAmp.
Figure 9 illustrates a graph generated using a Spectre simulator.
Figure 10 illustrates a graph that compares the performance of all the aforesaid OpAmps over the given range of frequency band.
DETAILED DESCRIPTION OF THE INVENTION
A method and apparatus are described for facilitating a high EMI immunity CMOS miller operational amplifier. The proposed operational amplifier comprises an inner differential circuit and an outer differential circuit, the differential circuit in each amplifier is a CMOS differential circuit. The inner differential circuit drives the outer differential circuit. The operational amplifier further comprises at least one low pass filter between the inner and outer differential circuit. The inner differential circuit also comprises a pair of transistors connected in cascade configuration to the pair of transistors of the inner differential circuit. Each transistor of the pair of transistors is configured as a diode connected transistor for providing low capacitance at the output node of the inner differential circuit. The output from the output node of the inner differential circuit is given to the outer differential circuit. The outer differential circuit also comprises at least one transistor connected in cascade configuration to one of the transistors of the outer differential circuit, which is also further configured as diode connected for providing low impedance path for common-mode EMI disturbances, in order to provide output of the operational amplifier free from the EMI disturbances. The aforesaid Miller operational amplifier is further provided with a back-biasing circuit with source degeneration resistance, in order to reduce output offset voltage over a wide range of frequencies whereas the offset voltage is due to the EMI disturbances.

The method is further described below with respect to various detailed circuit diagrams. However, it will be apparent, to one of an ordinary person skilled in the art that the present invention may be implemented without such specific details. In other instances, well-known structures and techniques have not been described in detail in order not to unnecessarily obscure the present invention.

Figure 1 illustrates one of the preferred embodiment of the proposed Miller operational amplifier in the form of a detailed circuit level diagram (hereinafter referred as a Miller OpAmp). The Miller OpAmp circuit (100) comprises two CMOS differential circuits (110, 120) having a first sub circuit and a second sub circuit with an inverting and non-inverting input terminals for receiving the corresponding input signals. The first sub circuit is an inner CMOS differential circuit (110) (hereinafter referred as inner differential circuit) and the second sub circuit is an outer differential circuit (120) (hereinafter referred as outer differential circuit). The inner differential circuit (110) drives the outer differential circuit. The inner differential circuit (110) comprises a differential pair of NMOS transistors M1a and M2a along with a differential pair of PMOS transistors M3a and M4a. One of transistor of the inner differential circuit can be realized as a diode connected transistor. Transistors M1a and M3a are connected in a cascade configuration. In the same way, Transistors M2a and M4a are connected in a cascade configuration Similarly, the outer differential circuit (120) comprises a differential pair of NMOS transistors M1 and M2 and a differential pair PMOS transistors M3 and M4, which are configured in a cascade connection as shown in figure 1. one of transistor of the outer differential circuit can also be realized as a diode connected transistor. In one implementation, the transistor M3 is configured as a diode connected transistor. The Miller OpAmp circuit further comprises two RC low filters (130) (low pass filters) connected between the inner differential circuit (110) and outer differential circuit (120) as shown in the Figure 1. The outer differential circuit also comprises couple of source degeneration resistors Rs for providing source biasing Vs to the pair of transistors M1 and M2 respectively. The outer differential circuit is back biased by a back-biasing circuit (140) that comprises a pair of transistors M1b and M2b, where the source terminal of the pair of transistors M1b and M2b is connected to a common substrate terminal of the outer differential circuit at node Vsb as shown in the figure 1. Thus, the Miller OpAmp is represented as a source-buffered Miller OpAmp. The circuit (100) further comprises NMOS transistors MBIAS, M5a, M5, M5b, M6 and M7 connected with a current source IBIAS. Transistors M5a, M5 and M5b are configured as current source transistors and connected to the inner differential circuit (110), outer differential circuit (120) and back-biasing circuit (110) respectively. The output node of the outer differential circuit (120) is connected with a series RC circuit (resistor RZ and capacitor CC in series) for improving the stability of the overall output (Vout) of the circuit at wide range of frequency.

The proposed Miller OpAmp is formed by combining a replica Miller OpAmp and a source buffered differential amplifier with source degeneration. The replica Miller OpAmp is formed by the inner differential circuit and outer differential circuit. The replica Miller OpAmp is further modified by configuring the transistors M4a and M3 as diode connected. The source buffered differential amplifier with source degeneration is formed by the replica Miller OpAmp along with the back-biasing circuit. Therefore, specification of the invention may be further described into two stages, i.e. the replica Miller OpAmp and another one is the source buffered differential amplifier with source degeneration.

A. Modified replica Miller OpAmp:
Referring to the circuit diagram as shown in the figure 4. The figure illustrates a Modified replica Miller OpAmp that comprises an inner differential circuit and an outer differential circuit along with respective pairs of transistors M1a, M2a, M3a, M4a, M1, M2, M3 and M4 in similar configuration as illustrated in figure 1. The term replica implies that the inner differential circuit is replicated by the outer differential circuit. As described in figure 1, the Modified replica Miller OpAmp also comprises two RC filters connected between the inner differential circuit sand outer differential circuit at the inverting terminal and non-inverting terminal respectively. The output of the inner differential circuit is applied to the outer differential circuit. The inverting terminal receives an input signal that may be a sinusoidal signal. The input signal may contain an unwanted common mode EMI disturbance. Such EMI disturbances may further produce an output offset voltage due to a finite output impedance and mismatch present between the aforesaid transistors. The EMI disturbances present in the input signal are rejected by the RC filter and finds a low impedance path through the transistor M3a towards the transistor M4 of the outer differential circuit. Since the transistor M4a is configured as a diode connected transistor, a very low capacitance is provided at node Vx. Similarly, the non-inverting terminal receives an input signal that may be a sinusoidal signal and may contains an unwanted common mode EMI disturbance. One of transistor of the outer differential circuit is configured as a diode connected transistor to provide a low impedance path to the common mode EMI disturbances present in the input signal received at the non-inverting terminal. The NMOS transistors M5a and M5 are configured as current source transistors for the inner differential circuit and outer differential circuit respectively as discussed in Figure 1.

The transistors M3a and M4a of the inner differential circuit act as active loads, connected in cascade configuration to the respective transistor of the differential pair transistors M1a and M2a as similar to the figure 1. The transistors M3a and M4a help in compensating miller capacitance of the differential pair transistors M1a and M2a. Similarly, the transistors M3 and M4 of the outer differential circuit also act as active load and connected in cascade configuration to the respective transistor of the differential pair transistors M1 and M2 thereby to provide compensation of miller capacitance of the differential pair transistors M1 and M2.

Figure 5 shows the comparison of the modified replica Miller OpAmp with a conventional Miller OpAmp in a tabular form. The dimensions of the transistors in the modified replica Miller OpAmp are kept identical to those in the conventional one. The table shows that the modified replica Miller OpAmp provides better frequency response as compared to the classical Miller OpAmp. The Figure 6 shows the comparison of output offset voltage when an EMI signal of 900 mVpp is applied at the input. Thus, the modified miller OpAmp delivers greater performance with more immunity to EMI signal and produces an output offset as low as less than 10mV upto 200 MHz. The output offset voltage of the modified replica Miller OpAmp as well as the conventional Miller OpAmp is plotted against a range of frequency in a graph (obtained using Spectre simulator) as shown in figure 6 with 900 mVpp of EMI signal is applied at the input. The graph shows the improved performance of the modified replica Miller OpAmp over the standard Miller OpAmp, since the modified replica Miller OpAmp produces comparatively lower output offset voltage.

B. Source buffered differential amplifier with source degeneration:
Now referring to Figure 7 for the circuit diagram of the source buffered Miller OpAmp with source degeneration resistance. The circuit comprises a Miller OpAmp with a back-biasing circuit and source degeneration resistors and as also described previously. The Miller OpAmp comprises a differential pair of NMOS transistors M1 and M2 along with a pair of PMOS load transistors M3 and M4 and a current source transistor M5 as shown in the figure. The pair of transistors M1 and M2 of the miller OpAmp are back-biased by a back-biasing circuit formed by an auxiliary differential pair of transistors M1b and M2b along with a current source transistor M5a as shown in the figure 7. The back-biasing circuit bootstraps the bulk-source voltage of transistors M1 AND M2 and keeps the average drain current of M1 and M2 at a constant value. The output offset voltage due to the input common mode EMI disturbance component can be minimized by reducing the magnitude of the transfer function of the input common mode EMI disturbance to the sources of the differential pair of transistors M1 and M2. The transfer function can be given as below:
H(?)=(j?C_T1)/(2gm1+j?(C_T1+2C_gs1)) …………...…….. (1)
Where, 2Cgs1 is the gate to source capacitance of the transistor pair M1 and M2; and
2Gm1 is the conductance of the transistor pair M1 and M2.

Since the magnitude of the transfer function H(w) can be reduced by increasing the denominator of the equation 1. The back-biasing circuit provides an additional capacitance in parallel to the gate to source capacitance 2Cgs1, where the additional capacitance is produced by the parasitic capacitance from the transistors M1b, M2b and the current source transistor M5a. The additional capacitance so produced by the back-biasing circuit increases the denominator of the equation 1 and therefore the magnitude of the transfer function H(w) is reduced.

The circuit further comprises source degeneration resistors Rs connected to the sources of transistors M1 and M2 respectively, and a load capacitor CL connected at the overall output (Vout). The source degeneration resistors provides negative feedback to the transistors M1 and M2 for controlling the gate to sources voltages of the transistors M1 and M2. Thus, improves the linearity.

Figure 8 represents the comparative table that compares Source-buffered Miller OpAamp with source degeneration resistance against a conventional Miller OpAmp. Here also the dimensions of the transistors in the modified replica Miller OpAmp are kept identical to those in the conventional one for fair comparison. The table shows that the Source-buffered Miller OpAamp with source degeneration resistance provides lower output offset voltage as compared to the classical Miller OpAmp. Here also, an EMI signal of 900mVpp is applied at the input and output of both the OpAmps is measured to derive various parameters as shown in Figure 8. Figure 9 illustrates a graph that is generated by using a Spectre simulator. The graph clearly shows that the Source-buffered Miller OpAamp with source degeneration resistance produces reduced output offset voltage over a wider range of frequency.

C. Proposed Miller OpAmp:
Refereeing back to figure 1 that illustrates the circuit diagram of the proposed CMOS Miller OpAmp. The combination of the modified replica Miller OpAmp with the Source buffered Miller OpAmp and source degeneration resistance results in the proposed CMOS Miller OpAmp as represented by the circuit. The CMOS Miller OpAmp provides a reduced output offset voltage over a wide range of frequencies, i.e. from 10 MHz to 1 GHz.

The circuit comprises a first stage of the new CMOS miller OpAmp that comprises the modified replica Miller OpAmp as represented in figure 4. The circuit further comprises a second stage that comprises the back-biasing circuit along with the modified replica Miller OpAmp and source degeneration resistors Rs.

The functioning of the first stage of the proposed CMOS Miller OpAmp is similar to the modified replica miller OpAmp as illustrated in figure 4. The circuit receives an inverting and non-inverting signal at the inverting and non-inverting terminal respectively. The non-inverting signal is coupled from the outer differential circuit to the inner differential circuit through the RC filter that rejects the out of band common mode EMI disturbance signal. The filtered signal is further coupled to the transistor M4 through the transistor M3a. The load transistor M4a is configured as diode connected that results in low capacitance at node Vx. Similarly, the inverting signal is coupled to the corresponding inverting terminal of the circuit that may also contain the common mode EMI disturbance signal. The transistor M3 is also configured as diode connected that provides a low impedance path for the differential mode as well as common mode EMI disturbance signal. Thus, the non-inverting signal and inverting signal meet at the output terminal of the circuit having reduced offset voltage.

The circuit further comprises the second stage that combines the aforesaid modified replica Miller OpAmp with the back-biasing circuit and source degeneration resistors. Such modification provides reduced output offset voltage for wide range of frequencies, i.e. from 10 MHz to 1 GHz, as explained above in respect of the figure 7.

The proposed CMOS Miller OpAmp is compared with the conventional Miller OpAmp for various parameters as shown in a table given in figure 2. The table shows that the proposed CMOS Miller OpAmp delivers the output with more stability and reduced output offset voltage over wide range of frequency. A graph is also plotted through a simulation using a Spectre simulator as shown in figure 3, the graph also witnesses better performance given by the proposed Miller OpAmp in terms of output offset voltage and stability over wide range of frequency, i.e. from 10 MHz to 1 GHz.

Figure 10 also illustrates a graph that compares the performance of all the aforesaid OpAmps over the given range of frequency band. The figure shows that the proposed Miller OpAmp has minimized output offset voltage to around 5 mV over the frequency range of 10 MHz to 1 GHz.
,CLAIMS:
1. A high EMI immunity CMOS miller operational amplifier (100), comprising:
two CMOS differential circuits (110, 120) comprising a first CMOS differential circuit (110) and a second CMOS differential circuit (120) with an inverting input and a non-inverting input, wherein an output node of the first differential CMOS circuit(110) is connected to the outer differential circuit (120);
at least one low pass filter (130) connected between the first CMOS differential circuit (110) and the second CMOS differential circuit (120);
a back-biasing circuit (140) connected to the inverting input and the non-inverting input of the second CMOS differential circuit (120);
a current source connected with a plurality of transistors, wherein the plurality of transistors are connected to the first CMOS differential circuit (110), the second CMOS differential circuit (120) the back-biasing circuit (140); and
a series RC circuit connected at an output node of the outer differential circuit (120).
2. A high EMI immunity CMOS miller operational amplifier as claimed in claim 1 further comprising source degeneration resistors Rs connected to the second CMOS differential circuit (120).
3. A high EMI immunity CMOS miller operational amplifier as claimed in claim 1 further comprising a load capacitor CL connected at an output (Vout) of the operational amplifier (100).
4. A high EMI immunity CMOS miller operational amplifier as claimed in claim 1, wherein the inner differential circuit (110) comprises a differential pair of NMOS transistors M1a and M2a and a differential pair of PMOS transistors M3a and M4a.
5. A high EMI immunity CMOS miller operational amplifier as claimed in claim 4, wherein one of transistor of the inner differential circuit (110) is realized by a diode connected transistor.
6. A high EMI immunity CMOS miller operational amplifier as claimed in claim 4, wherein transistors M1a and M3a are connected in a cascade configuration and transistors M2a and M4a are connected in a cascade configuration.
7. A high EMI immunity CMOS miller operational amplifier as claimed in claim 1, wherein the outer differential circuit (120) comprises a differential pair of NMOS transistors M1 and M2 and a differential pair PMOS transistors M3 and M4.
8. A high EMI immunity CMOS miller operational amplifier as claimed in claim 7, wherein one of transistor of outer differential circuit (120) is realized by a diode connected transistor.
9. A high EMI immunity CMOS miller operational amplifier as claimed in claim 7, wherein transistors M1 and M3 are connected in a cascade configuration and transistors M2 and M4 are connected in a cascade configuration.
10. A high EMI immunity CMOS miller operational amplifier as claimed in claim 1, wherein the plurality of transistors connected with a current source comprise the NMOS transistors MBIAS, M5a, M5, M5b, M6 and M7.
11. A high EMI immunity CMOS miller operational amplifier as claimed in claim 10, wherein the NMOS transistors M5a, M5 and M5b are connected to the inner differential circuit (110), outer differential circuit (120) and back-biasing circuit (110) respectively.
12. A method for providing a high EMI immunity operational amplifier, the method comprising:
generating a differential output signal by using an operational amplifier circuit, wherein the operational amplifier circuit comprises a first sub-circuit and a second sub-circuit;
coupling a first input signal to a first input of the first sub-circuit through at least one passive filter such that unwanted signals from the first input signal are rejected;
generating a first output signal by using the first sub-circuit and the second sub-circuit, wherein an output from the first sub-circuit is applied to the second sub-circuit, wherein the first sub-circuit comprises a first differential pair of transistors along with along with a first and a second transistors, wherein a first and a second transistors are connected to each transistor of the first differential pair of transistors in cascade configuration respectively, wherein the first transistor is configured as diode connected, similarly, the second sub-circuit comprises a second differential pair of transistors along with a third and a fourth transistors, wherein a third and a fourth transistors are connected to each transistor of the second differential pair of transistors in cascade configuration respectively;
providing low capacitance at an output node of the first sub-circuit by configuring the second transistor as diode connected, wherein the output from the output node of the first sub-circuit is coupled to the fourth transistor;
coupling a second input signal to a second input of the second sub-circuit such that unwanted signals from the second input signal finds a low impedance path through the third transistor, wherein the fourth transistor is configured as diode connected, wherein the second input signal is inverted with respect to the first input signal;
rejecting further the unwanted signals at higher frequencies by back-biasing the second sub-circuit by using a back-biasing circuit, wherein the back-biasing circuit comprises a pair of transistors such that sources of both the transistors are connected to the gate of the transistors of the second differential pair; and
combining the first output signal from the fourth transistor with a second output signal resulted from the second input signal at an output node for generating the differential output signal.
13. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein matching characteristics of the transistors in pair of the first differential pair as well as of second differential pair.
14. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein configuring NMOS transistors as the first and the second differential pairs.
15. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein configuring PMOS transistors as the first, the second, the third and the fourth transistors.
16. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein further comprises providing more than one passive filter at the first or the second input of the operational amplifier circuit.
17. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein selecting the passive filter from at least one of RC filter, LC filter or Pi filter of signal or multiple stage.
18. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein the unwanted signals are common mode or differential mode EMI disturbances.
19. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein there may be more than one pair of transistors in the back-biasing circuit.
20. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein the transistors of the pair of transistors in the back-biasing circuit are NMOS transistors.
21. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein the operational amplifier circuit generates the differential output signal with a very low output offset voltage (less than 5 mV) from 10MHz to 1 GHz.
22. The method for providing the high EMI immunity operational amplifier as in claim 12, wherein the output node further includes resistor RZ and capacitor CC in series for improving the stability at wide range of frequency.