FORM - 2 THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION (See section 10 and rule 13) Title: A SELF-BIASED MIXER IN 0.18 µm CMOS FOR AN ULTRA-WIDEBAND RECEIVER Applicant: Applicant : IITB MONASH RESEARCH ACADEMY Nationality: INDIAN Address : IIT Bombay Powai, Mumbai 400 076, India THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER, IN WHICH IT IS TO BE PERFORMED FIELD OF INVENTION The present invention relates to a self-biased CMOS mixer with an integrated quadrature multiplication circuit. In particular, the present invention relates to a self-biased fully differential CMOS mixer, in which the biasing is switched to lower the flicker noise figure (NF). More particularly, the present invention relates to a self-biased fully differential CMOS mixer configured for ultra-wideband applications. BACKGROUND OF INVENTION Since the introduction of the superheterodyne receiver, patented in 1917 by Edwin Armstrong, electronic mixers are used in a multitude of electronic applications requiring one or more frequency translations. Since these mixers are also identified as multipliers due to their operation, they multiply two signals with different frequencies in the time domain, thereby resulting in output signals lying at the fundamental as well as at the sum and difference frequencies. Because of this multiplication, any circuit exhibiting a second order non-linearity and through which two or more arbitrary signal frequencies are routed, generates sum and difference frequencies, which are often undesirable (since this causes signals to spread in adjacent channels). This property is identified as cross-modulation. Consequently, mixers based on a non-linear operation are usually avoided, as they tend to generate spurious components difficult to be filtered. However, as active devices are inherently non-linear, it is important to realize that every signal coupling parasitically in a transistor circuit, may cause cross-modulation because of the transistor's intrinsic non-linearity. For this reason, any feedthrough from the RF signal or from the local oscillator to the mixer or other sub-circuits is highly undesirable and thus should be avoided. Nowadays, mixers are usually designed as active multipliers. In particular, mixers in superheterodyne radio receivers multiply the local oscillator (LO) signal with the radio frequency (RF) signal which has been received by the antenna, generating a sum or difference component lying at the chosen intermediate frequency (IF) and thereby allowing the demodulation to occur at the latter frequency. In direct conversion receivers (also called zero-IF receivers), the precision of the LO signal is even more crucial, since any deviation of the LO frequency from the RF carrier frequency results in large demodulation errors as well as a considerable DC and low frequency offset, which may cause disturbances or even worse, pull the receiver front end out of its operating region. To summarize, the receiver precision is highly dependent on the accuracy of the generated oscillator signal (phase noise) as well as on the various mixer design parameters (such as linearity, noise figure NF, matching and isolation). Wireless device architecture is divided into various modules. Out of all modules, one of the key components among them is radio frequency (RF) as well as the transmitter (Tx) and Receiver (Rx) front end. The higher frequencies are used in wireless communication for reducing antenna size. Since very high frequency is used for communication to achieve low-power, high computing and processing speed, it is required to down convert higher frequencies to lower frequencies for the receiver and vice-versa for transmission. In the receiver design, RF mixer is used to down convert high frequencies to the base band frequencies. A down conversion mixer is basically a three-terminal device which converts high RF to low IF (Intermediate frequency) by providing LO (Local Oscillator) input. GaAs HEMT and BJT provide significant improvement in RF front end circuits. But due to the requirement of high level integration and combining RF front end with back end, these technologies impose more complexity and cost. The modern radio frequency CMOS (Complementary Metal Oxide and Semiconductor) technology provides better solution in terms of integration and cost. However, CMOS technology requires designing circuits operating at lower supply voltages with good performance in terms of linearity, isolation and noise. The important features of the mixer are the conversion efficiency, isolation between the inputs and the output, power consumption, linearity, and noise. PRIOR ART & DISADVANTAGES OF THE RESPECTIVE PRIOR ART Earlier References [1], [2] reported works report UWB mixers with on-chip LC resonant circuitry. However, these circuits occupy a large chip area. The mixer presented in the Reference [3] uses a bulk local oscillator (LO) injection method, which increases the noise of the mixer. Similarly, the Reference [4] has proposed an improved bulk LO injection mixer with lower NF. However, it still shows a low IIP3. Another important parameter in mixers is the isolation between mixer ports. It is discussed in the Reference [5] that due to stringent requirements of orthogonal frequency-division multiplexing (OFDM) and UWB applications, the isolation between mixer ports should be as high as possible. As proposed in the in the Reference [6), the isolation depends on the circuit symmetry. Generally, this symmetry is measured by parameters such as common-mode rejection ratio (CMRR). Different kinds of multipliers/mixers have been proposed in the prior art literature. Of these, the Gilbert cell mixer has been used in a wide range of applications. However, all of these reported mixers require additional biasing circuitry. To get rid of additional biasing circuit, there are different self-biased differential amplifiers reported in the literature. Nevertheless, it is a single ended differential circuit and does not provide a quadrature multiplication. Therefore, there is an existing need for developing a self-biased fully differential multiplier with an integrated quadrature multiplication, which would achieve improved performance as compared to the conventional mixer circuits discussed above. Accordingly, the recent developments in mixer design are used to focus on ultra-wideband (UWB) applications with lesser power consumption, increased linearity, and lower noise figure (NF). OBJECTS OF THE INVENTION Some of the objects of the present invention - satisfied by at least one embodiment of the present invention - are as follows: An object of the present invention is to provide self-biased fully differential CMOS mixer. Another object of the present invention is to provide self-biased fully differential mixer having an improved receiver performance over ultra-wideband with lesser power consumption. Still another object of the present invention is to provide self-biased fully differential mixer having an improved receiver performance over ultra-wideband with increased linearity. Yet another object of the present invention is to provide self-biased fully differential mixer having an improved receiver performance over ultra-wideband with a lower noise figure (NF). A further object of the present invention is to provide self-biased fully differential mixer having a CMOS circuit, which is linear, high-gain, has lesser noise figure (NF) and shows high isolation between the input and output ports. These and other objects and advantages of the present invention will become more apparent from the following description when read with the accompanying figures of drawing, which are, however, not intended to limit the scope of the present invention in any way. SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a self-biased CMOS mixer with an integrated quadrature multiplier circuit comprising: a stacked configuration of a plurality of transistors (M1 - M12) connected by means of a plurality of transmission lines configured to mix a radio frequency (RF) signal with a local oscillator signal and to output a mixed intermediate frequency signal and to facilitate a multiplication operation between VLo and VRF inputs; wherein the biasing of the mixer is generated by connecting the circuit output nodes to the gate of the tail transistors and or stabilizing the bias voltage of the overall CMOS mixer. Typically, the stacked configuration of a plurality of transistors includes a pair of four inverters M1-M4 and M5-M8 each and the currents thereof are varied by four transistors M9-M12 for achieving multiplication between the VLOand VRF inputs. Typically, the transistors M1 and M4 are switched ON and M2 and M3 are switched OFF while working under the positive half cycle of the input signal to generate the equivalent small signal current iy(oc VRF) by transistors M11 and M9 to be passed through the differential load RL. Typically, the transistors M2 and M3 are turned ON during the negative half cycle to generate the small signal current by transistors M9 and M11 to be passed through the differential load RL. Typically, the self-biased CMOS mixer is self-biased in a fully complementary configuration. Typically, the self-biased CMOS mixer is configured with a symmetrical self-biased circuit for consuming a very low power of the order of 3.45 mW with 1.8V supply and operates between 1 to 6 GHz. Typically, the plurality of transistors comprises NMOS and PMOS transistors to facilitate the multiplication operation. Typically, the integrated quadrature multiplier circuit comprises integration of the mixer stages and transmission lines on a common semiconductor substrate. Typically, the conversion gain of the said mixer is between 12-15.5 dB with the RF input between 2-4 GHz. Typically, the linearity of the said mixer measured in terms of the maximum third-order input intercept point (IIP3) is - 4.5 dBm at 6 GHz, 170 MHz IF output, and LO input power at 7 dBm. Typically, the flicker noise figure (NF) of the said mixer is lowered by minimum 12 dB. Typically, the flicker noise figure (NF) of the said mixer is obtained minimum 12 dB and isolation is by more than 45 dB of isolation across a frequency band between 1 to 6 GHz. Typically, the maximum isolations across a frequency band between 1 to 6 GHz and observed between ports for RF-to-IF, LO-to-RF and LO-to-IF is 45 dB, 50 dB and 52 dB respectively. DETAILS OF THE INVENTION A CMOS mixer is an essential component in various applications, which requires mixing, phase-difference detection, modulation-demodulation, and frequency translation. Recent developments in mixer design focus on ultra-wideband (UWB) applications with lesser power consumption, increased linearity, and lower noise figure (NF). An elaborate configuration of the self-biased CMOS mixer in UMC 0.18µm technology is disclosed in this patent specification. The mixer configured in accordance with the present invention comprises a complementary, symmetrical self-biased circuit. It consumes 3.45 mW of power and operates between 1 GHz to 6 GHz. From the measurement results, it demonstrates obtaining a maximum conversion gain of 13 dB, a maximum IIP3 of -4.5 dBm, a minimum noise figure of 12 dB, and more than 45 dB of isolation across a frequency band spanning between 1 GHz to 6 GHz for making this self-biased CMOS mixer highly suitable for UWB RF applications. The following are the various RF front end applications of this self-biased CMOS mixer: 1) Mixer, 2) Multiplier in phase-difference detection in PLL (Phase Locked Loop), 3) Modulator-Demodulator, and 4) Frequency converter. DESCRIPTION OF THE INVENTION SELF-BIASED MIXER CORE The self-biased CMOS mixer configured in accordance with the present invention and shown in Figure 1 incorporates an integrated quadrature multiplication circuit with self-biasing in a fully complementary configuration. It has a stacked configuration with NMOS and PMOS transistors to provide the multiplication operation. The mixer consists of a pair of four inverter M1-M4 and M5-M8 each, the currents of which are varied by four transistors M9-M12 to achieve multiplication between the VLoand VRF inputs. As shown in Figure 1, the biasing of the mixer is generated by connecting the circuit output nodes to the gate of the tail transistors. This stabilizes the bias voltage of the entire mixer. The working principle of the proposed mixer is explained in Figure 2. When the differential input voltage (VL0+-VL0~) is large, the transistor pairs M1-M3 and M2-M4 operate as switches. During the first half cycle of the input signal, the transistors M1 and M4 are turned on and M2 and M3 are turned off. So, the equivalent small signal current /y(α vRF) generated by transistors M11 and M9 is passed through the differential load RL. Similarly, during the negative half cycle, transistors M2 and M3 are turned on and the small signal current generated by transistors M9 and M11 is passed through the load. In the Reference [8], the output of this mixer is expressed as: where, This equation is valid for a small signal that is applied to the mixer. SELF-BIASED MIXER PARAMETERS There are basically two kinds of mixer topologies that are widely studied and discussed in literature: transconductance switch (GmSw) discussed in Reference [91 and the switched transconductance (SwGm) discussed in Reference[10]. The derivation of the various mixer performance parameters such as conversion gain, feedthrough, noise figure, and linearity are explained in the following subsections. A} Conversion Gain (CG): The self-biased mixer configured in accordance with the present invention is complementary in nature, meaning that the conversion gain is double that of a conventional Gilbert cell mixer. The CG of a Gilbert cell mixer is given by: The overall Gm of the self-biased mixer configured in accordance with the present invention is given by: The load of the circuit is given by: So, the overall CG of the self-biased mixer of Figure 1 and configured in accordance with the present invention is given by: where, gm9and gm11 are the input transconductances of the RF input transistors M9 and M11 respectively. are the output conductance of the LO input transistors M1, Similarly, M3, M5, M7, respectively. The conventional single-balanced mixer with the capacitance CP appearing at high frequencies at node P is shown in Figure 3a. This capacitance limits the mixer operation at higher frequencies and reduces the CG of the mixer. The CG of this mixer considering the CP effect is given by: Table-I below provides the values of these parameters. gm{= gm9 +gm11) 18.4 mS Rs 500Ω fo 1.6 kΩ Cs 1.8 pF Co Gml.o(= gm +gms) 100 fF 15.65 mS Wp/Wn 3 y 2/3 Cr[= Cp9+Cp11) 200 fF Further, the single-balanced equivalent circuit of the self-biased mixer configured in accordance with the present invention is shown in Figure 3b. Accordingly, the modified conversion gain of the self-biased mixer configured in accordance with the present invention is given from equation (4) as: Therefore, CG in equation (5) is written as: The capacitive degeneration introduced by Zs increases the effective gm of the proposed mixer at higher frequencies [11l The poles and zeros of the proposed configuration are based on the values of Zload, Zs, CPand gmof the transistors. The CG of equation (6) is plotted in Figure 4 by using the parameters that are tabulated in Table I. It shows that the calculated results closely follow the simulation results. The tabulated parameters are calculated during the initial bias conditions. The difference in the plots is due to the parasitic capacitances which are not captured in the calculated parameters. B| Feedthrough: Although, in a conventional Gilbert cell mixer, the NMOS or PMOS transistors function as the LO switch; the self-biased mixer (Figure 1) configured in accordance with the present invention is symmetrical and the CMOS inverter functions as the LO switch. Thus, the alternating currents generated by the incoming RF signals in the transistors M9 and M11 are switched by the CMOS inverter, which improves the switching in the self-biased mixer of Figure 1. Consequently, the common mode components that appear at the output are reduced due to better switching in the mixer. Therefore, the self-biased mixer configured in accordance with the present invention achieves an improved isolation in comparison to the conventional Gilbert ceil. The isolation parameter of this self-biased mixer is analyzed by evaluating the CMRR. The CMRR of the differential amplifier indicates the amount of common mode signal appearing at the differential output. Accordingly, the mixer common mode rejection ratio (MCMRR) for the self-biased mixer configured in accordance with the present invention is calculated by the equation: Further, the RF common mode to IF differential mode rejection is defined as MCM.DM as given below: MCMRR for Gilbert cell mixer is calculated as given below: The differential gain, by considering all transconductances of the input transistors to be non-identical is given by: For comparing the MCMRR values, the Gilbert cell mixer is configured by making its power consumption the same as for the self-biased mixer configured in accordance with the present invention. The MCMRR of the aforesaid self-biased mixer and the Gilbert cell mixer is simulated by using Monte Carlo methods in Cadence. The simulations of the common mode (CM) gain are carried out by applying common mode RF (CMRF) and common mode LO (CMLO) signals. From the Monte Carlo CMRR simulation data with 1000 samples and RF input at 4 GHz (Figure 6a-b), it is evident that the MCMRR of the self-biased mixer is higher than that of the Gilbert cell mixer. The values of the transconductances Of the input transistors are taken from the Monte Carlo simulation results for calculating the MCMRR. C} Noise Figure (NF): The noise figure of the self-biased mixer configured in accordance with the present invention is based on three sources of noise, i.e. the noise sources from the transconductance stage (M9-M12), from the switching stage and from the load stage (M1-M8). The calculation of the thermal noise figure has been done using the method explained in [12]. Two RF noise current sources In.M2 9 and 1n M2 11 are generated by transistors M9 and M11, respectively. The noise source from the switching stage is given by Vn'sw2 So, the noise output at node Z+ is derived as: Let AT represent the fractional period during which the switching transistors (M1-M8) behave as a differential circuit. The output differential noise generated by the switching CMOS pair is given by: The noise due to the switching LO differential pair is weighted by a factor of 2 , and the noise generated by RF transconductance stage and switching stage are weighted by a factor of (1-2α)[121. The total input referred noise is therefore given by: Dj. Linearity: The linearity of the mixer is based on the overdrive voltage of the RF input transistors. While stacking multiple transistors, it is difficult to achieve a higher overdrive voltage with a limited supply voltage. This would limit the capability of this circuit to provide high linearity at a lower supply voltage. MEASUREMENT OF THE SELF-BIASED MIXER CORE A self-biased mixer fabricated in the 180nm RFCMOS process provided by UMC, Taiwan is shown in Figure 1. A micrograph of the fabricated chip is shown in Figure 11. The area, including the pads of the chip, is 819um × 665um. The circuit is self-biased such that all transistors except M13-M16 remain in saturation. A PCB has been specifically fabricated for the self-biased configured made according to the present invention mixer, to be tested up to 6 GHz. The fabricated PCB with the packaged die connected is shown in Figure 12. The PCB tracks have been configured as coplanar waveguides (CPW). An external termination resistance of 50Ω was connected to provide input matching at the LO and the RF ports over a wide frequency band. The CPW line width is calculated using the technique mentioned in [14]] The CPW line parameters are shown in Table-ll below: CPW PARAMETERS The block diagram of the self-biased mixer test setup is shown in Figure 13. The differential signals were produced by using wide bandwidth baluns connected to the RF and LO inputs and at the IF output. The RF transistor inputs were biased using a bias tee connected between the signal input and the inputs of SMA connectors of PCB, The testing of the self-biased mixer is carried out at room temperature. Moreover, the typical corner of the device has been considered while characterizing the self-biased mixer. The current drawn by the self-biased mixer, including the buffer during test was 7 mA from the 1.8 V supply, when the input RF transistors are biased at 0.9 V. The power consumption of the self-biased mixer core excluding the buffer is 3.45 mW when a 1.8V supply is provided. The test parameters are tabulated in Table-Ill below: TESTPARAMETEKS Parameters Value RF input freq 1-10 GHz IF output freq 40-500 MHz Power Supply 1.8 V LO input power 7 dBm RF input power > -35 dBm The input reflection coefficients (S11) at the RF, LO and IF ports are shown in Fig.14. The S11 values measured at the RF and LO input ports are less than -10 dB for the band that spanned from 1 GHz to 10 GHz. The S11 values measured at the IF output port is less than -10 dB for an IF frequency range from 10 MHz to 500 MHz. The measured and simulated CG at 3 GHz RF input with variation in IF frequencies between 40 MHz to 500 MHz are shown in Figure 15. It can be observed that the measured CG of the proposed mixer is around 13 dB till 170 MHz. The CG of the proposed mixer drops at higher IF frequencies. The 3 dB IF bandwidth for the proposed mixer is measured to be around 500 MHz. Further, the simulated and measured CG plotted at various RF input frequencies and at IF of 170 MHz are shown in Figure 15. The measured gain of the proposed mixer is between 10 to 13 dB for an RF band between 1 GHz to 6 GHz. The CG variation with change in the LO input power at 3 GHz RF input and 170 MHz IF output is shown in Figure 17. The measured NF plotted at various IF values is shown in Figure 18. The NF of the proposed mixer is between 12-15,5 dB when the RF input is between 2-4GHz. The linearity of the proposed mixer was measured using a two-tone analysis. The measured third-order input intercept point (IIP3) is shown in Figure 19. The maximum IIP3 observed for the proposed mixer is -4.5 dBm at 6 GHz RF input, 170 MHz IF output, and LO input power at 7 dBm. The measured LO-RF, LO-IF, and RF-IF isolations are shown in Fig. 20. The maximum isolations observed between ports: RF-to-IF is 45 dB, LO-to-RF is 50 dB, LO-to-IF is 52 dB. Finally, the measured MCMRR for various RF input frequencies with the IF at 170 MHz and LO input power at 7 dBm are shown in Figure 21. The CMRF and CMLO for the MCMRR measurement was provided by using a power divider. The measured results of the proposed mixer are summarized and compared with other state-of-the-art mixers in Table IV below: PERFORMANCE SUMMARV Reference TeclmologyFrequcncylF Vdd 1 NF(dB) CG(dB) IIP3 Isolations (