A Self Test Structure For Interconnect And Logic Element Testing In
Programmable Devices
Field of the Invention
The invention relates to a self-test structure for interconnect and logic element testing in programmable devices.
Background of the Invention
Testing of programmable logic like Field Programmable Gate Array (FPGA) is a very complex task because all logic elements (configuration latches and programmable resources combined) can attain mind-boggling logic combinations requiring huge amount of test-vectors to test them. So Design For Testabihty (DFT) designers usually adopt a combination of ad hoc and traditional approaches for achieving maximum testability. Any DFT technique, which helps to determine device status at silicon without much of tester's time, is highly desirable.
Generally a Linear Feedback Shift Register (LFSR) is used for generating particular signature, which verifies device's functionality to some extent. A LFSR is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values.
Figure 1 shows the main diagram of the US Patent No. 5,550,843 by Wilson K. Yee entitled 'Programmable Scan Chain Testing Structure And Method'. The above-mentioned circuit comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contain an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.
The aforesaid prior art solves a major testing issue of FPGAs and other programmable devices, but the cost paid in terms of silicon hardware is too expensive. For each logic cell cluster, the invention proposes to have dedicated scan multiplexers and routing resources. Seeing the complexity and size of today's FPGAs, the number of such multiplexers will grow drastically which would further occupy valuable silicon space. Further more, the testing hardware, causing increased size, is never used by actual user application. As small size and low power are the key Universal Selling Point for today's electronic products in general and FPGAs in particular, the prior art looses its significance.
The testability offered by the aforesaid US patent covers only the logic portion and not the routing, which takes around 80% of total silicon size, hence more susceptible to Mure.
Another drawback is that it is highly dependent on the correctness of EDA software tool set. As the programmable scan chain is activated through proper configuration of latches done using FPGA software and hardware, any small problem in setup may lead to wrong results.
Thus the major problem faced while testing an FPGA chip is its heavy dependency on system EDA software. Neither results/outputs can be expected nor inputs can be applied to the FPGA unless the Input / Output Block IOs and Logic blocks are programmed. This invention proposes to remove this dependency of testing from software and yet give initial health check of device on reset state of configuration latches. The implemented logic will help generate pseudo-random sequences without any need for user to program configuration latches.
The Objects and Summary of the Invention
To obviate the aforesaid drawbacks the object of the instant invention is to provide scan chains for testability by using existing device architectural resources.
Another object of the invention is to use said testability by using reset state configuration bits.
Yet another object of the invention is provide software independent solution that verifies logic block as well as the routing paths.
To achieve the above objects the instant invention provides a self test structure for interconnect and logic element testing in programmable devices comprising:
- plurality of said logic elements;
- an interconnect structure for connecting said logic elements;
- SRAM based configuration latches for configuring said interconnect structure; characterized in that it includes
- test configuration means for configuring any desired set of logic elements,
interconnect structure and configuration latches during reset state that links
said logic elements and interconnect structure to form a complete path
between the interface points of said programmable logic device to enable
testing of said desired elements in said complete path.
The configuration latches associated with logic elements and interconnect structure other than said desired logic elements and interconnect structure are not configured.
The programmable logic device is configured to logic zero at the time of reset.
The programmable logic device includes a FPGA.
The said FPGA includes LUTs.
The said LUT in a logic element implements XOR functionality.
The present invention also provides a method for testing a self test structure comprising the steps of:
- resetting the logic elements and configuration latches;
- configuring a logic zero value in said logic elements and configuration latches; and
characterized in that
- programming the desired set of logic elements, interconnect structure and configuration latches in the reset state; and
- concatenating said desired set of logic elements to form a complete path, thereby enabling testing of said desired elements in said complete path.
Brief Description of the Accompanying Drawings
The invention will now be described with reference to the accompanying drawings
Figure 1 shows the invention in accordance with the USPN 5,550,843.
Figure 2 shows a logic element of FPGA.
Figure 3 shows the structure of a LUT.
Figure 4 shows the connectivity between the logic elements.
Figure 5 shows the arrangement of latches in FPGA.
Figure 6 shows the connections between logic elements in the reset state.
Figure 7 shows a normal LUT implementation using SRAM Latches and multiplexers.
Figure 8 shows another embodiment in accordance with the invention.
Detailed Description of the Invention
Figure 2 shows a generic diagram of FPGA having a LUT 20, a flip-flop 23 and multiplexers 21, 23 that can support a register-packing mode. This is collectively referred to as a logic element of the FPGA. The LUTs in a logic element are SRAM based. The architecture of a LUT 20 is as shown in figure 3. It consists of 16 6T-SRAM cells 3[1:16].
A FPGA structure contains numerous logic elements, which are interconnected to each other. Figure 4 broadly shows such an arrangement. The logic elements 40 and 41 are connected to each other through Programmable Switch Matrix (PSM) 42 controlled by 6T-SRAM cells / configuration latches. The PSM 42 connects the output of one logic element to another once it is configured.
The invention proposes to implement some logical circuits at the time of INITIAL RESET by intelligent implementation of configuration latches. Before configuring the same, all the configuration latches are RESET to an initial value ZERO.
Figure 5 shows the structure used for storing a value in configuration latches. It consists of a Vertical Shift Register (VSR) 50, a Horizontal Shift Register (HSR) 51 and plurality of latches. To store the zeros in the configuration latches, a sequence of zeros is stored in VSR 50. Then the plurality of latches is enabled column by column using HSR 51. Once zeros are stored in the configuration latches at the reset, the desired functionality bits are stored in the configuration latches.
Once the configuration latches are reset, they can implement o A LSFR chains inside the device. o A shift register using LUTs as feed-through or o A shift register using direct connection to Flip-flops.
Figure 6 shows the connections between logic elements once they are configured in the reset state. The reset state positioning of configuration latches ensures that above
mentioned connections are made at the time of initial reset. Furthermore, the reset state configuration (all zeros) inside an LUT implements an XOR gate instead of logic 0. This is done by making some minor modification in LUT structure as shown in Figure 7.
Figure 7 shows a normal LUT implementation using SRAM Latches and multiplexers. The new connectivity of latches to output multiplexers are incorporated by making some software changes. However the changes made are trivial.
Reset state also ensures that these chains have their input and output available as primary input/output at tester. The LSFR chains are made by concatenating identical logic units (an LUT and a FF). The LUT in a logic element implements XOR functionality and forwards the output to the flip-flop present in the same logic element. The routing resources are also programmed as the connections between the logic elements are made in the reset state. Thus the desired complete path between the logic elements is formed vide the routing resources keeping the un-required connections open.
Figure 8 shows another embodiment detailing a feed through path. By slightly changing the connectivity of the configuration latches and output multiplexer of figure 7, a feed through can be implemented in LUTs. The flip-flops can be connected again to form a shift register as shown in figure 8.
Thus the problem of increased silicon size is tackled by using existing device architecture resources for making scan chain. As explained in figures 6 and 7, the proposed invention utilizes the existing flip-flops and LUT for implementing a similar scan chain for testability purpose using Reset State configuration bits. Hence it is quite economical in terms of silicon area.
The proposed invention not only tests Logic portion, but also checks user routing paths. As the scan chains use same user routing as users application, so while testing Logic, the user routing is automatically tested. This also further reduces any extra overhead due to scan chain routing while at same time increasing tests coverage of the architecture.
As the proposed invention never involves any software support, the device initial tests can be made independent of FPGA software and hardware for configuration. The invention uses an inteUigent use of reset state of configuration latches to make necessary connections.

claim:
A self test structure for interconnect and logic element testing in programmable devices comprising:
- plurality of said logic elements;
- an interconnect structure for connecting said logic elements;
- SRAM based configuration latches for configuring said interconnect structure;
characterized in that it includes
- test configuration means for configuring any desired set of logic elements,
interconnect structure and configuration latches during reset state that
links said logic elements and interconnect structure to form a complete
path between the interface points of said programmable logic device to
enable testing of said desired elements in said complete path.
The self-test structure as claimed in claim 1 wherein the configuration latches associated with logic elements and interconnect structure other than said desired logic elements and interconnect structure are not configured.
The self-test structure as claimed in claim 1 wherein said programmable logic device is configured to logic zero at the time of reset.
The self-test structure as claimed in claim 1 wherein said programmable logic device includes a FPGA.
The self-test structure as claimed in claim 4 wherein said FPGA includes LUTs.
The self-test structure as claimed in claim 5 wherein said LUT in a logic element implements XOR functionality.
7. A method for testing a self test structure comprising the steps of:
- resetting the logic elements and configuration latches;
- configuring a logic zero value in said logic elements and configuration latches; and
characterized in that
- programming the desired set of logic elements, interconnect structure and configuration latches in the reset state; and
- concatenating said desired set of logic elements to form a complete path, thereby enabling testing of said desired elements in said complete path.

8. A self test structure for interconnect and logic element testing in programmable devices substantially as herein described with reference to and as illustrated in the accompanying drawings.
9. A method for testing a self test structure substantially as herein described with reference to and as illustrated in the accompanying drawings.