A SENSE AMPLIFIER PROVIDING LOW CAPACITANCE WITH REDUCED RESOLUTION TIME
Field of the Invention
The present invention relates to memory devices and more specifically to a sense amplifier providing a high speed sensing with high speed read operations in static random access memory (SARM) circuits.
Background of the Invention
In an integrated memory circuit, a sense amplifier is used to improve the speed of a memory and to provide signals, which confirms to the requirements of driving peripheral circuits within the memory. Due to large arrays of SRAM cells, a resulting signal of a read operation has a much lower voltage swing (of the order of few tens milli volts). The sense amplifier is used to sense this small swing and provide the corresponding full rail-to-rail voltages. The sense amplifier senses the difference between a true bit line and a complimentary bit line during a read operation and amplifies the difference, so that the resulting signal will have a swing width from a ground voltage to a supply voltage.
FIGURE 1 illustrates a general configuration for an SRAM column. The SRAM column includes 'N' number of rows in one column. During a read cycle, one of the N word lines goes high and a corresponding memory cell discharges a bit line (if '0' is stored in the memory cell) or a complementary bit line (if T is stored in the memory cell). When a sufficient voltage difference is created between the true bit line and the complementary bit line, the sense amplifier is enabled and the voltage difference is amplified and an output data is generated corresponding to a data stored in the memory cell.
FIGURE 2 illustrates a circuit diagram 200 for a conventional cross-coupled latch type sense amplifier. It consists of two PMOS transistors MP1 and MP2 and two NMOS transistors MN1 and MN2 connected between a true bit line and a complementary bit line BITIO and BITBIO.

The transistors MP1 and MNl and the transistors MP2 and MNl are individually connected to form two inverters. The two inverters are cross coupled to form a latch circuit. The sense amplifier also consists of two PMOS transistors MP3 and MP4, with their one end connected to the bit line, the other end to the latch output node and a gate terminal receives a control signal SAEN1. The transistors MP3 and MP4 transfer a resulting signal of a read operation to the cross coupled latch in response to the control signal SAEN1. The NMOS transistor MN3 is configured to provide a ground voltage to the cross coupled latch in response to the control signal SAEN1, with one end connected to the latch and the other end to the ground. The gate terminal of the MN3 receives a control signal SAEN1.
The true and complimentary bit lines BITIO and BITBIO are supplied with a true and a complementary data signals from the memory cells. The control signal SAEN1 is kept at a logic low causing the transistors MP3 and MP4 to conduct and thereby passing on the swing generated by the memory cell to the latch. The SAEN1 is then made to logic high, causing a supply voltage VDD and the ground GND to be connected to the latch. One of the bit lines having a higher value would cause one of the NMOS transistors MNl or MN2 to conduct more than the other. The transistor that conducts less (MNl or MNl) will have a lesser voltage at the drain terminal in comparison to the other NMOS transistor in the latch circuit. As a result, the transistor MP1 or MP1 will conduct. Thus decreasing the rate of fall of the slower transistor further eventually brings it to a cut off state. The PMOS itself will get into a saturation region. Then the junctions of INP and INN will be placed at two extremes of the VDD, i.e., one is pulled up to the supply voltage VDD and the other is pulled down to the ground voltage GND, depending on the value of the data signals received from the memory cells. This value is fed to an inverter, which further amplifies the signal and provides the output. Thus the cross coupled latch sense amplifier amplifies the true and the complementary data signals by a difference (VDD-GND), where VDD is a supply voltage and GND is a ground voltage.
However, the cross coupled latch sense amplifier imposes a very high capacitance on the bit lines and thereby slows down the discharge rate. Therefore, the read operation will be slower. To overcome this problem, alpha-latch type sense-amplifier was proposed.

FIGURE 3 illustrates a circuit diagram 300 of a conventional alpha type latch sense amplifier. The amplifier consists of two PMOS transistors MPland MP2 and two NMOS transistors MN1 and MN2 connected between true and complementary bit lines BITIO and BITBIO. The transistors MP1 and MN1 and the transistors MP2 and MN2 are individually connected to form two inverters. The two invertors are cross coupled so as to form a latch. Two NMOS transistors MN3 and MN4 have their one end connected to the NMOS transistors MN1 and MN2, the other end connected to a NMOS transistor MN5 and the gate connected to the bit lines. The transistor MN5 has its one end connected to the transistors MN3 and MN4, the other end connected to a ground and the gate configured to receive a control signal SAEN1.
Working of the alpha latch type sense amplifier is similar to the cross coupled latch sense amplifier. The difference is that the true and complementary data signals from the memory cells are fed to the sense amplifier circuit through the gates of the transistors MN3 and MN4. The control signal SAEN1 is kept at a high logic for causing the transistors MN5, MN3 and MN4 to conduct and thereby passing on the swing generated by the memory cell to the latch and causing a supply voltage VDD and a ground GND voltage to be connected to the latch. The cross coupled latch starts functioning and nodes INP and INN are resolved to the supply voltage and the ground voltage, depending on the true and complimentary data signals from the memory cells.
Due to an alpha type connection in the alpha latch type sense amplifiers, the input capacitance imposed on the bit lines is less than the cross coupled latch sense amplifier. However, the resolving time is poor because of the stack of 3 transistors as compared to a stack of 2 transistors in the cross coupled latch type sense amplifier.
Thus, the prior arts discussed above do not overcome the major prevailing problems like, slower read operations, suffered from a poor resolving time, etc.
Therefore, there is a need for a novel sense amplifier to provide a high speed read operation with a faster sensing speed in the SRAM circuits. Moreover, the sense amplifier provides a low resolution time.

Summary of the Invention
It is an object of the present invention to provide a sense amplifier for high speed read operations.
It is another object of the present invention to provide a sense amplifier having a low resolution time.
To achieve the aforementioned objectives, the present invention provides a sense amplifier circuit for providing a low capacitance with a low resolution time comprising:
a -latch circuit having a first inverter circuit cross coupled to a second inverter
circuit;
a first discharge device operatively coupled to said first inverter circuit;
a second discharge device operatively coupled to said second inverter circuit;
a first PMOS transistor operatively coupled between said first discharge device
and a bit line;
a second PMOS transistor operatively coupled between said second discharge
device and a complementary bit line;
a first NMOS transistor operatively coupled between said first discharge device
and a ground voltage;
a second NMOS transistor operatively coupled between said second discharge
device and the ground voltage;
a pull down circuit operatively coupled between said latch circuit and the ground
voltage;
a delay circuit operatively coupled among the first PMOS transistor, the second
PMOS transistor and said pull down circuit for producing a delay between a first
control signal and a second control signal; and
a first NOT gate operatively coupled to a first latch output node and a second
NOT gate operatively coupled to a second latch output node to provide an output
data corresponding to a data stored in a memory cell.

Further the present invention provides a sense amplifier circuit for providing a low capacitance with a low resolution time comprising:
a latch circuit having a first inverter circuit cross coupled to a second inverter
circuit;
a first pull down circuit receiving a first control signal;
a second pull down circuit receiving a second control signal;
a first discharge device operatively coupled between the first inverter circuit and
the first pull down circuit;
a second discharge device operatively coupled to the second inverter circuit and
the first pull down circuit;
a first PMOS transistor operatively coupled between said first discharge device
and a bit line;
a second PMOS transistor operatively coupled between said second discharge
device and a complementary bit line;
a first NMOS transistor operatively coupled between said first discharge device
and the ground voltage;
a second NMOS transistor operatively coupled between said second discharge
device and the ground voltage; and
a delay circuit operatively coupled among the first PMOS transistor, the second
pull down circuit and the first pull down circuit for producing a delay between the
first control signal and the second control signal to provide a low capacitance with
a low resolution time.
The present invention provides a method for a high speed sensing and reading through a sense amplifier circuit, said method comprising the steps of:
sensing a voltage difference between a bit-line and a complementary bit line;
applying a first control signal to enable a pull down circuit for actuating the sense
amplifier circuit;
applying a second control signal to disable a first PMOS transistor and a second
PMOS transistor and enabling a first NMOS transistor and a second NMOS

transistor to discharge an input capacitance of a first discharge device and a
second discharge device; and
generating an output across latch output nodes of the sense amplifier circuit.
Brief Description of Drawings
The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGURE 1 illustrates a block diagram of a general configuration for an SRAM column. FIGURE 2 illustrates a circuit diagram of a conventional cross coupled latch sense amplifier. FIGURE 3 illustrates a circuit diagram of a conventional alpha latch sense amplifier.
FIGURE 4 illustrates a circuit diagram of a gate input latch sense-amplifier according to the present invention.
FIGURE 5 illustrates a circuit diagram of a two stage sense amplifier according to the present invention.
FIGURE 6 illustrates a flow diagram of a method for providing a high speed sensing and reading through a sense amplifier circuit according to the present invention.
Detailed description of the invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present

invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components.
The present invention provides a sense amplifier circuit 400 for providing a high speed sensing with high read operation, with a low capacitance and a low resolution time.
FIGURE 4 illustrates a circuit diagram of a gate input latch sense amplifier according to the present invention. A sense amplifier circuit 400 providing a low capacitance with a low resolution time includes a latch circuit, a first discharge device MN1, a second discharge device MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN5, a second NMOS transistor MN6, a pull down circuit MN7, a delay circuit 402, a first NOT gate 404, and a second NOT gate 406.
In the present embodiment, .the latch circuit 400 includes a first inverter circuit and a second inverter circuit cross coupled with each other. The latch circuit is connected to a voltage source VDD. The first discharge device MN1 is operatively coupled to the first inverter circuit and the second discharge device MN2 is operatively coupled to the second inverter circuit. The first discharge device MN1 includes an NMOS transistor having a source and a drain terminal operatively coupled to a corresponding source and a drain terminal of an NMOS transistor MN3 of the first inverter circuit. A gate terminal of the first discharge device MN1 is operatively coupled to a drain terminal of the first PMOS transistor MP1 and the first NMOS transistor MN5.
The second discharge device MN2 includes an NMOS transistor having a source and a drain terminal operatively coupled to a corresponding source and a drain terminal of a NMOS transistor MN4 of the second inverter circuit. A gate terminal of the second discharge device MN2 is operatively coupled to a source terminal of the second PMOS transistor MP2 and to a drain terminal of the second NMOS transistor MN6.
The first PMOS transistor MP1 is operatively coupled between the first discharge device MN1 and a bit line BITIO. The second PMOS transistor MP2 is operatively coupled between the

second discharge device MN2 and a complementary bit line BITBIO. The first NMOS transistor MN5 is operatively coupled between said first discharge device MN1 and a ground voltage. The second NMOS transistor MN6 is operatively coupled between said second discharge device MN2 and the ground voltage.
The pull down circuit MN7 is operatively coupled between the latch circuit and the ground voltage. The pull down circuit MN7 includes an NMOS transistor for receiving a first control signal SAEN1 through a gate terminal and a drain terminal is operatively coupled to said latch circuit.
The delay circuit 402 is operatively coupled among the first PMOS transistor MP1, the second PMOS transistor MN2 and the pull down circuit MN7 for producing a delay between the first control signal SAEN1 and the second control signal SAEN2. In an embodiment of the present invention, the delay circuit 402 can be designed using two invertors in series or any other circuitry which can produce a delay between the control signals. The first PMOS transistor MP1, the first NMOS transistor MN5, the second PMOS transistor MP2 and the second NMOS transistor MN6 receive the second control signal SAEN2 through a gate terminal of the transistors. The first NOT gate 404 is operatively coupled ta a first latch output node INP and the second NOT gate 406 is operatively coupled to a second latch output node INN to provide an output data corresponding to a data stored in a memory cell.
FIGURE 5 illustrates a circuit diagram of a two stage sense amplifier according to the present invention. A sense amplifier circuit 500 provides a low capacitance with a low resolution time. The circuit 500 includes a latch circuit, a first pull down circuit MN7, a second pull down circuit MN8, a first discharge device MN1, a second discharge device MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN5, a second NMOS transistor MN6, and a delay circuit.
In the present embodiment, the latch circuit includes a first inverter circuit and a second inverter circuit cross coupled with each other. The latch circuit is coupled to a voltage source VDD. The first pull down circuit MN7 is configured to receive a first control signal SAEN1. The second

pull down circuit MN8 is configured to receive a second control signal SAEN2. The first discharge device MN1 is operatively coupled between the first inverter circuit and the first pull down circuit MN7. The second discharge device MN2 is operatively coupled to the second inverter circuit and the first pull down circuit MN7. The first pull down circuit MN7 is operatively coupled between discharge devices MN1, MN2 and a ground voltage. The second pull down circuit MN8 is connected between the latch circuit and the ground voltage. The first pull down circuit MN7 is operatively coupled to a source terminal of discharge devices MN1 and MN2 through a drain terminal, and a source terminal of said first pull down circuit MN7 is operatively coupled to the ground voltage. The first pull down circuit MN7 is provided with the first control signal SAEN1 through a gate terminal. The first PMOS transistor MP1 is operatively coupled between the first discharge device MN1 and a bit line BITIO. The second PMOS transistor MP2 is operatively coupled between said second discharge device MN2 and a complementary bit line BITBIO The first NMOS transistor MN5 is operatively coupled between said first discharge device MN1 and the ground voltage. The second NMOS transistor MN6 is operatively coupled between said second discharge device MN2 and the ground voltage. The delay circuit is operatively coupled among the first PMOS transistor MP1, the second pull down circuit MN8 and said first pull down circuit MN7 for producing a delay between the first control signal SAEN1 and the second control signal SAEN2 to provide a low capacitance with a low resolution time.
The two configurations of the sense amplifier as illustrated in FIGURE 4 and FIGURE 5 are very similar in working, except that in first configuration (FIG 4), the pull down transistor (MN7) is shared in the two stages of the sense-amplifier, while in the second configuration, two different pull down transistors (MN7 & MN8) are used.
When a sufficient voltage difference appears on the bit-lines, the first control signal SAEN1 goes high and the second control signal SAEN2 remains low for a small time interval, shown as delay element in FIGURE 4 and FIGURE 5. In this time interval delay, the input of the discharging devices MN1 and MN2 is high (with a small voltage difference, greater than or equal to the offset of this sense-amplifier), so both of these will discharge the nodes INP and INN with a current difference with a very fast rate. In this time duration, the transistors MN3 and MN4 will

work as in a conventional cross-coupled latch type sense amplifier leading to a creation of further voltage difference at nodes INP and INN. Overall effect of these two transistor pairs will lead to a sufficient voltage difference at nodes INP and INN in the duration 'delay', after which the SAEN2 signal goes high and transistors MP1, MP2, MN1 and MN2 are cut-off from the circuit. As SAEN2 signal goes high, the transistors MN5 and MN6 is switched on and discharge the input capacitances of the transistors MN1 and MN2 respectively. After this, the circuit works as an ordinary cross-coupled sense amplifier. The cross-coupled latch consisting of transistors MP3, MP4, MN3 and MN4 quickly resolves the nodes INP and INN, taking one to 0 and the other to the voltage VDD.
FIGURE 6 illustrates a flow diagram of a method for providing a high speed sensing and reading through a sense amplifier circuit according to the present invention. At step 602, a voltage difference is sensed between a bit-line and a complementary bit line. At step 604, a first control signal is applied to enable a pull down circuit for actuating the sense amplifier circuit. At step 606, a second control signal is applied to disable a first PMOS transistor and a second PMOS transistor and to enable a first NMOS transistor and a second NMOS transistor to discharge an input capacitance of a first discharge device and a second discharge device. At step 608, the output is generated across latch output nodes of the sense amplifier.
The present invention describes a sense amplifier circuit, which offers many advantages. Firstly, the present sense amplifier provides high speed sensing and reading operations when used in a memory device. Secondly, the amplifier imposes low input capacitance on the bit-lines, which makes them discharge at a much faster rate. Thirdly, the amplifier utilizes a low resolution time.
«
Although the disclosure of system and method has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We claim:
1. A sense amplifier circuit providing a low capacitance with a low resolution time
comprising:
a latch circuit having a first inverter circuit cross coupled to a second inverter
circuit;
a first discharge device operatively coupled to said first inverter circuit;
a second discharge device operatively coupled to said second inverter circuit;
a first PMOS transistor operatively coupled between said first discharge device
and a bit line;
a second PMOS transistor operatively coupled between said second discharge
device and a complementary bit line;
a first NMOS transistor operatively coupled between said first discharge device
and a ground voltage;
a second NMOS transistor operatively coupled between said second discharge
device and the ground voltage;
a pull down circuit operatively coupled between said latch circuit and the ground
voltage;
a delay circuit operatively coupled among the first PMOS transistor, the second
PMOS transistor and said pull down circuit for producing a delay between a first
control signal and a second control signal; and
a first NOT gate operatively coupled to a first latch output node and a second
NOT gate operatively coupled to a second latch output node to provide an output
data corresponding to a data stored in a memory cell.
2. The circuit of claim 1, wherein said first discharge device comprises an NMOS transistor.
3. The circuit of claim 1, wherein said second discharge device comprises an NMOS
transistor.

4. The circuit of claim 2, wherein said first discharge device having a source and a drain
terminal operatively coupled to a corresponding source and a drain terminal of an NMOS
transistor of the first inverter circuit and a gate terminal of the first discharge device is
operatively coupled to a drain terminal of the first PMOS and the first NMOS transistor.
5. The circuit of claim 3, wherein said second discharge device having a source and a drain
terminal operatively coupled to a corresponding source and a drain terminal of an NMOS
transistor of the second inverter circuit and a gate terminal of the second discharge device
is operatively coupled to a source terminal of the second PMOS and to a drain terminal of
the second NMOS transistor.
6. The circuit of claim 1, wherein said pull down circuit comprises an NMOS transistor.
7. The circuit of claim 1, wherein said pull down circuit having a gate terminal for receiving
the first control signal, a drain terminal operatively coupled to said latch circuit, and a
source terminal connected to the ground voltage.
8. The circuit of claim 1, wherein said delay circuit comprises two serially connected
inverters.
9. A sense amplifier circuit providing a low capacitance with a low resolution time
comprising:
a latch circuit having a first inverter circuit cross coupled to a second inverter
circuit;
a first pull down circuit receiving a first control signal;
a second pull down circuit receiving a second control signal;
a first discharge device operatively coupled between the first inverter circuit and
the first pull down circuit;
a second discharge device operatively coupled to the second inverter circuit and
the first pull down circuit;

a first PMOS transistor operatively coupled between said first discharge device
and a bit line;
i a second PMOS transistor operatively coupled between said second discharge
device and a complementary bit line;
a first NMOS transistor operatively coupled between said first discharge device
and the ground voltage;
a second NMOS transistor operatively coupled between said second discharge
device and the ground voltage; and
a delay circuit operatively coupled among the first PMOS transistor, the second
pull down circuit and the first pull down circuit for producing a delay between the
first control signal and the second control signal to provide a low capacitance with
a low resolution time.
10. The circuit of claim 9, wherein said first pull down circuit having a drain terminal
operatively coupled to a source terminal of the first discharge device and the second
discharge device, a source terminal connected to the ground voltage and a gate terminal
receiving the first control signal.
11. A method for high speed sensing and reading operations through a sense amplifier circuit
comprising:
sensing a voltage difference between a bit-line and a complementary bit line; applying a first control signal to enable a pull down circuit for actuating the sense amplifier circuit;
applying a second control signal to disable a first PMOS transistor and a second PMOS transistor and enabling a first NMOS transistor and a second NMOS transistor to discharge an input capacitance of a first discharge device and a second discharge device; and
generating an output across latch output nodes of the sense amplifier circuit. 12. A sense amplifier circuit providing a low capacitance with a low resolution time substantially as herein described with reference to the accompanying drawings.

13. A method for high speed sensing and reading operations through a sense amplifier circuit substantially as herein described with reference to the accompanying
drawings.