1. A signal demodulating apparatus for inversely converting an N-bit based code string to generate an M-bit based data string, where M and N are integers having a relation of M

The present invention relates a signal demodulating apparatus. This application is a divided out of Indian Patent Application No. 1267/DEL/95 filed July 7, 1995, for title "A SIGNAL MODULATING METHOD AND APPARATUS FOR CONVERTING AN M-BIT BASED DATA STRING INTO AN N-BIT BASED CODE STRING" This invention relates to a signal modulating method and a signal modulating circuit employed for recording digital speech signals, digital video signals and digital data signals. More particularly, it relates to a signal modulating method and a signal modulating circuit which may be employed for a mastering device for a replay-only optical disc or a recording/reproducing apparatus for once-write optical disc or an overwrite type optical disc. RELATED ART When recording digital signals, such as digital speech, video or data signals, error correction code data is first appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by channel coding into the code suited to the characteristics' of a recording/reproducing system. An optical disc, such as, for example, a compact disc (CD), is a recording medium having a wide field of application as a package medium for the picture information or as a storage device for a computer. The optical disc system reproduces signals recorded on a reflective surface of the disc via a transparent substrate having a thickness of the order of 1.2 mm. On the optical disc is recorded the information such as digitized audio signals, video signals or digital data. At this time, the error correction code data is appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by so-called channel coding into code data suited to the characteristics of the recording/ reproducing system. The signal format of the above-mentioned compact disc (CD) system is summarized as follows: sampling frequency 44.1 kHz number of quantizing bits 16 (linear) modulation system EFM channel bit rate 4.3218 Mb/s error correction system CIRC data transmitting rate 2.034 Mb/s The modulation system employed is 8-14 conversion or EFM. With the EFM, an input 8-bit code, referred to hereinafter as a symbol, is converted into a 14 channel bit code, to which a synchronization signal of 24 channel bits and a subcode of 14 channel bits are appended and the neighboring codes are interconnected by merging bits of 3 channel bits. The resulting data is recorded by the NRZI modulation system. Fig.12 shows a frame structure of the CD system. Referring to Fig.12, 24 symbol data (music signals) and 8 symbol parity, entering a modulating circuit from a cross-interleave Reed-Solomon code (CIRC) encoder during a sync frame (6 sample value domains, six samples each of the L and R channels, with each sample being 16-bit data) are transformed into 14 channel bits and connected by merging bits of three channel bits to give 588 channel bits per frame. The resulting data is recorded by the NRZI system at a channel bit rate of 4.3218 Mbps. The respective symbols entering the modulating circuit are transformed, by having reference to a lookup table ROM, into a channel bit pattern in which the number of "0"s between "1" and "1" is not less than 2 and not more than 10. The channel bit pattern of a frame synchronization signal Sf is "100000000001000000000010". As for the merging bit pattern, one of "000", "001", "010" and "100" is selected. Each sub-coding frame is made up of 98 frames. As the subcode for the 0'th and first frames, the subcode sync signal SO (="00100000000001") and SI (= "00000000010010") are appended (see Fig.13). Fig.14 shows, for a typical sample value of input data, a channel bit pattern after EFM and a'digital sum variation (DSV). Each 16-bit sample is split into upper 8 bits and lower 8 bits each of which is entered to the modulation circuit via a CIRC encoder for 8-14 conversion to produce 14 channel-bit information bits. Not less than 2 and not more than 10 "0"s are interposed between "1" and "1" of the information bits, as previously described. One of the merging bits "000", "001", "010" and "100" is selected. This rule is observed at all times at the connecting portions of the 14 information bits, so that EFM signals based on 17-channel bits are generated and outputted from the modulating circuit at 4.3218 Mbps. The number of channel bits is 27 in the case of the frame synchronization signal Sf. Since not less than 2 and not more than 10 channel bits are interposed between an optional channel bit "1" and the next channel bit "1", the period during which the high level or the low level of the NRZI recording waveform continues, that is the recording wavelength, is necessarily not less than 3T and not more than 11T (see Fig.14). In this case, the shortest recording waveform is 3T and the longest recording wavelength is 11T, with T being a period of a channel clock of 4.3218 MHz. This is referred to hereinafter as the 3T-11T rule of the EFM modulation regulation. The digital sum value or variation (DSV) is now considered as an index of the dc balance of the NRZI recording •/waveform. The DSV is given as a time integral of the recording waveform. That is, the variant of the DSV when the high level of the recording waveform has continued for a unit time T is +1, while the variant of the DSV when the low level of the recording waveform has continued for a unit time T is -1. The time change of DSV when the initial value of DSV at time tQ is assumed to be zero is given at the lower most portion of Fig.14. The modulated signal during the time since T1 until t2 is not monistically determined by the 17-channel bit pattern "01000001000001001", but depends on the modulated signals level at time tp that is on the ultimate level of the modulated signal waveform during the time interval from time tQ until time T1 (referred to hereinafter as CWLL). Thus the modulated signal waveform illustrated is that for the CWLL at time t0 being at a low level (CWLL = "0"). The modulated signal waveform for CWLL = "1" (high level) is inverted from the pattern for CWLL = "0" so that the high and low levels are inverted to low and high levels, respectively. Similarly, the DSV is also increased or decreased depending upon the CWLL, such that, if CWLL = "0" at time tQ, the DSV variant with the information pattern "01000100100010" (referred to hereinafter as 14 NWD), that is the DSV variant during the time period from tQ until tQ+14, is +2, as indicated in Fig.14. Conversely, if CWLL = "1" at time tn, 14 NWD = -2. The DSV variant since time tQ+14 until T1+14 is referred to as 17 NWD. The merging bits, inserted since time tQ+14 until time t1 is now explained. Of the four margin bits "000", "001", "010". and "100", "001" or "100" cannot be inserted under the above-mentioned 3T~llT rule, such that only "010" or "000" can be inserted. That is, if the number of "0"s at the trailing end of the previous information bit pattern, outputted before the merging bit, is B, and the number of "0"a at the leading end of the subsequently outputted current information bit pattern is A, since B=l and A=l, the leading and trailing ends of the merging bit must be "0" and "0", such that the merging bit pattern that can be inserted becomes "0X0", where X is arbitrary (don't care). In the lower most portion of Fig.14, there is shown the DSV with the bits "010" inserted as merging bits, by a solid line, while there is shown the DSV with the bits "000" inserted as merging bits, by a broken line. In general, the merging bits to be inserted at a connecting point need to be selected so that the 3T-11T rule of the modulation regulation will be met. Similarly, such merging bits are prohibited which, when inserted, will produce a repetition by two times of a 11T pattern which is the same as the 11T frame synchronization pattern. Of the merging bits satisfying the above requirements, such merging bits are selected as optimum merging bits which, when inserted, will produce the smallest absolute value of the cumulative DSV from the merging bit until the end of" the next information bit pattern connected to the prevailing cumulative DSV. In the example of Fig. 14, the DSV at time T1+14 when the merging bits "010" are inserted is +3, while the DSV at the same time point when the merging bits "000" are inserted is -1, so that the merging bits "000" are selected. The merging bits, found by the above-described algorithm, satisfy the 3T-11T rule of the modulation regulation at the connecting portion between two 14-bit data, while prohibiting generation of an erroneous frame sync signal and approaching the cumulative DSV of the EFM signal to a value as close to zero as possible. Problem to be Solved by the Invention Meanwhile, with the conventional EFM system, since the shortest run-length is limited to two, two merging bits suffice if for the purpose of coping with run-length limitations. If the number of the merging bits can be reduced to two, the data recording density may be increased by a factor of 17/16 without altering the physical size such as the recording wavelength. However, there are only three sorts of the 2-bit merging bits. In addition, it is a frequent occurrence that only one of the three sorts of the merging bits can be inserted because of limitations such as those imposed by run-length. Thus, with the conventional DSV control system, there exist a large number of domains in which it is impossible to control the DSV. The result is that low-frequency components of the modulated signals cannot be sufficiently suppressed to affect servo stability or the data error rate on data demodulation. In view of the foregoing, it is a principal object of the present invention to provide a signal modulation method and a signal modulation circuit whereby the input M bits, such as an input 8-bit code string, is directly transformed into N-channel bits, such as 16 channel bits, without employing the above-mentioned merging bits at the time of signal modulation, thereby reducing ill effects on the DSV control and also enabling sufficient suppression of the low-frequency components. Means to Solve the Problem For accomplishing the above object, the present invention provides a signal modulating method for converting an input M-bit code string into an N-channel bit pattern, where M and N are integers, with M < N, and for directly connecting the N-channel bit pattern to the next following N-channel bit pattern, wherein the improvement resides'in that a conversion table for converting an input M-bit code string into the N-channel bit pattern is partially duplexed and the duplexed portions of the conversion table are designed so that the codes of each of mutually associated code sets are such codes in which the DSV variants are opposite in sign and close to each other in absolute value, with codes having larger absolute values of the DSV variant being arrayed in said duplexed portions. According to the present invention, there is also provided a signal modulating method for converting an input M-bit code string into an N-channel bit pattern, where M and N are integers, with M < N, and for directly connecting the N channel bit pattern to the next following N channel bit pattern, wherein a conversion table for converting the M-bit code string into the N-channel bit pattern is formulated by the steps of selecting those bit patterns satisfying a modulation rule from among the total N channel bit patterns, classifying the selected bit patterns into a plurality of unit tables switchingly selected depending on the directly previous bit pattern, calculating the variants of the digital sum variation for each of the bit patterns of said unit tables, arraying the bit patterns in the order of the decreasing values of the calculated variants of the digital sum variation, and allocating the codes with the larger absolute values of the digital sum variations in the duplexed portions and allocating the codes with the smaller absolute values of the digital sum variations in the non-duplexed portions. The signal demodulating apparatus for carrying out the signal modulating method has the above-mentioned conversion table and means for comparing the cumulative digital sum variation values of the N-channel bit patterns in the duplexed portions of the conversion table of the input M-bit code string and selecting the bit pattern with a smaller digital sum variation value. The signal demodulating apparatus for demodulatxng—rare-signal obtained by modulation with the above-described signal modulating method and apparatus demodulates the modulated output signal on the N-channel bit pattern basis using a back-conversion table effecting the reverse of the converting operation by the conversion table to produce the M-bit code string signal. Preferably, means for pre-reading the code of a N-channel bit directly previous to the current code is provided in demodulating the N-channel bits of the modulated output signal, and the signal is demodulated using the pre-read N channel bits as well. In the above-described signal modulation method and apparatus or in the signal demodulating apparatus, the conversion table is made up of a plurality of unit tables for converting the input M-bit code string into the N channel bit pattern for satisfying a pre-set modulation rule, and conversion is performed whilst these unit tables are changed over appropriately. When converting the input 8-bit code string into the 16 channel bit pattern, with the input code string being of 8 bits, the channel bit pattern satisfies a modulation rule specifying the minimum wavelength of 3T and the maximum wavelength of 11T, T being a channel clock period. Codes are arrayed in the conversion table in the decreasing order of the variant of the digital sum variation and the duplexed portions are made up of codes with larger variation of the digital sum variation in the positive direction and codes with larger variation of the digital sum variation in the negative direction. Specifically, the concept of the merging bits itself is discarded and a table is provided for converting the input signal, such as an input 8-bit signal, into a 16 channel bit code. By this table, the symbols converted to the 16 channel bits code are connected to one another without merging bits. Depending on the previous and succeeding codes, such connection becomes impossible due to limitations imposed by the' run length, such as 3t~llT rule. For handling this inconvenience, the modulating circuit of the present invention has plural conversion tables, and means are provided for switching the tables used for conversion depending on the type of the codes modulated directly previously. The signal modulating apparatus of the present invention includes, as means for switching the tables depending on the type of the codes modulated directly previously, there is provided a separate reference table for prescribing the table sort to be employed for converting the symbol modulated directly subsequently, while there is also provided a table switching unit for switching the tables in use while having reference to the reference table. When producing these plural tables, there is provided means for producing a table having characteristics of possibly increasing the DSV in the positive -direction, or a front side table, and a table having characteristics of possibly increasing the DSV in the negative direction, or a back side table, for achieving sufficient suppression of the low-frequency components of the modulated signal. There are also provided, for sufficiently suppressing the low-frequency components in the modulated signal, means for calculating the cumulative DSV value when effecting conversion with the aid of the front side table, means for calculating the cumulative DSV value when effecting conversion with the aid of the back side table and means for judging which of the cumulative DSV values is smaller in absolute value for determining which of the front side table or the back side table is to be employed. With the codes produced on modulation with the present modulation system, there are occasions wherein the plural sorts of the 8-bit symbols are converted into the same 16 channel bit code. For correctly decoding these codes, the demodulating circuit of the present invention has means for previously acquiring and storing another symbol, that is another 16 channel bit code, and means for producing a 8-bit symbol using both the 16 channel bit code to be decoded and the partial or total information in the pre-read 16 channel bit code. Operation With the constitution of the present invention, since the duplexed portions of the conversion table are designed so that the codes of each of two associated code sets are such codes in which the DSV variants are opposite in sign and close to each other in absolute value, DSV control can be achieved by selecting one of the duplexed portion and the non-duplexed portion. In addition, the codes having larger absolute values of the DSV variant are arrayed in the duplexed portion in the conversion table for achieving sufficient suppression of the low-frequency components of the modulated signals. In addition, by having plural sorts of the conversion tables, and switching the tables to be used for the next conversion depending upon the directly previous code, symbol interconnection becomes possible without employing merging bits. Low-frequency components in the modulated signal can be suppressed by preparing two sorts of tables affording mutually inverse operations to the cumulative DSV, that is a positive operation and a negative operation, and by suitably switching the two sorts of the table for modulation. The modulated signal modulated in accordance with the present system can be decoded by pre-reading a superfluous N-channel bit pattern and decoding a modulated signal in conjunction with the pre-read N-channel bit pattern. Specifically, the 8-bit input signal, converted with the conventional method into 14-bit information bits and three merging bits, thus totalling at 17 bits, can be converted into a 16-channel bit code. Embodiments The signal modulation method according to the' present invention is presupposed on converting an input M-bit code string into a N-channel bit pattern, M and N being integers with M < N, and on directly connecting the N-channel bit pattern to the next N-channel bit pattern. The conversion table for converting the M-bit code string into the above-mentioned N-channel bit pattern is partially duplexed. The duplexed portions are configured so that the variants of the DSV of the codes of each of two mutually associated code sets are opposite in sign and close to each other in the absolute value. The present invention provides a signal modulating method for creating an optical disc recording medium on which a recording signal is formed by converting an M-bit based data string into an N-bit based code string, where M and N are integers having a relation of M receiving the M-bit based data string as a first data word of a plurality of data words; translating the first data word into a first code word from a first table of a plurality of primary and secondary code word tables, wherein the secondary code word tables are associated with only a portion of the data words; determining whether the plurality of secondary code word tables can be used for translating a second data word into a second code word based on a value of the second data word; if the plurality of secondary code word tables can be used for translating the second data word, then determining whether the plurality of primary code word tables or the plurality of secondary code word tables is to be used for translating a second data word into a second code word based on a DSV value; determining which one of the plurality of code word tables is to be used based on a previous data word; and wherein there is at least a general progression of DSV values for the code words in each of the plurality of primary tables from at least substantially a relative maximum DSV associated with a minimum data word value toward a relative minimum DSV associated with a maximum data word, and further wherein there is at least a general progression of DSV values for the code words in the secondary tables from at least substantially a relative minimum DSV toward relative maximum DSV and wherein the code words in the secondary tables are associated with a portion of the data words in a progression from at least substantially a minimum data word value toward a maximum value. The present invention also provides a signal modulating apparatus for carrying out the above-mentioned method, the apparatus comprising: an input unit operable to input the M-bit based data string as an input signal value; a processor to convert the M-bit data into the N-bit code in accordance with a conversion table; and an output unit to output the N-bit based code string as a modulation result; wherein the processor being connected to a memory to store the conversion table comprises a plurality of primary and secondary code word tables, each of said primary and secondary code word tables provided in groups of tables, said groups of primary and secondary tables each respectively containing binary values which all have a pattern of at least some binary digits associated with the respective group; said primary code word tables containing code words in one-to-one correspondence with a plurality of available data words and provided at least generally in a progression of DSV values from at least substantially a relative maximum DSV associated with a minimum data word toward a relative minimum DSV associated with a maximum data word; said secondary code word tables containing code words which correspond only with a portion of the available data words and wherein code words from said secondary tables have DSV values which are arranged at least generally in a progression of DSV values from at least substantially a relative minimum DSV toward relative maximum DSV and wherein the code words in the secondary tables correspond with a portion of the data words from at least substantially a minimum data word value toward a maximum value. The invention of this divisional application relates to a signal demodulating method for inversely converting an N-bit based code string to generate an M-bit based data string, where M and N are integers having a relation of M T2b_s, T3a-s' T3b-s' T4a-s and T4b-s *n association with the code tables Tla, Tlb' T2a' T2b' T3a' T3b' T4a and T4b' respectively. These tables Tla_g to T4b_g receive addresses determined from the three parameters, namely the 8-bit input signal values, the current state values and the value indicating which of the front side table or the back side table is to be employed, and finds out the associated next state value. The address generating circuit 14 acquires the 8-bit input signal and the current state value supplied from the state value storage memory 13 in order to generate an address for producing from the 16-bit code table ROM 23 an address for acquiring the 16-bit code in case of employing the first table to transmit the address to a read-out circuit 15. The read-out circuit 15 receives the address signal from the address generating circuit 14 and, using the address signal, acquires a 16-bit code from the 16-bit code table ROM 23. This code is transmitted to a cumulative DSV calculating circuit 16. The cumulative DSV calculating circuit 16 calculates, from the 16-bit code received from the read-out circuit 15 and from the current cumulative DSV value received from the cumulative DSV storage memory 25 the value of the cumulative DSV resulting from employing the 16-bit code and transmits the calculated cumulative DSV value to a comparator circuit 20. The address generating circuit 17 receives the 8-bit input signal and the current state value from the state value storage memory 13. The address generating circuit 17 also generates an address resulting from employing the second table from the 16-bit code table ROM 23 and routes the address to a read-out circuit 18. The read-out circuit 18 receives the address signal from the address generating circuit 17 and, using the address signal, produces a 16-bit code from the 16-bit code table ROM 23. This code is routed to a cumulative DSV calculating circuit 19. The cumulative DSV calculating circuit 19 calculates, from the 16-bit code received from the read-out circuit 18 and the value of the current DSV received from the cumulative DSV storage memory 25, the value of the cumulative DSV resulting from employing the 16-bit code, and transmits the calculated value to a comparator circuit 20. The comparator 20 acquires, from the cumulative DSV calculating circuit 16 and the cumulative DSV calculating circuit 19, the value of the cumulative DSV in case of effecting the conversion using the first table and the value of the cumulative DSV in case of effecting the conversion using the second table and compares the corresponding absolute values to each other. Which of the tables gives the smaller absolute value of the cumulative DSV is determined and a signal indicating which table is to be employed is transmitted to the selector 12. If instructed by the comparator 10 to enter the DSV control mode, the selector 12 routes a signal indicating which of the first and second tables is to be employed to the address generator 21. If instructed by the comparator 10 not to effect the DSV control, the selector 12 issues a signal to the address generator 21 for instructing the address generator 21 to use the first table in any case. Using the value of the 8-bit input signal, the current state value received from the state value storing memory 13 and the signal from the selector 12 indicating as to which of the first or second tables is to be employed, the address generator 21 generates an address for acquiring the 16-bit code from the 16-bit code table ROM 23 and an address for acquiring the next state value from the next state value decision table ROM, and transmits the addresses to read-out circuit 22 and 26. The read-out circuit 22 receives an address signal from the address generator 21 and, using the address signal, acquires the 16-bit code from the 16-bit code table ROM 23. This code is the 16-bit code output which is issued from the present modulator. The read-out circuit 22 also transmits the 16-bit code to a cumulative DSV calculating circuit 24. The cumulative DSV calculating circuit 24 calculates, for the 16-bit code received from the read-out circuit 22 and the cumulative DSV received from the cumulative DSV storage memory 25, the value of the cumulative DSV which will prevail after using the 16-bit code, and updates the contents of the cumulative DSV storage memory 25 with the calculated value. The read-out circuit 26 receives the address signal from the address generating circuit 21 and, using the address signal, acquires the next state value from the next state value decision table ROM 27. The read-out circuit 26 outputs the next state value to the state value storage memory 13 for updating its storage contents. In Fig.9, a curve A shows low-frequency components, as found by Fourier transform, of a recording waveform produced on modulating input-8-bit sample signals using the above-described signal modulating method and apparatus of the present invention. On the other hand, a curve B shows low-frequency components of a recording waveform produced on modulating the same sample signals using a conventional EFM system and Fourier transforming the generated recording waveform, while a curve C shows low-frequency components of a recording waveform produced on modulating the same sample signals using a system corresponding to the conventional EFM system having two merging bits and Fourier transforming the generated recording waveform. It is seen from the curves A, B and C of Fig.9 that, with the present embodiment, the low-frequency components may be lowered to a level substantially equal to that achieved with the conventional EFM system, despite the fact that the modulation efficiency is equivalent to that of the conventional EFM system with the two merging bits, that is equal to 17/16 times that of the conventional EFM system. The method of receiving the signal modulated with the modulating system of the present invention and demodulating the received signals to original 8-bit signal will now be explained. With the conventional EFM system in which the 14-bit information bits are associated with the 8-bit input signal in a full one-to-one relationship, back conversion from the 14-bit information bits to the 8-bit signals can be achieved without any inconvenience. With the embodiment of the present invention, there are occasions wherein the same 16-bit signals are allocated to different 8-bit input signals, so that the demodulator cannot effect the back conversion on simply receiving the 16-bit codes. Thus, if the demodulator of the present embodiment cannot effect back conversion on reception of a 16-bit code, it receives another symbol, that is another 16-bit code, in order to effect back conversion based upon the two symbols. The algorithm of the demodulating system of the present embodiment is shown in Fig.10. The sum of the demodulation algorithm shown in Fig. 10 is now explained. The 16-bit code which can be allocated in common to two totally different values of the input 8-bit signals is necessarily of the type in which the state value is changed next time to [2] or [3], as previously explained. In addition, if the state value to which one of such 16-bit codes transfers next is 2, the state value to which the other of the 16-bit codes transfers next is necessarily 3. The table employed for the state value of [2] is made up of codes each of which has the first bit and the 13th bit equal to 0, with the MSB being the first bit, while the table employed for the state value of [3] is made up of codes each of which has one or both of the first bit and the 13th bit equal to 1, with the MSB being the first bit. From these conditions, if the state value of the 16-bit code about to be back-converted transfers to [2], the next oncoming 16-bit code has both the first bit and the 13th bit equal to 0, whereas, if the state value of the 16-bit code about to be back-converted transfers to [3], the next oncoming 16-bit code has one or both the first bit and the 13th bit equal to 1. Thus, if the demodulator on reception of a 16-bit code is unable to effect the back-conversion, it receives another symbol (16-bit code) at step S25 of Fig.10 in order to check the first and the 13th bits at step S26. Thus it is checked at step S27 if both of these bits are "0". If the result of judgment at step S27 is YES, that is if both of the bits are "0", the 16-bit code about to be back-converted is the code the state value of which transfers next to [2]. If the result of judgment at step S27 is NO, that is if one or both of the bits are "1", the 16-bit code about to be back-converted is the code the state value of which transfers next to [3]. This enables back-conversion to be effected monistically. Taking an illustrative example, this operation is explained by referring to the conversion table of Fig.l. In the case of the front side table T1a of the unit table T, of the conversion table of Fig.l, with the state value equal to 1, the 16-bit codes for 8-bit input signals "5" and "6" are both "0010000000100100". Thus the demodulator on reception of the code "0010000000100100" cannot effect the back-conversion. In such case, the demodulator reads another symbol. If the code thus read is "0010000000001001", for example, this code is a code which has been converted for the state value [3], because the 13th bit of the code is "1". If the code is the same code, herein "0010000000100100", the state value next transfers to [2] or to [3] if the input signal value is "5" or "6", respectively, the demodulator can effect correct decoding, that is it can judge the input signal to be such signal the state value of which transfers next time to [3], that is "6". If, in the flow chart of Fig.10, the 16-bit code is entered at step S21, reference is had to the conversion table at step S22 and it is found at step S23 that decoding can be achieved monistically, the program may naturally proceed to step S24 to output the decoded 8-bit signal. Fig.11 shows, in a block diagram, an illustrative construction of a signal demodulator embodying the present invention. In Fig. 11, a 16-bit input code is routed to a 1-symbol delay circuit 31 and an AND gate 34. The 1-symbol delay circuit 321 delay the input 16-bit code by one symbol. The 16-bit code, thus delayed by one symbol, is routed to a decoding table ROM 32 having a first table for decoding ITa therein and to a decoding table ROM 33 having a second table for decoding ITb therein. The decoding table ROM 32, having the first table for decoding ITa therein, receives the 16-bit code to effect back-conversion to output a 8-bit signal. If the code is the 16-bit code of the type which by itself does not permit back-conversion monistically, the demodulator after outputting the 16-bit code outputs a 8-bit signal the state value of which transfers to [2]. The 8-bit output signal value is routed to a judgement circuit 35. Similarly to the decoding ROM 32, the decoding ROM 33, having the second table for decoding ITb therein, receives the 16-bit code and effects back-conversion to output a 8-bit signal. If the 16-bit input code is such code as permits monistical back-conversion, it outputs nothing or outputs special data. If the 16-bit code is such a code which by itself does not permit monistical back-conversion, the modulator after outputting the code outputs a 8-bit signal value the state value of which transfers to [3]. The 8-bit signal, thus outputted by the modulator, is routed to the judgement circuit 35. The AND circuit 34 takes AND of the input 16-bit code and a 16-bit code "1000 0000 0000 1000" from a comparison value generating circuit 36, which in hexadecimal notation is "8008", in order to check the first and 13th bits of the input 16-bit code, and outputs "0" and "1" if the bits of the 16-bit AND outputs are all "0" and otherwise, respectively. Since "8008" is such a code in which only the first bit and the 13th bit are "1" and the remaining bits are "0", with the MSB being the first bit, the output of the AND gate 134 is "0" or "1" if both the first bit and the 13th bit are "0" or if one or both of the first bit and the 13th bits are "1", respectively. The judgement circuit 35 receives the signal from the AND circuit 34 and the 8-bit signal values supplied from the first table ROM for decoding 32 and the second table ROM for decoding 33. First, if no 8-bit signal is routed or special data is routed from the second table ROM for decoding 33, it indicates that the 16-bit input code has been decoded monistically to the 8-bit signal, so that the judgement circuit 35 directly outputs the 8-bit signal value routed from the first table for decoding 32 as an output signal. If the 8-bit signal value is supplied from the second table ROM for decoding 33, it indicates that the input 16-bit code has not been able to be decoded monistically to the 8-bit signal value. Since the data fed from the first table for decoding 32 and the second table for decoding 33 have been passed through the on-symbol delay circuit 31, these signals are codes pre-read by one symbol. Thus, if the 16-bit code entering the AND gate 34 is the code converted for the state value of [2], that is if the output signal of the AND gate 34 is "0", the judgement circuit 35 outputs the 8-bit signal, received from the first table ROM for decoding 32, as an output signal. On the other hand, if the 16-bit code entering the AND gate 34 is the code converted for the state value of [3], that is if the output signal of the AND gate 34 is "1", the judgement circuit 35 outputs the 8-bit signal, received from the second table ROM for decoding 33, as an output signal. The above-described embodiment of the present invention is preferably applied above all to modulation or demodulation in recording digital speech, video or data on a high-density optical disc. The following is a typical signal format in the high-density optical disc: modulation system a sort of 8-16 conversion channel bit rate 24.43 Mbps error correction system CIRC data transmission rate 12.216 Mbps The present invention is not limited to the above-described embodiments. For example, the number of bits N of the input signal or the number of channel bits M of the converted output signal is not limited to N=8 or M=16, but may be set to desired arbitrary values. Effect of the Invention With the present invention, as described above, since the duplexed portions of the conversion table are designed so that the codes of each of two associated code sets are such codes in which the DSV variants are opposite in sign and approximate to each other in absolute value, the low-frequency components of the modulated signal can be suppressed satisfactorily. Since plural sorts of the conversion tables are provided and the table to be employed for the next conversion s changed over depending on the directly previous code, it becomes possible to connect respective N-channel bits without employing merging bits. By providing two sorts of conversion tables affording opposite operations, that is a positive operation and a negative operation, on the cumulative DSV, and by carrying out modulation while these two sorts of the tables are changed over appropriately, the low-frequency components of the modulated signals can be suppressed sufficiently. In contrast to the 8-14 conversion (EFM) customarily employed in CDs, 8-bit input signals can be converted into 16 channel bit codes without employing merging bits. That is, in contrast to the conventional method in which a 8 bit pattern is converted into a 14-bit information bit pattern and three merging bits, thus totalling at 17 bits, the data recording density may be raised by a factor of 17/16, while the low-frequency components are suppressed. For raising the recording density, it may be contemplated to convert the 8-bit symbol into 14 information bits plus two merging bits, thus totalling at 16 bits. In contrast to this method, the low-frequency components of the modulated signals can be suppressed sufficiently because two sorts of conversion tables affording inverse operations, that is positive and negative operations, on the cumulative DSV, are provided, and modulation is carried out whilst these two sorts of tables are changed over appropriately. In addition, the signals modulated n accordance with the present system may be decoded by pre-reading an additional symbol and performing decoding the signal in conjunction with the additional symbol. WE CLAIM: 1. A signal demodulating apparatus for inversely converting an N-bit based code string to generate an M-bit based data string, where M and N are integers having a relation of M