We claim:

1. A single board common control hardware platform for use in variety of application comprises of a digital signal processor, a field-programmable gate array, analog to digital converters, a digital to analog converter, a random access memory, a flash memory, Ethernet ports, a dynamic random access memory, configurational random access memory, a real time clock, a power monitor and a plurality of analog and digital input/output channels. , Description:[018] While the embodiments of the disclosure are subject to various modifications and alternative forms, specific embodiment thereof have been shown by way of example in the figures and will be described below. It should be understood, however, that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alterative falling within the scope of the disclosure.
[019] As used in the description herein and throughout the claims that follow, the meaning of "a," "an," and "the" includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.
[020] The terms "comprises", "comprising", or any other variations thereof used in the disclosure, are intended to cover a non-exclusive inclusion, such that a device, system, assembly that comprises a list of components does not include only those components but may include other components not expressly listed or inherent to the system, or assembly, or device. In other words, one or more elements in a system or device proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system, apparatus or device.
[021] Hereinafter, a single board common control hardware platform will be discussed in more detail.
[022] Referring to figure 1 which illustrates block diagram of the single board common control hardware platform. The single board common control hardware platform comprises DSP TMS320F28335 and Cyclone V SOC 5CSEBA4U23A7N, 672-pin UBGA package Altera FPGA. Altera Cyclone V SOC which includes the Hard Processor System (HPS) with integrated ARM® Cortex™-A9MP Core processor and soft NEOS processor. 8GB fixed + 8 GB Removable flash memory + 4 GB RAM available in the module. The modules has many High speed peripherals i.e. 2 Ethernet ports, 2 CAN ports, USB port, 2 RS485 & 2 RS232. 40 Analog inputs, 4 analog outputs, 32 isolated Digital inputs, 36 isolated digital outputs, 14 PWM signals and 5 speed signals are available in the board. The PCB design was done using PCB design CAD tools for Signal integrity, Thermal analysis, Power analysis and EMI/EMC analysis. DSP processor is used for processing/PWM generation and FPGA is used for protection and communication.
[023] Technical details: Analog Inputs (Current, voltage and 3 wire RTD temperature). The analog inputs section consists of circuitry for supporting 40 analog signals coming from the sensors. 16 channel to FPGA, 16 channels to DSP and 8 channel 3 wire RTD inputs to FPGA. Each channel can take analog input range, ± 1.5V (± 10V). 16 channel analog inputs to FPGA is provided thro’ external ADC and 16 channel input to DSP has been provided using internal ADCs of the DSP. Analog input signals can be either current or voltage. Each channel is provided with two burden resistors, 0.5W each, 1206 package for current inputs, provision has been made to mount 100k, 0.125W resistor if input is voltage. The resistor values in the gain circuit will be changed for different input ranges. All 32 analog signals are having LC filter for EMI/EMC protection, TVS diode arrays IC, SP723ABTG from Little fuse is used at the input of all 32 channel for ESD protection and to clamp the input voltage level to ± 12V.
[024] PT100 Resistor temperature Detector (RTD), 8ch available. The signal from the temperature sensor is amplified and filtered by the RTD circuit. ADC, 8 Channel, 1 MSPS, ultra low power, INL ± 0.7LSB, 12 bit SAR ADC, small footprint, AD7091R-8BRUZ from Analog device is used to provide total 8 channel temperature, digital data to FPGA. A channel sequencer in the IC will allow a preprogrammed selection of channels to be converted sequentially. The AD7091R also feature an on-chip conversion clock, an on-chip accurate 2.5V reference and a high speed serial interface.
[025] All the data and important / faster control / status signals from the field are connected to FPGA thro’ 16 bit, 16 channel ADC from Analog devices. The parallel outputs of the ADC are connected to the FPGA. As the ADC has an internal driver, clamping circuit and digital filter, an external driver IC is not used. A reset signal to ADCs comes from the processor section. These critical signals can be taken to the DSP thro’ a data /address bus between DSP & FPGA for further processing at DSP. ADC, AD7616BSTZ from Analog devices, is used for converting 16 channel analog data to digital data.
[026] Analog outputs: Four channel, 16 bit DAC from Analog device is used to provide a total of 4 channel of two current outputs and two voltage outputs.
[027] Digital Inputs: Totally 42, isolated, digital inputs are provided, out of which 24 digital inputs signals are connected to FPGA and 10 digital input signals are connected to DSP. In addition ,8 high speed signals are provided for functioning in high speed mode. These high speed signals are connected to DSP. Small footprint Opto Isolator MOCD207M, Dual channel, Input-output Isolation of 2500 VAC(RMS) from Fairchild is used for field isolation. For the high speed inputs, Avago’s dual channel, high speed, Input-output Isolation of 4500 VAC(RMS), opto-coupler, ACPL-054L-500E is used for field isolation
[028] Digital outputs: Totally 38, isolated, digital output signals are provided, out of which 24 digital output signals are from FPGA and 8 digital output signals are from DSP. 8 Channel, high voltage, high current, with integrated clamping diode, darligton driver IC ULN2803ADW from Texas Instruments are used for level shifing the voltage from 3.3V to 15V. These signals are fed to opto coupler for field isolation. Vishay’s Opto-isolator, VOD223T, Dual channel, Input-output Isolation of 4000 VRMS, high Current transfer ratio, low current drive is used for field isolation and driving the output, each output can drive 24V, 25mA load.
[029] PWM signals from DSP: TMS320F28335 DSP supports 12 channel PWM outputs. The DSP chip has two independent event manager modules. MICREl’s Quad, 1.2A peak, 25nS rise/fall time, 2 input logic gate, MOSFET driver IC, MIC4468YWM used for driving the output signal. The driver IC can drive any load i.e. Capacitive, Inductive and resistive loads.
[030] QEP/ speed input to DSP: Texas Instrument’s IC AM26LV32E, low voltage high speed quadruple differential line receiver with ±15KV IEC IC AM26LV32EMDREP is used for interfacing Quadrature Encoder Pulse (QEP) signal to DSP. IC TPD4S009 ,4 channel, TVS diode arrays IC is used for ESD protection. LC filter is used for EMI/EMC protection.
[031] Referring to figure 2, which illustrates TMS320F28335 DSP features:
High performance Static CMOS Technology
- Upto 150MHz (6.67-ns Cyle Time)
- 1.9V/1.8V Core, 3.3V I/O design
High performance 32-Bit CPU
- IEEE-754 Single precision Floating point unit (FPU)
- 16 x 16 and 32 x 32 MAC Operations
- 16 x 16 Dual MAC
- Harvard Bus Architecture
- Fast Interrupt Response and Processing
- Unified memory Programming model
- Code efficient (in C/C++ and assembly)
Six channel DMA controller (for AADC Mc BSP, e PWM, XINTF and SARAM)
16Bit or 32 Bit External interface (XINTF)
- Over 2 Million x 16 Address reach
On–Chip memory
- 256K X 16 Flash, 34K X 16 SARAM
- 1K X 16 OTP ROM
Boot ROM (8K X 16)
- With software Boot modes ( via SPI, SPL, CAN, I2C, Mc BSP, XINTF and Parallel I/O)
- Standard Math Tables
Clock and system control
- Dynamic PLL change supported
- Watchdog timer module
- On chip oscillator
GPIO0 to GPIO63 can be connected to one of the eight external core interrupts
Peripheral Interrupt Expansion (PIE) block that supports all 58 peripheral inputs
128-bit Security Key/Lock
- Protects Flash/OTP/RAM Blocks
- Preventive Firmaware Reverse Engineering
Enhanced control peripherals
- Upto 18 PWM outputs
- Upto 6 HRPWM outputs with 150ps MEP resolution
- Upto 6 event capture Inputs
- Upt 2 quadrature Encoder interfaces
- Upto 8 32Bit /Nine 16 Bit timers
- Three 32 bit CPU timers
Serial port peripherals
- up to 2 CAN Modules
[031] Figure 3 illustrates architecture of a field-programmable gate array. The single board common control hardware platform board supports the following communication ports:
- 10/100/1000 Ethernet – 2ports
- UART
- SD
- I2C
- SPI – On board Temperature measurement
- CAN –
[032] 10 /100 /1000 Ethernet: The board supports two ports of 10/100/1000 base-T Ethernet using an external Micrel KSZ9021RNI PHY and HPS Ethernet MAC function. The PHY-to-MAC interface is RGMII interface. The Ethernet function must be provided in the Cyclone V SoC HPS (MAC) for typical networking applications. The Micrel KSZ9021RNI PHY uses 3.3-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator.
[033] UART –RS232: The board supports UART, one each from FPGA and DSP.
[034] RS485: The board supports Isolated RS485 -2 ports.
[035] CAN channels: The CCHP has three isolated CAN transceivers, 2 from FPGA and one from DSP.
[036] I2C: The board supports I2C Interface using Cyclone V SoC HPS I2C function.
[037] Real-Time Clock (HPS): The HPS system has a battery backed real-time clock (RTC) connected through the I2C interface. The RTC is implemented using a DS1339 device from Maxim Semiconductor. The device has a built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time. The device uses a supercap with a nominal voltage of 1.55 V. Using typical current capacity, the RTC is expected to have 48 backup hours
[038] Memory: The board has the following memory interfaces:
- DDR3-SDRAM
- QSPI FlashROM (QSPI device is supported. )
- eMMC FlashROM/ Micro SDCARD
- EEPROM
- DPRAM
- DDR3-SDRAM
[039] DDR3-SDRAM: The board supports two 32 Meg x 16 x 8 banks interfaces for high-speed sequential memory access. User can use hard memory controller (HPS on the top edge of the FPGA) to run DDR3 SDRAM memory. 32-bit data bus comprises of two x16 devices.
[040] QSPI Flash ROM: The board supports using Cyclone V SoC HPS QSPI function a 512Mbit Quad-SPI flash device for non-volatile storage of user code space.
[041] eMMC / SD card: The board supports SD card interface using Cyclone V SoC HPS SD function.
[042] EEPROM: The board supports using Cyclone V SoC HPS I2C function a 32kbit EEPROM device for MAC Address of Ethernet, Board identification.
[043] DPRAM: The board supports DPRAM using Cyclone V SoC FPGA 2Mbit Block RAM
[044] The FPGA contains 2700+231 kBytes of embedded memory, a part of this memory is configured as Dual Port RAM to serve as a communication channel between the FPGA ARM SOC processor and the DSP processor. For both the FPGA ARM SOC processor and the DSP processor this Dual Port RAM will be part of the external memory space.
[045] On board Oscillators: The board includes oscillators with a frequency of 25-MHz, 50-MHz, 100-MHz and 125-MHz.
[046] Power voltage monitoring and power-on reset: Monitoring circuit POWER_ON RESET watch the power voltages on the CCHP board. At power-on, power-down or if a power supply voltage fails (falls below its monitoring level), the power-on reset circuit generates a low going reset pulse, which is distributed to the FPGA ARM Soc. The FPGA ARM Soc resets the DSP; LED “PWR” signals the status of the board power voltages.
[047] The power supply voltages are monitored by Power supply monitoring and supervisors.

[048] Power supply distribution is illustrated in figure 4. The module gets +24V, ±15V and +5V, other voltages required for operations of the internal circuits would be generated internally.
Advantages of the present invention
[049] The present invention provides for a single board common control hardware platform that will reduce the complexity of usage of more than ten Input/output boards required for various applications.
[050] The present invention provides for a single board common control hardware platform which will have efficiency more than the prior art.
[051] The present invention provides for reliable single board common control hardware platform.
[052] The present invention provides for better speed of operation /real time as there is no bus is involved for Input/output communication.
[053] The present disclosure provides cost effective single board common control hardware platform as it is a compact single board solution with integrated I/Os.
[054] The present disclosure provides single board common control hardware platform which is easy to use and test.
[055] The present disclosure provides single board common control hardware platform which meets stringent vibration requirement as it is a single board solution.
[056] With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.
[057] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles, ‘a', or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations).
[058] The above description does not provide specific details of manufacture or design of the various components. Those of skill in the art are familiar with such details, and unless departures from those techniques are set out, techniques, known, related art or later developed designs and materials should be employed. Those in the art are capable of choosing suitable manufacturing and design details.
[059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. It will be appreciated that several of the above-disclosed and other features and functions, or alternatives thereof, may be combined into other systems or applications. Various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may subsequently be made by those skilled in the art without departing from the scope of the present disclosure as encompassed by the following claims.
[060] The claims, as originally presented and as they may be amended, encompass variations, alternatives, modifications, improvements, equivalents, and substantial equivalents of the embodiments and teachings disclosed herein, including those that are presently unforeseen or unappreciated, and that, for example, may arise from applicants/patentees and others.
[061] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.