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A Single Photon Emitter (Spe) And A Method Of Fabrication Thereof

Abstract: ABSTRACT A SINGLE PHOTON EMITTER (SPE) AND A METHOD OF FABRICATION THEREOF The present disclosure describes a single photon emitter (SPE). The SPE comprises a substrate layer (202), a metal film (204) deposited on the substrate layer (202), an array of nanopillars (210) fabricated on the metal film (204), in such a manner that each nanopillar of the array of nanopillars (210) has a predefined aspect ratio and is spaced apart from another nanopillar by a predefined distance, and a semiconductor layer (206) deposited on the array of nanopillars (210). A first part of the semiconductor layer (206) is in contact with a nanopillar, and a second part of the semiconductor layer (206) is in contact with the metal film (204). Further, the metal film (204) is configured to absorb one or more excitons from the second part of the semiconductor layer (206) to ensure emission of the stream of single photons from the first part of the semiconductor layer (206). [Figure 2A]

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
05 September 2024
Publication Number
37/2024
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
Parent Application
Patent Number
Legal Status
Grant Date
2025-07-07
Renewal Date

Applicants

Indian Institute of Science
C V Raman Road, Bangalore -560012, Karnataka, India

Inventors

1. Mayank Chhaperwal
Indian Institute of Science, C V Raman Road, Bangalore -560012, Karnataka, India
2. Kausik Majumdar
Indian Institute of Science,C V Raman Road, Bangalore -560012, Karnataka, India.

Specification

CLAIMS
WE CLAIM:
5
1. A single photon emitter (SPE), the SPE comprises:
a substrate layer (202);
a metal film (204) deposited on the substrate layer (202);
an array of nanopillars (210) fabricated on the metal film (204), in such a manner
10 that each nanopillar of the array of nanopillars (210) has a predefined aspect ratio and is
spaced apart from another nanopillar by a predefined distance; and
a semiconductor layer (206) deposited on the array of nanopillars (210);
wherein each nanopillar of the array of nanopillars (210) is fabricated of a material
that prevents disruption to structure of a first part of the semiconductor layer (206) and a
15 nanopillar on excitation introduces a strain on the first part of the semiconductor layer (206)
thereby allowing funnelling of a plurality of excitons from the first part of the semiconductor
layer (206) towards the excited nanopillar,
wherein an exciton from the plurality of excitons moves to a defect state created
on the first part of the semiconductor layer (206) and the exciton when released from the
20 defect state, emits a single photon, and
wherein the metal film (204) is configured to absorb one or more excitons from a
second part of the semiconductor layer (206), such that no photons are emitted from the
second part of the semiconductor layer (206) to ensure emission of the stream of single
photons from the first part of the semiconductor layer (206).
25
2. The SPE as claimed in claim 1, further comprises: one or more layers (208) of a dielectric
material deposited on the semiconductor layer (206) for reducing loss of excitons from the
semiconductor layer (206).
30 3. The SPE as claimed in claim 1, wherein the semiconductor layer (206) is fabricated of a
semiconductor having a direct bandgap.
4. The SPE as claimed in claim 1, wherein the predefined distance is defined such that the first
part of the semiconductor layer (206) is in contact with a nanopillar, and the second part of
35 the semiconductor layer (206) is in contact with the metal film (204).
5. The SPE as claimed in claim 1, wherein the predefined distance between each nanopillar is
defined based on:
spot size of an excitation source such that at a given time, a single nanopillar is
40 excited by the excitation source.
20
6. The SPE as claimed in claim 1, wherein the metal film (204) is fabricated from a metal
having reflectance that covers an emission wavelength range of the single photon emitter.
7. The SPE as claimed in claim 1, wherein the material for fabrication of each nanopillar
5 comprises a polymer-based photoresist.
8. The SPE as claimed in claim 1, wherein the predefined aspect ratio of each nanopillar is at
least 3:1.
10 9. The SPE as claimed in claim 1, wherein the second part of the semiconductor layer (206)
contacts the metal film at a predetermined distance from a center point of each nanopillar.
10. The SPE as claimed in claim 1, wherein the SPE further comprises:
a transparent gate electrode deposited on the one or more layers (208) of a dielectric
15 material, wherein the transparent gate electrode enables application of a gate voltage, to
electrostatically tune doping of the semiconductor layer (206).
11. A method for fabricating a single photon emitter (SPE), the method comprising:
forming (702) a substrate layer (202);
20 depositing (704) a metal film (204) deposited on the substrate layer (202);
fabricating (706) an array of nanopillars (210) fabricated on the metal film (204),
in such a manner that each nanopillar of the array of nanopillars (210) has a predefined aspect
ratio and is spaced apart from another nanopillar by a predefined distance; and
depositing (708) a semiconductor layer (206) deposited on the array of nanopillars
25 (210);
wherein each nanopillar of the array of nanopillars (210) is fabricated of a material
that prevents disruption to structure of a first part of the semiconductor layer (206) and a
nanopillar on excitation introduces a strain on the first part of the semiconductor layer (206)
thereby allowing funnelling of a plurality of excitons from the first part of the semiconductor
30 layer (206) towards the excited nanopillar,
wherein an exciton from the plurality of excitons moves to a defect state created
on the first part of the semiconductor layer (206) and the exciton when released from the
defect state, emits a single photon, and
wherein the metal film (204) is configured to absorb one or more excitons from a
35 second part of the semiconductor layer (206), such that no photons are emitted from the
second part of the semiconductor layer (206) to ensure emission of the stream of single
photons from the first part of the semiconductor layer (206).
12. The method as claimed in claim 11, further comprising:
40 depositing (710) one or more layers (208) of a dielectric material deposited on the
semiconductor layer (206) for reducing loss of excitons from the semiconductor layer (206).
13. The method as claimed in claim 11, wherein the semiconductor layer (206) is fabricated of
a semiconductor having a direct bandgap.
21
14. The method as claimed in claim 11, further comprising:
fabricating the metal film (204) from a metal having reflectance that covers an
emission wavelength range of the single photon emitter.
5
15. The method as claimed in claim 11, wherein the material for fabrication of each nanopillar
comprises a polymer-based photoresist.
16. The method as claimed in claim 11, further comprising:
10 defining the predefined distance between each nanopillar in such a manner that
such that the first part of the semiconductor layer (206) is in contact with a nanopillar, and
the second part of the semiconductor layer (206) is in contact with the metal film.
17. The method as claimed in claim 11, further comprising:
15 defining the predefined distance between each nanopillar based on spot size of an
excitation source such that at a given time, a single nanopillar is excited by the excitation
source.
18. The method as claimed in claim 11, wherein the predefined aspect ratio of each nanopillar
20 is at least 3:1.
19. The method as claimed in claim 11, wherein the second part of the semiconductor layer
(206) contacts the metal film at a predetermined distance from a center point of each
nanopillar.
25
20. The method as claimed in claim 11, further comprising:
depositing a transparent gate electrode on the one or more layers (208) of a
dielectric material, wherein the transparent gate electrode enables application of a gate
voltage, for electrostatically tuning doping of the semiconductor layer (206).

Documents

Application Documents

# Name Date
1 202441067119-STATEMENT OF UNDERTAKING (FORM 3) [05-09-2024(online)].pdf 2024-09-05
2 202441067119-REQUEST FOR EARLY PUBLICATION(FORM-9) [05-09-2024(online)].pdf 2024-09-05
3 202441067119-FORM-9 [05-09-2024(online)].pdf 2024-09-05
4 202441067119-FORM-8 [05-09-2024(online)].pdf 2024-09-05
5 202441067119-FORM-26 [05-09-2024(online)].pdf 2024-09-05
6 202441067119-FORM FOR SMALL ENTITY(FORM-28) [05-09-2024(online)].pdf 2024-09-05
7 202441067119-FORM 18A [05-09-2024(online)].pdf 2024-09-05
8 202441067119-FORM 1 [05-09-2024(online)].pdf 2024-09-05
9 202441067119-EVIDENCE OF ELIGIBILTY RULE 24C1h [05-09-2024(online)].pdf 2024-09-05
10 202441067119-EVIDENCE FOR REGISTRATION UNDER SSI(FORM-28) [05-09-2024(online)].pdf 2024-09-05
11 202441067119-EVIDENCE FOR REGISTRATION UNDER SSI [05-09-2024(online)].pdf 2024-09-05
12 202441067119-EDUCATIONAL INSTITUTION(S) [05-09-2024(online)].pdf 2024-09-05
13 202441067119-DRAWINGS [05-09-2024(online)].pdf 2024-09-05
14 202441067119-DECLARATION OF INVENTORSHIP (FORM 5) [05-09-2024(online)].pdf 2024-09-05
15 202441067119-COMPLETE SPECIFICATION [05-09-2024(online)].pdf 2024-09-05
16 202441067119-FER.pdf 2024-11-07
17 202441067119-Proof of Right [31-12-2024(online)].pdf 2024-12-31
18 202441067119-OTHERS [15-04-2025(online)].pdf 2025-04-15
19 202441067119-FER_SER_REPLY [15-04-2025(online)].pdf 2025-04-15
20 202441067119-COMPLETE SPECIFICATION [15-04-2025(online)].pdf 2025-04-15
21 202441067119-CLAIMS [15-04-2025(online)].pdf 2025-04-15
22 202441067119-PatentCertificate07-07-2025.pdf 2025-07-07
23 202441067119-IntimationOfGrant07-07-2025.pdf 2025-07-07

Search Strategy

1 202441067119E_01-11-2024.pdf

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