A SYSTEM AND METHOD FOR A FAST CLOCK RECOVERY IN DIGITAL VIDEO COMMUNICATION
Field of invention
This invention relates to a field of digital video communication, and more specifically to a system and method for overcoming clock recovery problems in the presence of program clock reference (PCR) packet jitters in a digital video communication using a fast and efficient clock recovery algorithm with a minimal computational overheads and a low response time (less than 4 seconds).
Background of the invention
In conventional digital video communication systems data is made available to a customer's home television set at a request or demand by the customer. Customers select a channel and enter a code into a box (widely known as set top box) at home, and a program gets delivered or displayed. Each set top box (STB) must receive data and then process it to produce a continuous high-quality audio/video program. Such universal video-on-demand requires massive amounts of audio/video data multiplexing, which is done as per the Moving Picture Experts Group (MPEG 2) system standard (13818-1).
The MPEG 2 system standard is a well-known international standard for compression and transmission of video and audio data streams. The MPEG-2 standard was developed by the International Standards Organization (ISO) Moving Picture Experts Group (MPEG) and is documented in ISO/IEC DIS 13818-1, "Information Technology-Generic Coding of Moving Pictures and Associated Audio Information: Systems," ISO/IEC DIS 13818-2, "Information Technology-Generic Coding of Moving Pictures and Associated Audio Information Video" and ISO/IEC Committee Draft 13818-3, "Information Technology' Generic Coding of Moving Pictures and Associated Audio Information: Audio." The MPEG-2 systems specification provides a multi-layer hierarchical organization for multiplexing and transmission of video, audio and other types of program data streams, and is described in greater detail in A. Wasilewski, "MPEG-2 Systems Specification: Blueprint for Network Interoperability," Communications Technology, February 1994.
The MPEG-2 video and audio specifications provide compression and encoding of video and audio data streams. MPEG-2 video compression is described in greater detail in D. LeGall, "MPEG: A Video Compression Standard for Multimedia Applications," Communications of the ACM, Vol. 34, No. 4, pp. 46-58, April 1991.
In a digital video broadcast (DVB) communication system, audio/video data is transmitted through a transport stream. The transport stream consists of packets having a fixed length of 188 bytes, and such construction is adapted on an assumption that transmission is performed over an ATM system or through a digital broadcast system. A payload or adaptation field is allocated to a portion other than a packet header of the transport stream packet. The adaptation field has a function for transmitting information, such as PCR and the like with some stuffing function.
A decoding time stamp (DTS) and a presentation time stamp (PTS) specify a time instance, at which a packet should be decoded and presented, respectively. The DTS and PTS are all referenced to an encoder's system time clock (also known as STC) running at 27 MHz. Samples of a STC clock, known as PCR values, are transmitted through a transport stream packet at regular time intervals to a decoder and a reference time is reconstructed by means of these clock samples and a standard phase locked loop (PLL) system.
There are various pertbrmance measures, such as accuracy, response time, performance budget, etc for measuring efficiency of a clock recovery algorithm. Some of these are described below:
The task of any clock recovery algorithm is to estimate and compensate for a drift occurring between a transmitter clock frequency and a receiver clock frequency. Unfortunately, the presence of transmission jitter (Jt) affects the performance of the estimation/compensation process. This makes the transmitter clock to appear faster or slower than it actually is and causes the propagation of some residual jitter (Jr) up to the receiver clock signal. To overcome above problem, several consecutive clock samples
must be observed and processed. The larger the numbers of the clock samples are, the more accurate the estimation of the drift to be removed is, and thus the clock signal is more accurately synchronized. However, the point of contention is waiting for a larger number of clock samples means that the observation period is longer and so is the response time of the algorithm. Some performance measures have been defined to quantify and compare the various clock recovery algorithms
The accuracy (d) of a clock synchronization algorithm is the ratio between the power of the transmission jitter J, and the power of the tolerable value of residual jitter Jr:
(Equation Removed)
The time taken by the clock synchronization algorithm to compensate the initial drift D, based on the observed clock samples, corresponds to the transient phase. Its duration is the response time, and is defined as follows:
The response time (t0) of a clock synchronization algorithm is the time required for the error of the synchronized clock signal to decrease and stay within a predetermined threshold, in the idealized condition that no jitter is present at the input. The threshold is fixed at the 5% of the tolerable jitter, Jr. During to the algorithm is said to be in the transient phase, when to has expired it is said to be in the steady state.
Performance budget (Φ) of a clock synchronization algorithm is the ratio between the steady state accuracy do and the response time to.
An ideal synchronization algorithm should have an infinite performance budget.
FIGURE 1 shows a block diagram of a conventional clock recovery system. An MPEG-2 transport stream is fed to a DVB-T modulator via a transport stream packet injector. The modulator outputs a Coded Orthogonal Frequency Division Multiplexing (COFDM) signal, which is demodulated and detected by a front-end tuner of a set top box (STB).
The output of the front-end tuner is a 188-byte transport stream packet, which contains both audio and video data. The set top box (STB) back-end, which contains a CPU, decodes the transport stream for rendering decoded audio/video data at a television (TV) set. For audio/video time synchronization, a 27 MHz voltage controlled crystal oscillator (VCXO) is used in the set top box (STB) back-end. In practical scenario (DVB communication), a transport stream is received by an antenna and the antenna output is rendered to a set top box (STB) front-end.
A correct clock recovery at a set top box (STB) receiver side is very essential for audio/video synchronization. However, there are several factors, which lead to degradations in a clock recovery process. Some of these factors are:
1. A difference between the transmitter system clock frequency and the receiver
STC frequency (generally a VCXO),
2. An introduction of a significant amount of jitter by a communication channel,
3. A delay introduced by an inner interleaving and de-interleaving blocks in the
transmitter and receiver side (particularly in DVB-T transmission), and
4. In worse channel conditions (such as % guard interval, channel fading, low
camer-to-noise ratio etc.) arrival of PCR packets gets delayed, as the set top box
(STB) tuner front-end takes much time to detect and demodulate the signal.
FIGURE 2 shows an existing system for a clock recovery as disclosed by a publication titled a new method of clock recovery in MPEG decoders' by Hooman Hassanzadegan and Nima Sarshar, Iran. It shows an addition of a random value to a PCR value generated in a PCR generation block to indicate a jitter. The simulation results show that the time spacing between every two consecutive PCRs is 0.1 second, which is the minimum PCR rate mentioned in the MPEG specifications.
The drawback in the above mentioned system is that the computations involved for the clock recovery requires a complex and a high cost apparatus.
FIGURE 3 shows a block diagram of a clock recovery algorithm as proposed in the Indian patent number 2052/Del/2004 titled "Low complexity & low cost solution to clock recovery problem in the presence of large clock jitter in DVB-terrestrial". A PCR call back function determines a time interval between successive input PCR signals. In a PCR call back function block an average PCR difference is calculated on an arrival of PCR packets and this difference is stored in a global database. The PCR call back function and a clock recovery task are running concurrently, which are executed concurrently in a real time operating system. The PCR call back function invokes the clock recovery task on arrival of a first PCR packet. In a clock recovery task block, a voltage controlled oscillator (VCXO) at a receiver is corrected at regular time intervals rather than waiting for a PCR event to occur on arrival of PCR packets. This time interval duration is calculated as an average PCR inter arrival time to set a timer after reading a system time clock (STC) value from the voltage controlled oscillator VCXO. A system time clock (STC) value is read again on expiry of the timer interval and, then a frequency error is calculated from the differences of STC values.
The frequency error is calculated using the following equations:
Dii.Teren-,--e - S'lVourrent-PCRcurrent)
PCRT.ickD.if - (PCRcurrcnt-PCRprovious)
TickError = ( STC current-PCRcurrent) - (STCprevious-PCRprevicus )
TimeError = 27/000000/PCRTickDiff
FreqError - TickError * TimeError
FreqError = (Tick-Error * 27000000) / PCRTickDiff.
From the frequency error, a correction value is calculated. The voltage controlled oscillator (VCXO) is then set by the correction value.
The frequency error remains unstable due to an uncertain arrival of the PCR packets at a receiver end and, thus the synchronization for the receiver system clock is lost.
A proposed method described below is used to overcome synchronization problems. An average PCR difference is calculated using a simple infinite impulse response (1IR) filter having a low computational complexity. A large time constant i.e. |i|=1.0 is used to maintain a stable value of the computed average.
A large time constant helps in maintaining a stable value of the computed average, but takes a large number of samples and hence a large time to stabilize to an average value as is evident from the plot shown in FIGURE 4. A large settling time will result in switching overhead, when switching from one channel to another.
Transfer function of the filter is,
(Equation Removed)
As the time constant coefficient is 1-1/128, the filter is implemented with simple shift and addition operations. An output of the filter is multiplied by a coefficient 1/128 to compensate for a gain factor of the filter, which is implemented as a left shift operation. Table

(Table Removed)
The table provided above shows that 31 arithmetic operations are executed in every average PCR difference interval. It is observed that an average PCR difference is approximately 35 milliseconds. Therefore, the average computational overhead for the proposed clock recovery algorithm/ method in terms of arithmetic operations executed per second is: 31/35 *1000 - 886 arithmetic operations per second.
Drawbacks of the algorithm:
1. The algorithm utilizes a large response time, which is evident as the average PCR
diff filter needs to accumulate around 1500 PCR samples for a stable output.
Since the average time interval between two PCR's (neglecting the transmission
jitter) is around 35 ms, which equals to a response time of around 52.5 seconds.
2. The use of a normalization and non-linear saturation block as the parameters of
this block depend on channel conditions and have to be reset, if there is an
increase in channel jitter.
In a digital video communication, uncertain or untimely arrival of PCR packets at a receiver side causes problems in the synchronization of a receiver system clock with that of a transmitter clock The existing system and methods available to overcome these aspects cannot reduce such problems accurately and efficiently, specifically in worse channel conditions. Therefore errors like color loss, jittery video, audio dropouts still persist. Moreover, the existing systems and methods have high computational overhead and/or are very slow to respond.
Thus, there is need of a clock recovery mechanism that utilizes a fast clock recovery algorithm having a minimal computational overhead and a low response time to overcome clock recovery problems in the presence of PCR packet jitters in a digital video communication
Summary of the invention
It is an object of the present invention to provide a system and method for a fast clock recovery in a digital video communication using an algorithm having a low response time (less than 4 seconds).
It is another object of the present invention to provide a system and method for a fast clock recovery in a digital video communication using an algorithm having minimal computational overheads.
It is yet another object of the present invention to provide a low complexity and a low-cost solution to clock recovery problems in the presence of large clock jitters in a digital video communication.
To achieve said objectives, the present invention provides a system utilizing a clock recovery algorithm that serves as a low complexity and a low-cost solution to clock recovery problems in the presence of large clock jitters in a digital video communication, the system comprising:
a delay measurement block for generating Program Clock Reference (PCR) input signals and for continuously determining time intervals between successive PCR input signals,
a first storage device connected to an output of the delay measurement block for generating a first PCR signal corresponding to the time intervals between arrival of the successive PCR input signals,
a PCR inter-arrival time computation filtering device having a first input connected to an output of the first storage device and a second input connected to the output of the
delay measurement block for receiving the PCR signals to determine an average time of arrival difference between successive PCR packets,
an error correction device connected to an output of the PCR inter-arrival time computation filtering device for minimizing errors in the average time of arrival difference between the successive PCR packets,
a controlled system clock generator connected to an output of the error correction device to generate a system clock,
a second storage device connected at an output of the controlled system clock generator for generating a first system clock output, and
a controlled clock period difference computation element having a first input connected to an output of the second storage element and a second input receiving a second system clock output from the controlled system clock generator for computing a clock period difference between the first system clock output and the second system clock output, the controlled clock period difference computation element having an output connected to the error correction device to form a feedback circuit for minimizing errors between the system clock output and the average time of arrival difference between successive PCR packets
, wherein the PCR inter-arrival time computation filtering device comprises a plurality of filters with different time constants to provide a stable average time value in a low response time.
Further, the present invention provides a method utilizing a clock recovery algorithm that serves as a low complexity and a low-cost solution to clock recovery problems in presence of large clock jitters in a digital video communication, said method comprising the steps of: and determining a time interval between successive input PCR signals, computing an average time difference between successive PCR packets, computing an average difference between successive system clock signals, minimizing an error between successive PCR packets and system clock signals,
generating successive system clock signals

, wherein computing the average time difference between successive PCR packets is done through a plurality of filters with different time constants to provide a stable average time difference value in a low response time.
In a digital video broadcast (DVB) operation, irregularity in an arrival of PCR packets at a receiver end causes serious problems in synchronization of a receiver system clock with that of a transmitter clock. To overcome these problems, a low complexity, a low-cost clock recovery algorithm (with very minimal response time, that is, less than 4 seconds) is proposed that corrects the voltage-controlled oscillator (VCXO) at the receiver end by predicting an average PCR difference value at a regular time interval instead of waiting for the delayed packets to arrive. The proposed algorithm recovers the lost synchronization of a transmitter and a receiver even in worse channel conditions (such as ¼ guard interval, channel fading, low carrier-to-noise ratio etc.). In addition, the present algorithm utilizes very little computational overheads.
Brief Description of the drawings
The present invention is described with the help of accompanying drawings.
FIGURE 1 illustrates a block diagram of a conventional clock recovery system.
FIGURE 2 illustrates a block diagram for a clock recovery system in MPEG decoders.
FIGURE 3 shows a block diagram of a clock recovery algorithm as proposed in the Indian Patent 2052/Del/2004.
FIGURE 4 shows a graph for a PCR average difference plotted as a function of PCR sample numbers for an algorithm proposed in the Indian Patent 2052/Del/2004.
FIGURE 5 shows a system block diagram for a clock recovery in a digital video communication in accordance with the present invention.
FIGURE 6 shows a block diagram of an improved clock recovery algorithm in accordance with the present invention.
FIGURE 7 shows various responses of infinite impulse response (1IR) filters with varying time constants in accordance with the present invention.
FIGURE 8 shows a graph for a PCR average difference plotted as a function of PCR sample numbers for an algorithm proposed in the present invention.
FIGURE 9 shows a graph depicting a frequency error as a function of PCR sample numbers in accordance with the present invention.
Detailed Description of the Invention
The present invention provides a system and method for overcoming clock recovery problems in the presence of program clock reference (PCR) packet jitters in a digital video communication using a fast and efficient clock recovery algorithm having low computational overheads and a minimal response time (less than 4 seconds). Hence, the new invention improves the performance of the clock recovery algorithm over previous inventions by reducing computational overheads as well as the response time.
FlGURE 5 shows a block diagram of a clock recovery system 500 in accordance with the present invention. The clock recovery system 500 includes a PCR delay measurement block 502, a first storage element 504, a PCR average difference filter block 506, a frequency correction generation block 508, a system clock generator 510, a second storage element 512, and a SCF difference computation device 514. The PCR delay measurement block 502 generates input PCR signals for the clock recovery system 500. The PCR delay measurement block 502, also measures delays between successive PCR packets. The PCR delay block 502 consists of a logic-parsing device for providing a selective PCR packet output. The logic-parsing device can be a de-multiplexing logic device for a priority based injection of PCR packets into a system.
Further, the first data storage element 504 receives PCR data streams from the PCR delay measurement block 502. The first storage element 504 includes a buffers or registers for introducing a temporal delay in the PCR data streams. The PCR average difference filter 506 receives input PCR signal streams to compute an average inter-arrival time between successive PCR packets. The gain factor of the PCR average difference filter 506 is then compensated by coupling the filter 506 output to a coefficient multiplier.
The gain compensated output of the PCR average difference filter 506 is then rendered to the frequency correction generation block 508 for applying minimization to an error induced in a PCR inter-arrival time.
The system clock generator 510 generates system clock outputs. A system clock generator can be a phase locked loop device that generates a system time clock. The system time clock is a generic system clock of a set top box (STB) in a digital video communication system. Two system clock outputs are generated, wherein a delay between the two system clock outputs is established by introducing the second storage element 512 at one of the two system clock outputs of the system clock generator 510. The SCF difference computation device 514 is connected to an output of the system clock generator 510 for computing a difference between the two system clock outputs. The
difference between the two system clock outputs is further converted to a differential frequency error minimization device for converting this difference to a frequency error and applying a correction to the same. The SCF difference computation device 514 is a voltage to frequency conversion device.
A clock recovery algorithm is already described in FIGURE 3 as proposed in the Indian patent number 2052/Del/2004 titled "Low complexity & low cost solution to clock recovery problem in the presence of large clock jitter in DVB-terrestrial".
FIGURE 6 shows a block diagram of an improved clock recovery algorithm in accordance with the present invention. The response time for this algorithm has been reduced to less than 4 seconds. An average PCR difference filter block is replaced by a bank of filters with varying time constants in order to improve the response time of the system.
The fast responding filters (having lower time constants) give an output with larger standard deviation as compared to slower filters. As a time constant of a filter increases, its response time increases, but the output of the filter gets more stable.
FIGURE 7 shows responses of various filters as a function of collected PCR sample numbers. The idea is to initially tap the output from a fast responding filter and get the recovered clock at the receiver synchronized with the transmitter clock as soon as possible. Then slowly as more number of PCR packets has been collected and an improved estimate of the PCR difference can be obtained, the system switches to a filter with a higher time constant.
The main advantage of using the bank of filters is that initially, the filters with small time constants is brought into the loop, so that the system settles faster, but due to large variations in the output of the filters the accuracy will not be very good. Slowly as the time progresses and more PCR samples are collected, the filters with large time constants
are switched in to improve the accuracy of the clock recovery algorithm. Values of the PCR difference signal as a function of PCR sample numbers is shown in FIGURE 8. As a result of these modifications the algorithm gives a steady value of the frequency error as shown in FIGURE 9
Computational overhead:
Each filter in the filter bank requires one addition, one multiplication, one division and two shift operations in every average PCR difference interval. Since, in the present clock recovery algorithm five filters have been used, so there is an overhead of four additions, four multiplications, four divisions and eight shift operations. But this overhead is only in the initial state till the system stabilizes. Once the system stabilizes only the filter with the largest time constant is operational, so this overhead is there only for the first 1500 PCR samples.
The proposed clock recovery algorithm has various advantages. These advantages are described below;
The improved clock recovery algorithm caters to all channel conditions described in digital video broadcast-terrestrial (DVB-T) standards (EN 300 744) in term of PCR packet arrival and in maintaining receiver system synchronization in the given conditions. The EN 300 744 standards describe digital broadcasting systems for television, sound and data services; framing structure, channel coding and modulation for digital terrestrial television
The improved clock recovery algorithm works on a low cost hardware and causes negligible computational overheads on a system CPU.
The improved clock recovery algorithm is compatible with a digital video broadcast-satellite (DVB-S) communication receiver, a digital video broadcast-terrestrial (DVB-T) communication receiver, and a digital video broadcasting-cable (DVB-C) communication receiver

We claim:
1. A system utilizing a clock recovery algorithm that serves as a low complexity and low-cost solution to clock recovery problems in a presence of large clock jitters in a digital video communication, said system comprising:
a delay measurement block for generating Program Clock Reference (PCR) input signals and for continuously determining time intervals between successive PCR input signals;
a first storage device connected to an output of said delay measurement block for generating a first PCR signal corresponding to said time intervals between arrival of said successive PCR input signals;
a PCR inter-arrival time computation filtering device having a first input connected to an output of said first storage device and a second input connected to the output of said delay measurement block for receiving said PCR signals to determine an average time of arrival difference between successive PCR packets;
an error correction device connected to an output of said PCR inter-arrival time computation filtering device for minimizing errors in the average time of arrival difference between the successive PCR packets;
a controlled system clock generator connected to an output of said error correction device to generate a system clock;
a second storage device connected at an output of said controlled system clock generator for generating a first system clock output; and
a controlled clock period difference computation element having a first input connected to an output of said second storage element and a second input
receiving a second system clock output from said controlled system clock generator for computing a clock period difference between the first system clock output and the second system clock output, said controlled clock period difference computation element having an output connected to said error correction device to form a feedback circuit for minimizing errors between said system clock output and said average time of arrival difference between successive PCR packets
, wherein said PCR inter-arrival time computation filtering device comprises a plurality of filters with different time constants to provide a stable average time value in a low response time.
2. The system as claimed in claim 1, wherein said delay measurement block
comprises a signal parsing device for providing a selective PCR packet output.
3. The system as claimed in claim 2, wherein said signal parsing device comprises a
de-multiplexing logic device for a priority based injection of PCR packets.
4. The system as claimed in claim 1, wherein the plurality of filters are Infinite
Impulse Response (1IR) filters.
5. The system as claimed in claim 4, wherein said Infinite Impulse Response (IIR)
filters utilizes a low cost hardware.
6. The system as claimed in claim 1, wherein said controlled system clock generator
comprises a Phase Locked Loop device.
7. The system as claimed in claim 1, wherein said controlled system clock generator
is a voltage controlled crystal oscillator (VCXO) device.
8. The system as claimed in claim 1, wherein said first and second storage device
comprises at least one register for introducing a temporal delay.
9. The system as claimed in claim 1, wherein said controlled clock period difference
computation element is a voltage to frequency conversion device.
10. The system as claimed in claim 1, wherein said clock recovery algorithm satisfies
channel conditions described in DVB-T standard (EN 300 744) in terms of PCR
packet arrival and maintains receiver system synchronization in said channel
conditions.
11. The system as claimed in claim 1, wherein said clock recovery algorithm utilizes
low computational overheads on a system CPU.
12. The system as claimed in claim 1, wherein said clock recovery algorithm is
compatible with a digital video broadcast-satellite (DVB-S) communication
receiver.
13. The system as claimed in claim 1, wherein said clock recovery algorithm is
compatible with a digital video broadcast-cable (DVB-C) communication
receiver,
14. The system as claimed in claim 1, wherein said clock recovery algorithm is
compatible with a digital video broadcast-Terrestrial (DVB-T) communication
receiver.

15. The system as claimed in claim 1, wherein said clock recovery algorithm utilizes
a minimal response time.
16. A method utilizing a clock recovery algorithm that serves as a low complexity
and low-cost solution to clock recovery problems in presence of large clock jitters
in a digital video communication, said method comprising the steps of:
determining a time interval between successive input PCR signals; computing an average time difference between successive PCR packets; computing an average difference between successive system clock signals;
minimizing an error between successive PCR packets and system clock signals; and
generating successive system clock signals
, wherein computing the average time difference between successive PCR packets is done through a plurality of filters with different time constants to provide a stable time difference value in a low response time.
17. The method as claimed in claim 16, wherein said determining comprises
calculating a delay between successive system clock signals.
18. The method as claimed in claim 17, wherein said calculating comprises parsing an
input PCR signal stream.
19. The method as claimed in claim 18, wherein said parsing comprises de
multiplexing the input PCR signal stream for generating PCR packets.
20. The method as claimed in claim 16, wherein said computing the average time
difference between successive PCR- packets comprises applying filtering on PCR
packets to compute an average inter-arrival time of PCR packets.
21. The method as claimed in claim 20, wherein said filtering comprises correcting a
frequency of system clock signals at regular time intervals.
22. The rrjethod as claimed in claim 21, wherein said correcting comprises confirming
said regular time intervals to an average PCR inter-arrival time.
23. The method as claimed in claim 22, wherein said confirming comprises
determining a system clock value at a commencement and a termination of said
inter-arrival time.
24. The method as claimed in claim 16, wherein said generating the successive
system clock signals comprises generating at least two delayed system clock
outputs.
25. The method as claimed in claim 16, wherein said computing the average
difference between successive system clock signals comprises converting the
average difference between successive system clock signals to a frequency error.
26. A computer program product utilizing a clock recovery algorithm that serves as a
low complexity and low-cost solution to clock recovery problem in presence of
large clock jitter in a digital video communication, the computer program product
comprising a computer readable medium configured with processor executable
instructions, the computer program product comprising:
determining a time interval between successive input PCR signals; computing an average time difference between successive PCR packets; computing an average difference between successive system clock signals;
minimizing an error between successive PCR packets and system clock signals; and
generating successive system clock signals
wherein said computing the average time difference between successive PCR packets is done through a plurality of filters with different time constants to provide a stable time difference value in a low response time.
27. The computer program product of claim 26, wherein the computer readable
medium comprises a storage medium is one of a floppy diskette, hard disk, CD
ROM, or magnetic tape.
28. A system utilizing a clock recovery algorithm that serves as a low complexity and
low-cost solution to clock recovery problems in a presence of large clock jitters in
a digital video communication substantially as herein described with reference to
and as illustrated in the accompanying drawings.
29. A method utilizing a clock recovery algorithm that serves as a low complexity
and low-cost .solution to clock recovery problems in presence of large clock jitters
in a digital video communication substantially as herein described with reference
to and as illustrated in the accompanying drawings.
30. A computer program product utilizing a clock recovery algorithm that serves as a
low complexity and low-cost solution to clock recovery problem in presence of
large clock jitter in a digital video communication substantially as herein
described with reference to and as illustrated in the accompanying drawings.