REDUCED LEAKAGE MEMORY WITH NOISE MARGIN CONTROL ACROSS PROCESS CORNERS
Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a memory array for reducing leakages with a noise margin control during skewed process corners.
Background of the Invention
Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. As the size of integrated chips (ICs) is increasing, power dissipation .is also increasing. In deep submicron technologies, when we target very high capacity memory device, static power dissipation itself become comparable or more than the dynamic power. Methods to reduce leakage in a standby mode are applied to solve the problem. As the supply voltage decreases, data stability becomes a matter of concern, and particularly across process corners. So, various methods are targeted to resolve the noise margin problem across the process corners.
Noise margin problem arises particularly in a process corner, where NMOS is slow and PMOS is fast. Virtual ground level rises to a higher value than required/acceptable value and the cell stability is affected. A power gating technique is specifically applied to put the memory arrays in a standby mode for reducing leakage currents. Data protection transistors are added to a memory cell to prevent data destruction caused by noise margin degradation. The data protection transistors provide sufficient sink current to maintain data leakage during skewed process corners.
FIGURE 1 explains a conventional technique for reducing leakage currents in a memory cell. The present invention provides arranging, in series with a memory cell, complementary MOS switches M31 and M33. Diodes M32 and M34 are used to limit
th|*rt>ltage across memory cells to approximately (VDD-Vtn-Vtp) in a standby mode, where Vtn is the threshold voltage of an NMOS transistor M33 and Vtp is the threshold voltage of a PMOS transistor M31. The PMOS transistor M31 and the NMOS transistor M33 are used to provide a normal supply in an active mode. The wordline / enable line (WL/EL) are used to control Gates of transistors M31 and M33 separately. A turn-off control signal is applied to the at least one MOS transistor to enter in a stand-by mode. The overall resistance of the column and of the at least one transistor increases in standby mode. The conventional technique provides leakage reductions mainly in a standby mode.
Therefore, there is a need of a novel technique for reducing leakages in a memory array with a noise margin control during skewed process corners. The novel technique provides suitable sink currents during skewed (SF/FS) corners to prevent data leakage.
Summary of the Invention
It is an object of the present invention to provide a memory array for reducing leakages with a noise margin control during skewed process corners.
It is another object of the present invention to provide a memory array utilizing simple and cost effective diode transistors implementation for maintaining the sink currents during various process corners.
To achieve the aforementioned objectives, the present invention provides a memory array for providing leakage reductions with a noise margin control over process corners, said memory array comprising:
an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage;
|r a transistor circuit connected in series with each column for providing a sufficient voltage to maintain stored information in the memory array; and
a signal module for applying a turn-off control signal to the transistor circuit to enter in a standby mode
, wherein an additional transistor circuit connected in parallel to said transistor circuit, said additional transistor circuit comprises one or more diode transistors having their bulk controlled separately by one of a p-bulk signal and an n-bulk signal for controlling sink currents during said process corners.
Further the present invention provides a method of leakage reduction for a memory array through an additional transistor circuit, the additional transistor circuit providing a voltage control for maintaining noise margin over process corners, said method comprising the steps of:
providing a sufficient voltage in the standby mode to maintain stored information in the memory array through a transistor circuit;
applying a turn-off control signal to said transistor circuit through a signal module to enter in the standby mode; and
controlling sink currents through an additional transistor circuit
, wherein controlling the sink currents during said process corners through the additional transistor circuit, said additional transistor circuit comprises one or more diode transistors having their bulk controlled separately by one of a p-bulk signal and an n-bulk signal.
Brief Description of the Drawings
FIGURE 1 illustrates a conventional schematic diagram for reducing leakage currents for a memory device;
FIGURE 2 is a schematic diagram according to the present invention;
FIGURE 3 is a schematic diagram according to a first embodiment of the present invention;
FIGURE 4 is a schematic diagram according to a second embodiment of the present invention;
FIGURE 5 is a schematic diagram according to a third embodiment of the present invention;
FIGURE 6 is a schematic diagram according to a fourth embodiment of the present invention; and
FIGURE 7 illustrates a flow diagram of a method for leakage reductions with a noise margin for a memory array during skewed process corners, in accordance to the present invention.
Detailed Description of the Invention
The present invention provides a memory array for providing leakage reductions with a noise margin control over process corners is provided. The memory array enables to maintain data with reduced voltage across the skewed process corners, which otherwise cause data instability. The memory array includes an array of memory cell lines and columns, a transistor circuit, means for applying a turn-off control signal, and an additional transistor circuit. Each column is supplied between a high supply voltage and a
lov|fsupply voltage. The transistor circuit is connected in series with each column for providing a sufficient voltage to maintain stored information in the memory array. The additional transistor circuit is connected in parallel to the transistor circuit to provide a threshold voltage control in the memory array. The additional transistor circuit includes one or more diode transistors having their bulk controlled separately by either a p-bulk signal or an n-bulk signal for controlling sink currents during the skewed process corners.
The technique presented in the present invention offers many advantages. First, the proposed technique requires minimal circuits, which are very cost effective for reducing leakages and for maintaining sink currents during skewed process corners. Second, the proposed technique provides noise margin control during the skewed process corners so that there is no data loss or data instability occurs.
FIGURE 2 shows a schematic diagram 200 for illustrating a principle of the present invention. The schematic diagram 200 provides leakage reductions in a memory array with a noise margin control over skewed process corners. Problems of noise margin arise, particularly in process corners, where an NMOS transistor is slow and an PMOS transistor is fast. Virtual grounds level rises to a higher level than required/ acceptable value and cell stability is affected. The schematic diagram 200 includes an array of memory cell lines and columns, each of these columns are supplied between a high supply voltage (VDD) and a low supply voltage (GND). The schematic diagram 200 includes a transistor circuit connected in series with each column for providing a sufficient voltage to maintain stored information in a memory cell. The transistor circuit includes complementary MOS switches M31, and M33, and diode transistors, such as M32 and M34. The MOS transistor M31 is a P-channel MOS connected to the high supply voltage VDD, and the MOS transistor M33 is an N-channel MOS transistor connected to the low supply voltage GND. The schematic diagram 200 includes a signal module for applying a turn-off control signal to the transistor circuit to enter in a standby mode. The schematic diagram 200 further includes an additional transistor circuit for controlling sink currents during the process corners to provide the noise margin control. The additional transistor circuit includes one or more diode transistors, such as M35, and
M36 with their bulk controlled separately by an n-bulk signal and a p-bulk signal respectively. The threshold voltages of the transistor M35 and the transistor M36 are adjusted with the help of bulk bias to take care of the sink current in skewed process corners (SF/FS corners). During SF corners the transistor M36 provides additional sink to maintain the acceptable virtual ground level. Similarly the transistor M35 takes care of the virtual supply level.
FIGURE 3 is a schematic diagram according to a first embodiment of the present invention. The schematic diagram illustrating a principle of the present invention, where the Vt (threshold voltages) of the additional transistor M35 and the transistor M36 is controlled by a virtual supply voltage. The virtual supply voltages are a virtual ground voltage (VGND) and a virtual supply voltage (WDD). In case the bulk of N-diode (M35) is controlled by the virtual supply voltage WDD, a Vy of the diode depends on the virtual VDD level. With increased leakage, the WDD level decreases, and Vt also decreases, thus providing additional sink for the WSS level, helping to maintain noise margin.
FIGURE 4 is a schematic diagram according to a second embodiment of the present invention. The schematic diagram illustrating a principle of the present invention, where only one additional transistor M36 is used for providing suitable sink currents. The Vt (threshold voltages) of the additional transistor M36 is controlled by a ground voltage
(GND).
FIGURE 5 is a schematic diagram according to a third embodiment of the present invention. The schematic diagram illustrating a principle of the present invention, where the transistor M35 and the transistor M36 are used as a standard Vt devices. The standard Vt devices are used, if rest of the devices are in a high Vt process. Otherwise, we have to use low-Vt devices to act as a safe guard diode. In a SF corner, when an NMOS transistor is slow, a fast PMOS transistor comes into rescue to provide an additional sink, and hence maintaining the sufficient noise margin during the SF corner.
FIGURE 6 is a schematic diagram according to a fourth embodiment of the present invention. The schematic diagram illustrating a principle of the present invention, where only one additional diode transistor M36 is used for providing suitable sink currents. The additional transistor M36 is a low Vt diode in this embodiment.
The above-mentioned embodiments provide various combinations of the additional transistor circuits to provide additional sinks for maintaining the sufficient noise margins. Usage of the transistor M35 and the transistor M36 can be optionally be taken as only M35 or only M36 or both of these.
In FIGURES 2 to 6 the wordline / enable line (WL/EL) are used to control Gates of transistors M31 and M33 separately.
FIGURE 7 illustrates a flow diagram of a method for leakage reductions in a memory array operating in a standby mode with noise margin control over skewed process corners, in accordance to the present invention. At step 702, a sufficient voltage is provided in a standby mode to maintain stored information in a memory array through a transistor circuit. At step 704, a turn-off control signal is applied to the transistor circuit through a signal module to enter in the standby mode. At step 706, sink currents are controlled through an additional transistor circuit for maintaining noise margins over skewed process corners.
The present invention is likely to have various alterations, modifications, and improvements, which will readily occur to those skilled in the art. In particular, the foregoing description has been made in relation with a memory in which all the cells in a same column are supplied in parallel, but those skilled in the art will easily adapt the present invention to the case where other sets of cells are supplied in parallel.
Moreover, the foregoing description applies to a memory having all its columns simultaneously set to stand-by as well as to a memory in which only chosen columns are
set stand-by. In this latter case, the setting of a memory column to stand-by can be controlled from the address decoder of the memory.
The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.

WE claim:
1. A memory array for providing leakage reductions with a noise margin control
over process corners, said memory array comprising:
an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage;
a transistor circuit connected in series with each column for providing a sufficient voltage to maintain stored information in the memory array; and
a signal module for applying a turn-off control signal to the transistor circuit to enter in a standby mode
, wherein an additional transistor circuit connected in parallel to said transistor circuit, said additional transistor circuit comprises one or more diode transistors having their bulk controlled separately by one of a p-bulk signal and an n-bulk signal for controlling sink currents during said process corners.
2. The memory array as claimed in claim 1, wherein the transistor circuit comprises:
at least one MOS transistor in series with each column, the at least one MOS transistor comprising a first P-channel MOS transistor connected to the high supply voltage, and a second N-channel MOS transistor connected to the low supply voltage;
a first forward biased diode connected in parallel with the first P-channel MOS transistor; and
a second forward-biased diode connected in parallel with the second N-channel MOS transistor.
3. The memory array as claimed in claim 2, wherein the first P-channel MOS
transistor comprises a gate controlled by a word line (WL) and an enable signal
(EN) line.
4. The memory array as claimed in claim 2, wherein the second N-channel MOS
transistor comprises a gate controlled by a word line (WL) and an enable signal
(EN) line.
5. The memory array as claimed in claim 1, wherein the threshold voltage control is
controlled by one of a bulk biasing device and a low-Vt device.
6. The memory array as claimed in claim 1, wherein said process corners are skewed
corners selected from a group comprising SF corners and FS corners.
7. A method of leakage reduction for a memory array in a standby mode through an
additional transistor circuit, the additional transistor circuit providing a voltage
control for maintaining noise margin over process corners, said method
comprising the steps of:
providing a sufficient voltage in the standby mode to maintain stored information in the memory array through a transistor circuit;
applying a turn-off control signal to said transistor circuit through a signal module to enter in the standby mode; and
controlling sink currents through an additional transistor circuit
, wherein controlling the sink currents during said process corners through the additional transistor circuit, said additional transistor circuit comprises one or more diode transistors having their bulk controlled separately by one of a p-bulk signal and an n-bulk signal.
8. The method as claimed in claim 7, wherein said voltage control is achieved
through one of a bulk biasing and a voltage controlled device.
9. A memory array for providing leakage reductions with a noise margin control
over process corners substantially as herein described with reference to and as
illustrated in the accompanying drawings
10. A method of leakage reduction for a memory array substantially as herein
described with reference to and as illustrated in the accompanying drawings