PREAMBLE OF THE DESCRIPTION:

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE METHOD IN WHICH IT IS BEING PERFORMED

A) TECHNICAL FIELD

[0001] The present invention generally relates to the field of packet base transport networks such as Ethernet communication. The present invention particularly relates to a system and method for implementing a communication interface between a data plane and a control plane. The present invention more particularly relates to a system and method for accessing and managing dynamic data plane.

B) BACKGROUND OF THE INVENTION

[0002] Ethernet is a passive, contention-based broadcast technology which is currently becoming popular with packet based transport networks (PTN). The Carrier Grade Ethernet switches are becoming the transport technology choice for network carriers. The Ethernet switches that are employed need to comply with the existing communication standards. Further the need for an additional capacity requires a transfer of a large amount of data between the data plane and the control layer such as configuring data for complex data-structures, port and flow statistics, EthOam events, Learn and Ageing events and the like.

[0003] In hardware assisted Carrier grade Ethernet switches, the rate at which the event messages are generated are thousands of messages per second. The conventional method adequately handles a few interrupts per seconds but the method is not suitable for handling thousands of events per second. Further the increase in the number of ISRs will hog the CPU bandwidth there affecting the routine tasks of a control layer.

[0004] In view of foregoing, there is a need for a method and system to provide a communication interface between the control plane and data plane. Further there is a need for a system and method for accessing and managing a flexible data plane. Still further there is a need for a system and method for communicating different types of messages to a control layer through common interface without any additional burden on CPU. Yet there is a need for a system and method for adding new indirect address space or messages based on new features/enhancements in the Standards.

[0005] The above mentioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification. C) OBJECT OF THE INVENTION

[0006] The primary object of the present invention is to provide a system and method for accessing and managing a flexible and dynamic data plane.

[0007] Another object of the present invention is to provide a system and method for providing a communication between a data plane and a control plane through a mailbox.

[0008] Another object of the present invention is to provide an efficient method for accessing the data structures, port and flow statistics, EthOam events, learn and ageing events and the like, which are used heavily in data plane.

[0009] Yet another object of the present invention is to provide various addressing modes for acquiring event messages posted at the mailbox.

[0010] Yet another object of the present invention is to provide an indirect accessing scheme for acquiring event messages posted at the mailbox.

[0011] Yet another object of the present invention is to provide a system and method for communicating different types of messages to a control layer through common interface without any additional burden on CPU.

[0012] Yet another object of the present invention is to add new indirect address space or messages based on new features/enhancements in the Standards.

[0013] Yet another object of the present invention is to provide an efficient method for control plane to access the data plane for network switches implemented using FPGAs.

[0014] Yet another object of the present invention is to access the data plane through a common interface called as Postbox mechanism based Host Interface where multiple commands are posted.

[0015] Yet another object of the present invention is to provide a system and method for holding messages in HW/FPGA whenever the control layer is engaged in processing high-level tasks like Non-maskable Interrupt (NMI), etc.

[0016] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

D) SUMMARY OF THE INVENTION

[0017] The various embodiments of the present invention provide a system and method for providing a communication between a data plane and a control plane through post-box mechanism based communication interface implemented in FPGA. According to one embodiment of the present invention, the method comprises the steps of providing a common interface between the control plane and data plane for exchanging one or more messages, transmitting one or more messages simultaneously by the control plane to the data plane for accessing data structures, configuring a postbox to receive one or more messages from the control plane simultaneously, dividing an address space into at-least two segments for handling the different types of messages to a lower-layer, adopting a direct addressing mode for addressing the higher priority messages, and adopting an indirect addressing mode for addressing the low priority messages. The higher priority messages comprise control, status and debug registers and are modified independently. The higher priority messages are the one which do not interrupt the normal processing operation of a switch. The low priority messages comprise graceful, arbitrated and slow updates. The indirect addressing mode provides a queue to the control layer for addressing low priority messages. The control layer is allowed to post a plurality of indirect access commands so that a host interface is not blocked because of any single arbitrated update.

[0018] According to an embodiment of the present invention, the indirect addressing mode posts one or more indirect addressing commands for addressing the low priority messages. The method for posting one or more indirect addressing commands comprises the steps of storing a head and tail bucket comprising a bin number and a plurality of commands posted to avoid any overwrites by the host, allowing host to post a maximum number of eight commands at any given time, passing both the data and command bins simultaneously for write operations, and advising the host to write the data bins before writing the command bins, updating a posting to the command bins and the data bins, and wherein the host updates a main-control register with an Indirect Access bit (IND) and the indirect access count equal to number of commands posted by the host, updating a posting in the main-control register, and considering the head of the bucket/bin as 'Indirect access count' in the Main-Control register by the FPGA, generating a response through a Main-Status register by updating the indirect access count once the command is processed, generating an interrupt for the Main-Status register or using polling method by the host to avoid the un-necessary interrupts, posting an indirect command processing, and wherein the tail of the bucket/bin 'Indirect access count' is updated in the Main-Status register; and indicating that no commands are present in the bins on power-up or hard-reset, and 'no command' in the bin is indicated by initializing the Indirect access count to a preset value and wherein the preset value is indicated by "3'bl 11". wri

[0019] According to an embodiment of the present invention, one or more pseudo-codes are provided for handling indirect addressing commands. The pseudo code comprises a write command and a read command.

[0020] According to an embodiment of the present invention, a step of providing the write command comprises the steps of waiting for a pre-determined time interval when total commands posted are equal to eight; copying a data to a data bucket of the indirect access count; generating a command word, and writing a command to the control area of the bucket in the indirect access count, and wherein the writing command comprises at-least three writes for a 16 bit CPU; updating a main control register, and wherein the updating of the main control register comprises updating indirect access count AND ' 1' (IND bit) AND old contents; updating the indirect access count; and updating the total commands posted.

[0021] According to an embodiment of the present invention, a step of providing the read command comprises the steps of waiting for a pre¬determined time interval when the number of the total commands posted is equal to eight; generating a command word, and writing the generated command word in a command area pointed in the indirect access count; and updating a main control register. The step of updating the main control register comprises updating the indirect access count, AND '1' (IND bit) AND old contents; updating the indirect access count; and updating the total commands posted.

[0022] According to an embodiment of the present invention, one or more pseudo codes are provided for addressing the messages when the main-status register comes back with command execution, and wherein the step of writing the pseudo code comprises the steps of reading the data for the entire size using the indirect access count as bucket pointer when the command posted is read; and performing no read/write action when the command posted is write; updating the total commands posted in a counter; updating the tail pointer; and processing the multiple command responses when the indirect access count is greater than the tail pointer.

[0023] According to an embodiment of the present invention, the method further provides a general mailbox mechanism and a protection mailbox mechanism. The general mailbox mechanism is a simplified communication way from a lower-layer (FPGA) to the host for posting the messages. The bulk sized messages are of 16-byte or more and the message types include protection events, learning and ageing updates and port/flow statistics messages, and wherein the bulk sized messages are posted in a common buffer called a mailbox, and wherein all the message types are covered under a single ISR except for the protection event messages.

[0024] According to an embodiment of the present invention, the general mailbox mechanism and the protection mailbox mechanism provides a common interface to post the messages of size 16-bytes or less from FPGA to the control layer. The FPGA updates the total mail-count in the main-status register for their respective message counts whenever, any message is posted in the general mailbox or the protection mailbox. The FPGA further sets the corresponding mailbox bit in the main-status register indicating a new message is posted in a particular mailbox.

[0025] According to an embodiment of the present invention, an interrupt is generated on arrival of new message in a protection mailbox, and an interrupt is generated when a general mailbox has a minimum of sixteen messages.

[0026] According to an embodiment of the present invention, the method for operating the general mailbox mechanism comprises the steps of: applying a back pressure to the statistics module and the learning module when the general mailbox becomes full; slowing down the statistics read operation in a statistics module; putting a new Mac-address learning on hold in case of learning module; operating the ageing module continue to function without posting any ageing mails to the host; and re-generating all the mails/messages which are not reported to the host since the general mailbox is not cleared by the host due to an on-going high priority task.

[0027] According to an embodiment of the present invention, an internal logic buffers the important protection or event messages in a deep buffer when a back-pressure is applied to the FPGA in case of the protection mailbox mechanism. The deep buffer holds up to 512 protection messages.

[0028] According to an embodiment of the present invention, the step of operating the mailbox mechanism further comprises an overflow handling and a warm-reboot handling operations. The control layer misses the sync with the lower layer (FPGA), in-case of an overflow of mailbox or during a warm-reboot period of a switch. The lower-layer interrupts the host indicating that an overflow is detected and a re-play of the messages is required to sync-up with current status in case of mailbox overflow.

[0029] The various embodiments of the present invention provide a system for providing a communication between a data plane and a control plane through a postbox mechanism implemented in FPGA. The system comprises a host interface; a direct access register map module, an indirect access register map module, a general mailbox and a priority or protection mailbox. The direct access register map module of the system further comprises a control register, a status register and a debug register. The indirect access register map module of the system comprises a FGPA internal memory block and an external memory blocks for handling graceful, arbitrated and slow updates. The indirect access register map module further comprises a queue to control layer to address the graceful or arbitrated updates. The general mailbox of the system comprises a hardware learning or aging module and a port and flow statistics module for handling protection events, learning and ageing updates and port/flow statistics messages. The priority or protection mailbox of the system comprises one or more Ethernet Operation and Administration (EthOAM) modules for handling one or more protection messages, and wherein the common mailbox interface addresses the over-loading of the control layer because of too many interrupts to CPU.

[0030] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating the preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.

E) BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0032] FIG. 1 illustrates a block diagram of a system for providing a communication between the data plane and the control plane through mailbox, according to an embodiment of the present invention.

[0033] FIG. 2 illustrates a flowchart explaining the steps involved in a method for providing a communication between the data plane and the control plane through mailbox, according to an embodiment of the present invention.

[0034] FIG. 3 illustrates a format for command bin/bucket, according to an embodiment of the present invention.

[0035] FIG. 4 illustrates a format for data bin/bucket, according to an embodiment of the present invention.

[0036] FIG. 5 illustrates a flowchart explaining the process steps involved in a method for posting one or more indirect addressing commands in-order to address low priority messages, according to an embodiment of the present invention.

[0037] FIG. 6 illustrates a block diagram indicating a back pressure mechanism applied on the general mailbox and the protection mailbox, according to an embodiment of the present invention.

[0038] Although the specific features of the present invention are shown in some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention. F) DETAILED DESCRIPTION OF THE INVENTION

[0039] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that the logical, mechanical and other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.

[0040] The various embodiments of the present invention provide a system and method for providing a communication between a data plane and a control plane through a mailbox implemented in FPGA. The system is typically employed in Carrier grade Ethernet switches. The system is also adaptable to other networking switches and routers which incorporate enormous data structures at lower level.

[0041] FIG. 1 illustrates a block diagram of a system for providing a communication between the data plane and the control plane through mailbox, according to an embodiment of the present invention. The system comprises a host interface 101, a direct access register map module 102, an indirect access register map module 103, a general mailbox 104 and a priority or protection mailbox 105. The system receives a plurality of events, updates and messages from a control plane through the host interface. The address space of FPGA is intelligently divided to handle different types of events and updates provided to a lower layer (data plane). The direct access register map module 102of the system comprises a control register, a status register and a debug register (Collectively represented as 102a). The direct access register map module 102 adopts a direct addressing mode for addressing higher priority messages. The direct addressing mode modifies the registers according to the received high priority messages so that the received messages do not interrupt normal processing operation of the switch. The indirect access register map module 103of the system comprises a plurality of FGPA internal memory blocks 103a and a plurality of external memory blocks 103b for handling graceful, arbitrated and slow updates. The indirect access register map module further comprises a queue to the control layer in-order to address the graceful or arbitrated updates. The graceful or arbitrated updates have low priority as compared to packet processing section requests. The control layer posts multiple indirect access commands so that the host interface is not blocked due to a single arbitrated update. When the packet processing section (data plane) is not accessing any particular data-structure then only control layer is given an access. As the multiple commands are published at the host interface, the writes to host interface are posted and the reads from the host interface are delayed by a pre-defined time interval. The general mailbox 104 further comprises hardware learning or aging module 104a and a port and flow statistics module 104b for handling protection events, learning and ageing updates and port/flow statistics messages. The priority or protection mailbox 105 comprises one or more Ethernet Operation and Administration (EthOAM) modules for handling one or more protection messages 105a.

[0042] FIG. 2 illustrates a flowchart explaining the process steps involved in a method for providing communication between the data plane and the control plane through a mailbox, according to an embodiment of the present invention. The method comprises the steps of providing a common interface between the control plane and data plane for exchanging one or more messages (201). One or more messages are transmitted by the control layer to the data plane for accessing data structures (202).A mailbox is configured to receive one or more messages from the control plane (203). An address space is divided into at-least two segments for handling the different type of messages to a lower-layer (204). A direct addressing mode is adopted for addressing the higher priority messages (205). An indirect addressing mode is adopted for addressing low priority messages (206).

[0043] According to an embodiment of the present invention, atleast up to eight commands are posted to indirect access register map. A block-memory is provided to allocate upto eight bins/buckets for storing the commands and upto eight bins/buckets for storing the data. The length of each command bin is of atleast8-bytes as shown in FIG 3. Whereas the length of each data bin is of 64 bytes. The size of the data bin is further reduced based on a maximum burst size requirement of the connected external memory.

[0044] FIG. 3 illustrates a format for command bin/bucket, according to an embodiment of the present invention. The command bin format comprises a fixed field to store the information corresponding to a write/read byte address. The write/read byte addresses are used during the posting of multiple indirect read/write commands. The command bin format further provides a field for updating a bin/bucket number for the current command being entered. Further a write/read bit is provided in the command bin format for identifying the write/read operation requests for the addresses queued up in command bin.
[0045] FIG. 4 illustrates a format for data bin/bucket, according to an embodiment of the present invention. The format for data bin/bucket is designed to hold atleast 64 mails, where each mail is of 16 bytes.

[0046] FIG. 5 illustrates a flowchart explaining the process steps involved in a method for posting one or more indirect addressing commands in-order to address the low priority messages, according to an embodiment of the present invention. The method comprises the following steps: A head and tail bucket/bin number and number of commands posted on host is stored, in-order to avoid any overwrites (501). Further the host is allowed to post a maximum of eight commands at any given time (502). Both the data and command bins are simultaneously passed for write operations (503). The host is advised to write commands to the data bins before accessing the command bins. Further the host updates the commands written to the command and data bins (504). Accordingly the host updates a main-control register with an Indirect Access bit (IND) and the indirect access count is changed to the number of commands posted by the host (505). For updating the main-control register, the head of bucket/bin is considered as the 'Indirect access count' by the FPGA. Once the command is processed, a response is generated through a Main-Status register by updating the indirect access count (506). Further an interrupt is generated for the Main-Status register. The polling method is used by the host to avoid un-necessary interrupts. An indirect command processing is posted and the tail of the bucket/bin 'Indirect access count' is updated in the Main-Status register (507). On power-up or hard-reset, both 'Indirect access count' are initialized to "3'bl 11", indicating that no commands are present in the bins.

[0047] According to an embodiment of the present invention, the FPGA implementation comprises one or more hardware description language codes for handling the indirect addressing commands. The code for handling the indirect addressing commands comprises a write command code and a read command code. The algorithm for write command code comprises the following steps of:

[0048] Step 1: Wait for a pre-determined time interval when total commands posted equal to eight.

[0049] Step 2: Copy the data from commands to a data bucket of the indirect access count.

[0050] Step 3: Generate a command word. Write the command word to the control area of the bucket/bin in the indirect access count. The command write instruction requires at-least three writes for a 16 bit CPU.

[0051] Step 4: Update the main control register, where main control register = indirect access count and ' 1' (IND bit) and old contents.

[0052] Step 5: Increment the indirect access count.

[0053] Step 6: Increment the total commands posted.

[0054] According to an embodiment of the present invention, the algorithm for the read command code comprises the following steps of:

[0055] Step 1: Wait for a pre-determined time interval when total commands posted equal to eight.

[0056] Step 2: Generate a command word and write to a command area pointed in the indirect access count.

[0057] Step 3: Update main control register, where main control register = indirect access count,' 1' (IND bit) and old contents.

[0058] Step 4: Increment the indirect access count.

[0059] Step 5: Increment the total commands posted.

[0060] According to an embodiment of the present invention, the FPGA implementation comprises a hardware description language code for addressing messages when main-status register comes back with command execution. The algorithm illustrating steps involved in the code for addressing messages when main-status register comes back with command execution comprises the steps of:

[0061] Step 1: For Command posted = Read, read data from the command message using Indirect Access count as bucket pointer. Go to step 3.

[0062] Step 2: For Command posted = write, No read/write action needed.

[0063] Step 3: Decrement total commands posted counter;

[0064] Step 4: Increment tail pointer; and

[0065] Step 5: Process the multiple command responses when the indirect access count is greater than the tail pointer.

[0066] According to an embodiment of the present invention, the general mailbox of the system adopts a post-box mechanism to posting the plurality of lower priority messages and events. The general mailbox mechanism is a simplified communication way from a lower-layer (FPGA) to the host for posting bulkier size messages. The messages or events being posted are of 16-bytes or more. Further the message types include protection events, learning and ageing updates and port/flow statistics messages. The messages are posted in a common buffer called a mailbox. These message types are covered under are covered under a single ISR except for protection event messages. Even though the mailbox is configured for indirect access, it is de-coupled from the indirect addressing mode to avoid the head of line blocking for host interface. This implementation helps to reduce the number interrupts generated to host as it combines different type messages under single interface; which in-turn reduces overloading of host.

[0067] According to an embodiment of the present invention, the general mailbox mechanism and the protection mailbox mechanism further provide a common interface to post the messages with a size of 16-bytes or less from FPGA to the control layer. The FPGA updates the total mail-count in the main-status register for their respective message counts whenever, any message is posted in the general mailbox or the protection mailbox. The FPGA further sets the corresponding mailbox bit in the main-status register indicating a new message is posted in a particular mailbox. In case of protection mailbox, an interrupt is generated on arrival of any new message. In case of General mailbox, an interrupt is generated once General mailbox has minimum sixteen messages.

[0068] FIG. 6 illustrates a block diagram indicating a back pressure mechanism applied on the general mailbox and the protection mailbox, according to an embodiment of the present invention. A back pressure is applied to the general mailbox 104 and the protection mailbox 105, whenever the mailboxes get fully occupied. The general mailbox mechanism applies the back pressure to the statistics module 104b and the learning module 104a when the general mailbox 104 is full. The statistics module 104b slowdowns the statistics read operation, when the back pressure is received. Further a new Mac-address learning is put on hold in case of learning module. The ageing module 104a continues to function without any ageing mails posting to the host. All the mails/messages which are not reported to the host are re generated, since the general mailbox 104is not cleared by the host due to on going high priority task. In-case of protection mailbox 105, an internal logic buffers the important protection or event messages in a deep buffer when a back-pressure is applied in the FPGA. The deep buffer hold up to 512 protection messages.

[0069] According to an embodiment of the present invention, the mailbox further comprises an overflow handling and a warm-reboot handling operations. The control layer misses the sync with the lower layer (FPGA), in case of overflow of mailbox or warm-reboot period of a switch. The lower-layer (data plane) interrupts the host to indicate that an overflow is detected and the re-play of messages is required to sync-up with current status in case of mailbox overflow.

G) ADVANTAGES OF THE INVENTION

[0070] The present invention provides a communication between a data plane and a control plane through a mailbox. The system envisaged by the present invention provides efficient technique for accessing and managing a flexible and dynamic data plane. The system disclosed in the present invention further provides an efficient method for accessing the data structures, port and flow statistics, EthOam events, learn and ageing events and the like, which are used heavily in dataplane. The system proposes an indirect addressing mode for accessing event messages posted at the mailbox depending upon their priority. The system further communicates different types of messages to a control layer through a common interface without any additional burden on CPU. The present invention avoids an overloading of network CPU with Interrupt Service Routines (ISR) by stacking the interrupts received from the control plane into postbox based queue.

[0071] Although the embodiments herein are described with various specific embodiments, it will be obvious for a person skilled in the art to practice the invention with modifications. However, all such modifications are deemed to be within the scope of the claims.

[0072] It is also to be understood that the following claims are intended to cover all of the generic and specific features of the embodiments described herein and all the statements of the scope of the embodiments which as a matter of language might be said to fall there between.

CLAIMS

What is claimed is:

1. A method for providing communication between a data plane and a control plane through post-box mechanism based communication interface implemented in FPGA, the method comprising: providing a common interface between the control plane and data plane for exchanging one or more messages; transmitting one or more messages by the control plane to the data plane for accessing data structures; configuring a post-box to receive one or more messages simultaneously from the control plane; dividing an address space into at-least two segments for handling different type of messages to a lower-layer; adopting a direct addressing mode for addressing higher priority messages, and wherein the higher priority messages comprises control, status and debug registers, and wherein the higher priority messages are modified independently which do not interrupt the normal processing operation of a switch; and adopting an indirect addressing mode for addressing low priority messages, and wherein the low priority messages comprises graceful, arbitrated and slow updates, and wherein indirect addressing mode provides a queue to the control layer for addressing low priority messages, and wherein the control layer is allowed to post multiple indirect access commands so that a host interface is not blocked because of single arbitrated update.

2. The method according to claim 1, wherein the indirect addressing mode posts one or more indirect addressing commands for addressing low priority messages, and wherein the posting of one or more indirect addressing commands comprises the steps of: storing head and tail bucket comprising a bin number and number of commands posted to avoid any overwrites by the host; allowing a host to post maximum of eight commands at any given time; passing both data bins and command bins simultaneously for write operations, and advising the host to write the data bins before writing the command bins; updating a posting to the command bins and data bins, and wherein the host updates a main-control register with an Indirect Access bit (IND) and the indirect access count equal to number of commands posted by the host; updating a posting to the main-control register, and considering the head of the bucket/bin as 'Indirect access count' in the Main-Control register by the FPGA; generating a response through a Main-Status register by updating the indirect access count once the command is processed; generating an interrupt for the Main-Status register or using polling method by the host to avoid un-necessary interrupts; posting an indirect command processing, and wherein the tail of the bucket/bin 'Indirect access count' is updated in the Main-Status register; and an indication is provided to notify that no commands are present in the bins on power-up or hard-reset, and wherein the no commands in the bin is indicated by initializing the Indirect access count to a preset value and wherein the preset value is "3"bl 11".

3. The method according to claim 1 further comprises providing one or more pseudo codes for handling indirect addressing commands, and wherein the pseudo code comprises a write command, and a read command.

4. The method according to claim 3, wherein a step of providing the write command comprises the steps of: waiting for a pre-determined time interval when total commands posted equal to eight; copying a data to a data bucket of the indirect access count; generating a command word, and writing the generated command word to the control area of the bucket in the indirect access count, and wherein the writing command comprises at-least three writes for a CPU, and wherein the CPU has any one of 8 bits, 16 bits, 32 bits and 64 bits. Updating a main control register, and wherein the updating of the main control register comprises updating indirect access count and ' 1' (IND bit) and old contents; updating the indirect access count; and updating the total commands posted.

5. The method according to claim 3, wherein the step of providing the read command comprises the steps of: waiting for a pre-determined time interval when total commands posted equal to eight; generating a command word, and writing the generated command word to a command area pointed in the indirect access count; updating a main control register, and wherein the updating of the main ontrol register comprises updating the indirect access count, ' 1' (IND bit) and old contents; updating the indirect access count; and indirect access count the total commands posted.

6. The method according to claim 3 further comprises writing one or more pseudo codes for addressing the messages when main-status register comes back with command execution, and wherein writing the pseudo code comprises the steps of: reading the data for the entire size using the indirect access count as bucket pointer when command posted was read; and performing no read/write action when the command posted was write; updating total commands posted counter; updating the tail pointer; and processing multiple command responses when the indirect access count is greater than the tail pointer.

7. The method according to claim 1 further comprises a general mailbox mechanism and a protection mailbox mechanism.

8. The method according to claim 7, wherein the general mailbox mechanism is a simplified communication way from a lower-layer (FPGA) to the host for posting bulkier size messages, and wherein the of the messages is 16-byte or more, and wherein the message types includes protection events, learning and ageing updates and port/flow statistics messages, and wherein the messages are posted in a common buffer called a mailbox, and wherein except for protection event messages, all the message types are covered under a single ISR.

9. The method according to claim 7, wherein the general mailbox mechanism and the protection mailbox mechanism provides a common interface to post the messages of size 16-bytes or less from FPGA to the control layer, and wherein the FPGA updates the total mail-count in the main-status register for their respective message counts whenever, any message is posted in the general mailbox or the protection mailbox, and wherein the FPGA further sets the corresponding mailbox bit in the main-status register indicating a new message is posted in a particular mailbox.

10. The method according to claim 7, wherein an interrupt is generated on arrival of new message in case of protection mailbox, and wherein an interrupt is generated once a general mailbox has minimum sixteen messages in case of general mailbox.

11. The method according to claim 7, wherein the method of operating the general mailbox mechanism comprises the steps of: applying a Back-pressure to the statistics module and the learning module when the general mailbox goes full; slowing-down the statistics read operation in the statistics module; putting a new Mac-address learning on hold in case of learning module; operating the ageing module continuously to function without posting any ageing mails to the host; and re-generating all the mails/messages which are not reported to the host since the general mailbox is not cleared by the host due to an on-going high priority task.

12. The method according to claim 7, wherein an internal logic buffers the important protection or event messages in a deep buffer when a back pressure is applied in the FPGA in case of the protection mailbox mechanism, and wherein the deep buffer hold up to 512 protection messages.

13. The method according to claim 1, wherein the mailbox mechanism is configured to carry out an overflow handling operation and a warm-reboot handling operation, and wherein the control layer misses the sync with the lower layer (FPGA), in case of overflow of mailbox or warm-reboot period of a switch, and wherein the lower-layer interrupts the host indicating an overflow is detected and re-play of messages is required to sync-up with current status in case of mailbox overflow.

14. A system for providing communication between a data plane and a control plane through a post-box based mechanism implemented in FPGA, the system comprising: a host interface; a direct access register map module, and wherein the direct access register map module comprises a control register, a status register and a debug register; an indirect access register map module, and wherein the indirect access register map module comprises a FGPA internal memory bocks and external memory bocks for handling graceful, arbitrated and slow updates, and wherein the indirect access register map module comprises a queue to control layer to address the graceful or arbitrated updates; a general mailbox, and wherein the general mailbox comprises a hardware learning or aging module and a port and flow statistics module for handling protection events, learning and ageing updates and port/flow statistics messages; and
a priority or protection mailbox, and wherein the priority or protection mailbox comprises one or more Ethernet Operation and Administration (EthOAM) modules for handling one or more protection messages, and wherein the common mailbox interface address the over-loading of the Control layer because of too many interrupts to CPU.